From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D6B3C433F5 for ; Wed, 8 Dec 2021 05:59:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wdcWvPjlruDcBLaeEa+zxw4OEkpfCgMwVCbOfj8zsr4=; b=ISLGw6OrF8lrpv PWJsOI8xX94R9hIjJvnDoZfEf3/2DZMq2532Dv8u3Z6l52O2D0I6HiizVs/IWfb7kQBbrYhz4+gpO muL00Q7FUFBMFnU99xKKFvZB9SNlJEzebIIHCpBhZZxbK4394a98IWTQs10ny/ERXBeOFtBAqB5o/ Etfm1Y0hmEfzWuerBTaKY6YYEiZ1LLolTEg9PezJzEHm09xlo8Aqtfl4Ug6WdfdBrTWp9EiQY8cgj dnGmpTEKZRbe9W5mTzrNGLJTZZlvYTAaCrEdh+rAPr6E7SRQj5tVQId+w3+sE7h6rK2F95ONKCmE2 ZYAI8UbAZz1vFKDElpIA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mupxl-00BPzJ-Rg; Wed, 08 Dec 2021 05:57:58 +0000 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mupxh-00BPyC-42 for linux-arm-kernel@lists.infradead.org; Wed, 08 Dec 2021 05:57:54 +0000 Received: by mail-pf1-x42a.google.com with SMTP id k26so1505250pfp.10 for ; Tue, 07 Dec 2021 21:57:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=4xExbZbYSIl7+isCfcQ0r5xhwgvFT61AQ+ndN1ml1Rc=; b=gT29oLzeevjk6z2PGvpVuz1CA/d+35zpdtN/kx3V68ESfFYMvuA4f+DwmzKe1mvAAK 8UnUgGL2KXP5jh6lrP0BWNN0c/nAJEL2dCbm4ccWU8/EIMUpSMU/iQ/bgYUkG31+WwHP AZE4Vt//VAgpw53JVEs4EVZowhpqWiLO/UcfvIXH6Bmu/Tt7ShhBPoXabWXCRPimCB1v E8Vy7DPBtNGAfxPu9KbTbLubB/2f4q4478kVOrPyEpuHqlkGcIV/tCCyLOl/zArgHU+6 QACq/3M6mBg/hqlOUWB2psEFGAs8MEPcMUFTBc2/oDAZGMrRaL2tek3cf5PFc7YA6OEL M7Eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=4xExbZbYSIl7+isCfcQ0r5xhwgvFT61AQ+ndN1ml1Rc=; b=IHVZBk9ACf3OZS1LVn8iXvQMnDVZG1Fu6AAmvRZD9lQdGVzJMt6GxQbMvAMsMWx9ls VGaDitN/JzRaIrkQtfHBM00NmwL37el+P7RL5fuqjZOLDyHPe0pUBTNO8G4gQLJjU12A TXmtZxqB9T3PYdCgJhOAMtihTHMH/M01Li3Bnh0Jm5hj/CzcvylgitBMrwnRqeIZINZ4 wEICc4TRWngH3Dp3S+0yTpMxRW2jcHqso1dde7CsEWMY7fB5N5kPtjLKy+O+cAzvTUhe U+2Qb5qUmi7YcvN6qyDpsllVydf4M/Qrzt4TcYiBL/oF3z5H1qV4JXmXetceh7cUM9FX cZYg== X-Gm-Message-State: AOAM532OwULYtCj/sFCKMnmyK5o4fWXX1/RXN0lc5Y3KaomFhlYltNmS 1vvEVD+8CeRagmZUrdbs6sgyl4myYwjwprQd8hHpiQ== X-Google-Smtp-Source: ABdhPJxog3kPZtqJ6petGP4FrRVJyn+G9uTEaIlF+0dV7QE4Gz49Ro7vWeaKxcvnSunSmfngitcgU7s1ur1MH/sH+2w= X-Received: by 2002:a63:8b42:: with SMTP id j63mr27984759pge.514.1638943069917; Tue, 07 Dec 2021 21:57:49 -0800 (PST) MIME-Version: 1.0 References: <20211117064359.2362060-1-reijiw@google.com> <20211117064359.2362060-3-reijiw@google.com> <9f6e8b7e-c2b3-5883-f934-5b537c4ce19b@redhat.com> In-Reply-To: From: Reiji Watanabe Date: Tue, 7 Dec 2021 21:57:33 -0800 Message-ID: Subject: Re: [RFC PATCH v3 02/29] KVM: arm64: Save ID registers' sanitized value per vCPU To: Eric Auger Cc: Marc Zyngier , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Will Deacon , Peter Shier , Paolo Bonzini , linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211207_215753_194937_FB9C4777 X-CRM114-Status: GOOD ( 36.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Eric, On Tue, Dec 7, 2021 at 1:34 AM Eric Auger wrote: > > Hi Reiji, > > On 12/4/21 2:45 AM, Reiji Watanabe wrote: > > Hi Eric, > > > > On Thu, Dec 2, 2021 at 2:58 AM Eric Auger wrote: > >> > >> Hi Reiji, > >> > >> On 11/17/21 7:43 AM, Reiji Watanabe wrote: > >>> Extend sys_regs[] of kvm_cpu_context for ID registers and save ID > >>> registers' sanitized value in the array for the vCPU at the first > >>> vCPU reset. Use the saved ones when ID registers are read by > >>> userspace (via KVM_GET_ONE_REG) or the guest. > >>> > >>> Signed-off-by: Reiji Watanabe > >>> --- > >>> arch/arm64/include/asm/kvm_host.h | 10 +++++++ > >>> arch/arm64/kvm/sys_regs.c | 43 +++++++++++++++++++------------ > >>> 2 files changed, 37 insertions(+), 16 deletions(-) > >>> > >>> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h > >>> index edbe2cb21947..72db73c79403 100644 > >>> --- a/arch/arm64/include/asm/kvm_host.h > >>> +++ b/arch/arm64/include/asm/kvm_host.h > >>> @@ -146,6 +146,14 @@ struct kvm_vcpu_fault_info { > >>> u64 disr_el1; /* Deferred [SError] Status Register */ > >>> }; > >>> > >>> +/* > >>> + * (Op0, Op1, CRn, CRm, Op2) of ID registers is (3, 0, 0, crm, op2), > >>> + * where 0<=crm<8, 0<=op2<8. > >>> + */ > >>> +#define KVM_ARM_ID_REG_MAX_NUM 64 > >>> +#define IDREG_IDX(id) ((sys_reg_CRm(id) << 3) | sys_reg_Op2(id)) > >>> +#define IDREG_SYS_IDX(id) (ID_REG_BASE + IDREG_IDX(id)) > >>> + > >>> enum vcpu_sysreg { > >>> __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ > >>> MPIDR_EL1, /* MultiProcessor Affinity Register */ > >>> @@ -210,6 +218,8 @@ enum vcpu_sysreg { > >>> CNTP_CVAL_EL0, > >>> CNTP_CTL_EL0, > >>> > >>> + ID_REG_BASE, > >>> + ID_REG_END = ID_REG_BASE + KVM_ARM_ID_REG_MAX_NUM - 1, > >>> /* Memory Tagging Extension registers */ > >>> RGSR_EL1, /* Random Allocation Tag Seed Register */ > >>> GCR_EL1, /* Tag Control Register */ > >>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > >>> index e3ec1a44f94d..5608d3410660 100644 > >>> --- a/arch/arm64/kvm/sys_regs.c > >>> +++ b/arch/arm64/kvm/sys_regs.c > >>> @@ -33,6 +33,8 @@ > >>> > >>> #include "trace.h" > >>> > >>> +static u64 __read_id_reg(const struct kvm_vcpu *vcpu, u32 id); > >>> + > >>> /* > >>> * All of this file is extremely similar to the ARM coproc.c, but the > >>> * types are different. My gut feeling is that it should be pretty > >>> @@ -273,7 +275,7 @@ static bool trap_loregion(struct kvm_vcpu *vcpu, > >>> struct sys_reg_params *p, > >>> const struct sys_reg_desc *r) > >>> { > >>> - u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); > >>> + u64 val = __read_id_reg(vcpu, SYS_ID_AA64MMFR1_EL1); > >>> u32 sr = reg_to_encoding(r); > >>> > >>> if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) { > >>> @@ -1059,17 +1061,9 @@ static bool access_arch_timer(struct kvm_vcpu *vcpu, > >>> return true; > >>> } > >>> > >>> -/* Read a sanitised cpufeature ID register by sys_reg_desc */ > >>> -static u64 read_id_reg(const struct kvm_vcpu *vcpu, > >>> - struct sys_reg_desc const *r, bool raz) > >>> +static u64 __read_id_reg(const struct kvm_vcpu *vcpu, u32 id) > >>> { > >>> - u32 id = reg_to_encoding(r); > >>> - u64 val; > >>> - > >>> - if (raz) > >>> - return 0; > >>> - > >>> - val = read_sanitised_ftr_reg(id); > >>> + u64 val = __vcpu_sys_reg(vcpu, IDREG_SYS_IDX(id)); > >>> > >>> switch (id) { > >>> case SYS_ID_AA64PFR0_EL1: > >>> @@ -1119,6 +1113,14 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, > >>> return val; > >>> } > >>> > >>> +static u64 read_id_reg(const struct kvm_vcpu *vcpu, > >>> + struct sys_reg_desc const *r, bool raz) > >>> +{ > >>> + u32 id = reg_to_encoding(r); > >>> + > >>> + return raz ? 0 : __read_id_reg(vcpu, id); > >>> +} > >>> + > >>> static unsigned int id_visibility(const struct kvm_vcpu *vcpu, > >>> const struct sys_reg_desc *r) > >>> { > >>> @@ -1178,6 +1180,16 @@ static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, > >>> return REG_HIDDEN; > >>> } > >>> > >>> +static void reset_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) > >>> +{ > >>> + u32 id = reg_to_encoding(rd); > >>> + > >>> + if (vcpu_has_reset_once(vcpu)) > >>> + return; > >> The KVM API allows to call VCPU_INIT several times (with same > >> target/feature). With above check on the second call the ID_REGS won't > >> be reset. Somehow this is aligned with target/feature behavior. However > >> if this is what we want, I think we would need to document it in the KVM > >> API doc. > > > > Thank you for the comment. > > > > That is what we want. Since ID registers are read only registers, > > their values must not change across the reset. > > > > '4.82 KVM_ARM_VCPU_INIT' in api.rst says: > > > > System registers: Reset to their architecturally defined > > values as for a warm reset to EL1 (resp. SVC) > > > > Since this reset behavior for the ID registers follows what is > > described above, I'm not sure if we need to document the reset > > behavior of the ID registers specifically. > > If KVM changes the values across the resets, I would think it > > rather needs to be documented though. > > Makes sense to freeze the ID REGs on the 1st reset. Was just wondering > if we shouldn't add that the ID REG values are immutable after the 1st > VCPU_INIT. > Makes sense to freeze the ID REGs on the 1st reset. Was just wondering > if we shouldn't add that the ID REG values are immutable after the 1st > VCPU_INIT. Even after the 1st VCPU_INIT, ID REG values can be changed by KVM_SET_ONE_REG (KVM_SET_ONE_REG/KVM_GET_ONE_REG are allowed only after the 1st VCPU_INIT). The ID REG values are immutable after the 1st KVM_RUN, and I think we should document that. Is that what you meant ? Thanks, Reiji _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel