[PATCH 00/06] ARM: shmobile: SMP Cortex-A9 SCU rework

[PATCH 00/06] ARM: shmobile: SMP Cortex-A9 SCU rework

[Magnus Damm]

ARM: shmobile: SMP Cortex-A9 SCU rework

[PATCH 01/06] ARM: shmobile: Kill off sh73a0 scu_base_addr() function
[PATCH 02/06] ARM: shmobile: Kill off r8a7779 scu_base_addr() function
[PATCH 03/06] ARM: shmobile: Rework EMEV2 scu_base variable
[PATCH 04/06] ARM: shmobile: Move headsmp-sh73a0.S to headsmp-scu.S
[PATCH 05/06] ARM: shmobile: Common shmobile_scu_base in headsmp-scu.S
[PATCH 06/06] ARM: shmobile: Update EMEV2 to use scu_power_mode()

Rework the EMEV2 SMP code to make use of common scu_power_mode()
code together with a shared shmobile_scu_base and early SCU
setup code in headsmp-scu.S.

The patches are known to build for sh73a0, r8a7779 and EMEV2.

Note that the code has only been tested on the KZM9D/EMEV2 board,
and because of that changes to other boards have been kept at
a minimum. Next target after this is to update the r8a7779 SMP/SCU
code to make use of scu_base_addr(), but that requires hardware
access for testing.

Signed-off-by: Magnus Damm <damm@opensource.se>
---

 No known dependencies apart from previous SMP cleanup series
 "[PATCH 00/06] ARM: shmobile: Trivial SMP cleanups"
 Written against -next in renesas.git.

 arch/arm/mach-shmobile/Makefile              |    6 +-
 arch/arm/mach-shmobile/headsmp-scu.S         |   58 +++++++++++++++++++++++++
 arch/arm/mach-shmobile/headsmp-sh73a0.S      |   50 ----------------------
 arch/arm/mach-shmobile/include/mach/common.h |    3 -
 arch/arm/mach-shmobile/smp-emev2.c           |   59 +++++++-------------------
 arch/arm/mach-shmobile/smp-r8a7779.c         |   19 +++-----
 arch/arm/mach-shmobile/smp-sh73a0.c          |   26 +++++------
 7 files changed, 98 insertions(+), 123 deletions(-)

[PATCH 01/06] ARM: shmobile: Kill off sh73a0 scu_base_addr() function

[Magnus Damm]

From: Magnus Damm <damm@opensource.se>

Replace scu_base_addr() with a static shmobile_scu_base
variable and introduce SH73A0_SCU_BASE.

Later in the series the shmobile_scu_base variable will be
made into a global variable so this is preparation only.

Signed-off-by: Magnus Damm <damm@opensource.se>
---

 arch/arm/mach-shmobile/smp-sh73a0.c |   20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

--- 0006/arch/arm/mach-shmobile/smp-sh73a0.c
+++ work/arch/arm/mach-shmobile/smp-sh73a0.c	2013-02-12 23:13:14.000000000 +0900
@@ -39,13 +39,12 @@
 
 #define PSTR_SHUTDOWN_MODE	3
 
-static void __iomem *scu_base_addr(void)
-{
-	return (void __iomem *)0xf0000000;
-}
+#define SH73A0_SCU_BASE IOMEM(0xf0000000)
+
+static void __iomem *shmobile_scu_base;
 
 #ifdef CONFIG_HAVE_ARM_TWD
-static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29);
 void __init sh73a0_register_twd(void)
 {
 	twd_local_timer_register(&twd_local_timer);
@@ -71,21 +70,22 @@ static int __cpuinit sh73a0_boot_seconda
 
 static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
 {
-	scu_enable(scu_base_addr());
+	scu_enable(shmobile_scu_base);
 
 	/* Map the reset vector (in headsmp-sh73a0.S) */
 	__raw_writel(0, APARMBAREA);      /* 4k */
 	__raw_writel(__pa(sh73a0_secondary_vector), SBAR);
 
 	/* enable cache coherency on booting CPU */
-	scu_power_mode(scu_base_addr(), SCU_PM_NORMAL);
+	scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
 }
 
 static void __init sh73a0_smp_init_cpus(void)
 {
-	unsigned int ncores = scu_get_core_count(scu_base_addr());
+	/* setup sh73a0 specific SCU base */
+	shmobile_scu_base = SH73A0_SCU_BASE;
 
-	shmobile_smp_init_cpus(ncores);
+	shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
@@ -121,7 +121,7 @@ static void sh73a0_cpu_die(unsigned int
 	flush_cache_all();
 
 	/* Set power off mode. This takes the CPU out of the MP cluster */
-	scu_power_mode(scu_base_addr(), SCU_PM_POWEROFF);
+	scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
 
 	/* Enter shutdown mode */
 	cpu_do_idle();

[PATCH 01/06] ARM: shmobile: Kill off sh73a0 scu_base_addr() function

[Arnd Bergmann]

On Wednesday 13 February 2013, Magnus Damm wrote:

> -}
> +#define SH73A0_SCU_BASE IOMEM(0xf0000000)
> +
> +static void __iomem *shmobile_scu_base;
>  
>  #ifdef CONFIG_HAVE_ARM_TWD
> -static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
> +static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29);

This is causing a build warning in linux-next:

arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: initialization makes integer from pointer without a cast [enabled by default]
arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: (near initialization for 'twd_local_timer.res[0].start') [enabled by default]
arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: initialization makes integer from pointer without a cast [enabled by default]
/arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: (near initialization for 'twd_local_timer.res[0].end') [enabled by default]

The problem is that DEFINE_TWD_LOCAL_TIMER expects a physical
address to pass into ioremap(), while you are passing
an __iomem token.

	Arnd

[PATCH 01/06] ARM: shmobile: Kill off sh73a0 scu_base_addr() function

[Magnus Damm]

Hi Arnd,

On Sat, Feb 16, 2013 at 9:35 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Wednesday 13 February 2013, Magnus Damm wrote:
>
>> -}
>> +#define SH73A0_SCU_BASE IOMEM(0xf0000000)
>> +
>> +static void __iomem *shmobile_scu_base;
>>
>>  #ifdef CONFIG_HAVE_ARM_TWD
>> -static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
>> +static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29);
>
> This is causing a build warning in linux-next:
>
> arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: initialization makes integer from pointer without a cast [enabled by default]
> arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: (near initialization for 'twd_local_timer.res[0].start') [enabled by default]
> arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: initialization makes integer from pointer without a cast [enabled by default]
> /arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: (near initialization for 'twd_local_timer.res[0].end') [enabled by default]
>
> The problem is that DEFINE_TWD_LOCAL_TIMER expects a physical
> address to pass into ioremap(), while you are passing
> an __iomem token.

Thanks, will fix up.

/ magnus

[PATCH 02/06] ARM: shmobile: Kill off r8a7779 scu_base_addr() function

[Magnus Damm]

From: Magnus Damm <damm@opensource.se>

Replace scu_base_addr() with a static shmobile_scu_base
variable and introduce R8A7779_SCU_BASE.

Later in the series the shmobile_scu_base variable will be
made into a global variable so this is preparation only.

Signed-off-by: Magnus Damm <damm@opensource.se>
---

 arch/arm/mach-shmobile/smp-r8a7779.c |   17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

--- 0001/arch/arm/mach-shmobile/smp-r8a7779.c
+++ work/arch/arm/mach-shmobile/smp-r8a7779.c	2013-02-13 20:52:34.000000000 +0900
@@ -31,6 +31,9 @@
 #include <asm/smp_twd.h>
 
 #define AVECR IOMEM(0xfe700040)
+#define R8A7779_SCU_BASE IOMEM(0xf0000000)
+
+static void __iomem *shmobile_scu_base;
 
 static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
 	.chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
@@ -56,11 +59,6 @@ static struct r8a7779_pm_ch *r8a7779_ch_
 	[3] = &r8a7779_ch_cpu3,
 };
 
-static void __iomem *scu_base_addr(void)
-{
-	return (void __iomem *)0xf0000000;
-}
-
 static DEFINE_SPINLOCK(scu_lock);
 static unsigned long tmp;
 
@@ -75,7 +73,7 @@ void __init r8a7779_register_twd(void)
 
 static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
 {
-	void __iomem *scu_base = scu_base_addr();
+	void __iomem *scu_base = shmobile_scu_base;
 
 	spin_lock(&scu_lock);
 	tmp = __raw_readl(scu_base + 8);
@@ -153,7 +151,7 @@ static void __init r8a7779_smp_prepare_c
 {
 	int cpu = cpu_logical_map(0);
 
-	scu_enable(scu_base_addr());
+	scu_enable(shmobile_scu_base);
 
 	/* Map the reset vector (in headsmp.S) */
 	__raw_writel(__pa(shmobile_secondary_vector), AVECR);
@@ -171,9 +169,10 @@ static void __init r8a7779_smp_prepare_c
 
 static void __init r8a7779_smp_init_cpus(void)
 {
-	unsigned int ncores = scu_get_core_count(scu_base_addr());
+	/* setup r8a7779 specific SCU base */
+	shmobile_scu_base = R8A7779_SCU_BASE;
 
-	shmobile_smp_init_cpus(ncores);
+	shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
 }
 
 struct smp_operations r8a7779_smp_ops  __initdata = {

[PATCH 03/06] ARM: shmobile: Rework EMEV2 scu_base variable

[Magnus Damm]

From: Magnus Damm <damm@opensource.se>

Rename the static scu_base variable into shmobile_scu_base.

Later in the series the shmobile_scu_base variable will be
made into a global variable so this is preparation only.

Signed-off-by: Magnus Damm <damm@opensource.se>
---

 arch/arm/mach-shmobile/smp-emev2.c |   15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

--- 0001/arch/arm/mach-shmobile/smp-emev2.c
+++ work/arch/arm/mach-shmobile/smp-emev2.c	2013-02-13 21:01:25.000000000 +0900
@@ -32,8 +32,9 @@
 
 #define EMEV2_SCU_BASE 0x1e000000
 
+static void __iomem *shmobile_scu_base;
+
 static DEFINE_SPINLOCK(scu_lock);
-static void __iomem *scu_base;
 
 static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
 {
@@ -42,10 +43,10 @@ static void modify_scu_cpu_psr(unsigned
 	/* we assume this code is running on a different cpu
 	 * than the one that is changing coherency setting */
 	spin_lock(&scu_lock);
-	tmp = readl(scu_base + 8);
+	tmp = readl(shmobile_scu_base + 8);
 	tmp &= ~clr;
 	tmp |= set;
-	writel(tmp, scu_base + 8);
+	writel(tmp, shmobile_scu_base + 8);
 	spin_unlock(&scu_lock);
 
 }
@@ -70,7 +71,7 @@ static void __init emev2_smp_prepare_cpu
 {
 	int cpu = cpu_logical_map(0);
 
-	scu_enable(scu_base);
+	scu_enable(shmobile_scu_base);
 
 	/* Tell ROM loader about our vector (in headsmp.S) */
 	emev2_set_boot_vector(__pa(shmobile_secondary_vector));
@@ -83,12 +84,12 @@ static void __init emev2_smp_init_cpus(v
 {
 	unsigned int ncores;
 
-	if (!scu_base) {
-		scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
+	if (!shmobile_scu_base) {
+		shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
 		emev2_clock_init(); /* need ioremapped SMU */
 	}
 
-	ncores = scu_base ? scu_get_core_count(scu_base) : 1;
+	ncores = shmobile_scu_base ? scu_get_core_count(shmobile_scu_base) : 1;
 
 	shmobile_smp_init_cpus(ncores);
 }

[PATCH 04/06] ARM: shmobile: Move headsmp-sh73a0.S to headsmp-scu.S

[Magnus Damm]

From: Magnus Damm <damm@opensource.se>

Rename headsmp-sh73a0.S into headsmp-scu.S and
introduce shmobile_secondary_vector_scu().

The goal is to be able to share the function
above between all mach-shmobile SoCs that use
SCU for SMP. So far only sh73a0 use this.

At this time the SCU base address is still hard
coded in headsmp-scu.S to 0xf0000000, but this
will be changed in the future.

Signed-off-by: Magnus Damm <damm@opensource.se>
---

 Hum, perhaps git can generate a better patch with "rename" information?

 arch/arm/mach-shmobile/Makefile              |    2 -
 arch/arm/mach-shmobile/headsmp-scu.S         |   50 ++++++++++++++++++++++++++
 arch/arm/mach-shmobile/headsmp-sh73a0.S      |   50 --------------------------
 arch/arm/mach-shmobile/include/mach/common.h |    2 -
 arch/arm/mach-shmobile/smp-sh73a0.c          |    4 +-
 5 files changed, 54 insertions(+), 54 deletions(-)

--- 0001/arch/arm/mach-shmobile/Makefile
+++ work/arch/arm/mach-shmobile/Makefile	2013-02-05 18:23:20.000000000 +0900
@@ -15,7 +15,7 @@ obj-$(CONFIG_ARCH_EMEV2)	+= setup-emev2.
 # SMP objects
 smp-y				:= platsmp.o headsmp.o
 smp-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
-smp-$(CONFIG_ARCH_SH73A0)	+= smp-sh73a0.o headsmp-sh73a0.o
+smp-$(CONFIG_ARCH_SH73A0)	+= smp-sh73a0.o headsmp-scu.o
 smp-$(CONFIG_ARCH_R8A7779)	+= smp-r8a7779.o
 smp-$(CONFIG_ARCH_EMEV2)	+= smp-emev2.o
 
--- /dev/null
+++ work/arch/arm/mach-shmobile/headsmp-scu.S	2013-02-05 18:23:21.000000000 +0900
@@ -0,0 +1,50 @@
+/*
+ * Shared SCU setup for mach-shmobile
+ *
+ * Copyright (C) 2012 Bastian Hecht
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/memory.h>
+
+	__CPUINIT
+/*
+ * Reset vector for secondary CPUs.
+ *
+ * First we turn on L1 cache coherency for our CPU. Then we jump to
+ * shmobile_invalidate_start that invalidates the cache and hands over control
+ * to the common ARM startup code.
+ * This function will be mapped to address 0 by the SBAR register.
+ * A normal branch is out of range here so we need a long jump. We jump to
+ * the physical address as the MMU is still turned off.
+ */
+	.align	12
+ENTRY(shmobile_secondary_vector_scu)
+	mrc     p15, 0, r0, c0, c0, 5	@ read MIPDR
+	and	r0, r0, #3		@ mask out cpu ID
+	lsl	r0, r0, #3		@ we will shift by cpu_id * 8 bits
+	mov	r1, #0xf0000000		@ SCU base address
+	ldr	r2, [r1, #8]		@ SCU Power Status Register
+	mov	r3, #3
+	bic	r2, r2, r3, lsl r0	@ Clear bits of our CPU (Run Mode)
+	str	r2, [r1, #8]		@ write back
+
+	ldr	pc, 1f
+1:	.long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
+ENDPROC(shmobile_secondary_vector_scu)
--- 0001/arch/arm/mach-shmobile/headsmp-sh73a0.S
+++ /dev/null	2013-01-21 13:48:16.387453344 +0900
@@ -1,50 +0,0 @@
-/*
- * SMP support for SoC sh73a0
- *
- * Copyright (C) 2012 Bastian Hecht
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/memory.h>
-
-	__CPUINIT
-/*
- * Reset vector for secondary CPUs.
- *
- * First we turn on L1 cache coherency for our CPU. Then we jump to
- * shmobile_invalidate_start that invalidates the cache and hands over control
- * to the common ARM startup code.
- * This function will be mapped to address 0 by the SBAR register.
- * A normal branch is out of range here so we need a long jump. We jump to
- * the physical address as the MMU is still turned off.
- */
-	.align	12
-ENTRY(sh73a0_secondary_vector)
-	mrc     p15, 0, r0, c0, c0, 5	@ read MIPDR
-	and	r0, r0, #3		@ mask out cpu ID
-	lsl	r0, r0, #3		@ we will shift by cpu_id * 8 bits
-	mov	r1, #0xf0000000		@ SCU base address
-	ldr	r2, [r1, #8]		@ SCU Power Status Register
-	mov	r3, #3
-	bic	r2, r2, r3, lsl r0	@ Clear bits of our CPU (Run Mode)
-	str	r2, [r1, #8]		@ write back
-
-	ldr	pc, 1f
-1:	.long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
-ENDPROC(sh73a0_secondary_vector)
--- 0001/arch/arm/mach-shmobile/include/mach/common.h
+++ work/arch/arm/mach-shmobile/include/mach/common.h	2013-02-05 18:29:43.000000000 +0900
@@ -8,6 +8,7 @@ extern void shmobile_setup_delay(unsigne
 struct twd_local_timer;
 extern void shmobile_setup_console(void);
 extern void shmobile_secondary_vector(void);
+extern void shmobile_secondary_vector_scu(void);
 struct clk;
 extern int shmobile_clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
@@ -45,7 +46,6 @@ extern void sh73a0_add_standard_devices_
 extern void sh73a0_clock_init(void);
 extern void sh73a0_pinmux_init(void);
 extern void sh73a0_pm_init(void);
-extern void sh73a0_secondary_vector(void);
 extern struct clk sh73a0_extal1_clk;
 extern struct clk sh73a0_extal2_clk;
 extern struct clk sh73a0_extcki_clk;
--- 0001/arch/arm/mach-shmobile/smp-sh73a0.c
+++ work/arch/arm/mach-shmobile/smp-sh73a0.c	2013-02-05 18:23:20.000000000 +0900
@@ -80,9 +80,9 @@ static void __init sh73a0_smp_prepare_cp
 {
 	scu_enable(scu_base_addr());
 
-	/* Map the reset vector (in headsmp-sh73a0.S) */
+	/* Map the reset vector (in headsmp-scu.S) */
 	__raw_writel(0, APARMBAREA);      /* 4k */
-	__raw_writel(__pa(sh73a0_secondary_vector), SBAR);
+	__raw_writel(__pa(shmobile_secondary_vector_scu), SBAR);
 
 	/* enable cache coherency on booting CPU */
 	scu_power_mode(scu_base_addr(), SCU_PM_NORMAL);

[PATCH 05/06] ARM: shmobile: Common shmobile_scu_base in headsmp-scu.S

[Magnus Damm]

From: Magnus Damm <damm@opensource.se>

Update the code in headsmp-scu.S to use a global
shmobile_scu_base variable both for convenient SCU
base address storage and for the early SCU setup
code in shmobile_secondary_vector_scu.

With this patch applied r8a7779, sh73a0 and EMEV2
all make use of the global shmobile_scu_base
variable. However only sh73a0 makes use of the SCU
bring up code in shmobile_secondary_vector_scu.

Signed-off-by: Magnus Damm <damm@opensource.se>
---

 arch/arm/mach-shmobile/Makefile              |    4 ++--
 arch/arm/mach-shmobile/headsmp-scu.S         |    8 +++++++-
 arch/arm/mach-shmobile/include/mach/common.h |    1 +
 arch/arm/mach-shmobile/smp-emev2.c           |    2 --
 arch/arm/mach-shmobile/smp-r8a7779.c         |    2 --
 arch/arm/mach-shmobile/smp-sh73a0.c          |    2 --
 6 files changed, 10 insertions(+), 9 deletions(-)

--- 0009/arch/arm/mach-shmobile/Makefile
+++ work/arch/arm/mach-shmobile/Makefile	2013-02-13 21:54:34.000000000 +0900
@@ -16,8 +16,8 @@ obj-$(CONFIG_ARCH_EMEV2)	+= setup-emev2.
 smp-y				:= platsmp.o headsmp.o
 smp-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
 smp-$(CONFIG_ARCH_SH73A0)	+= smp-sh73a0.o headsmp-scu.o
-smp-$(CONFIG_ARCH_R8A7779)	+= smp-r8a7779.o
-smp-$(CONFIG_ARCH_EMEV2)	+= smp-emev2.o
+smp-$(CONFIG_ARCH_R8A7779)	+= smp-r8a7779.o headsmp-scu.o
+smp-$(CONFIG_ARCH_EMEV2)	+= smp-emev2.o headsmp-scu.o
 
 # IRQ objects
 obj-$(CONFIG_ARCH_SH7372)	+= entry-intc.o
--- 0009/arch/arm/mach-shmobile/headsmp-scu.S
+++ work/arch/arm/mach-shmobile/headsmp-scu.S	2013-02-13 21:54:27.000000000 +0900
@@ -39,7 +39,8 @@ ENTRY(shmobile_secondary_vector_scu)
 	mrc     p15, 0, r0, c0, c0, 5	@ read MIPDR
 	and	r0, r0, #3		@ mask out cpu ID
 	lsl	r0, r0, #3		@ we will shift by cpu_id * 8 bits
-	mov	r1, #0xf0000000		@ SCU base address
+	ldr	r1, =shmobile_scu_base
+	ldr	r1, [r1]		@ SCU base address
 	ldr	r2, [r1, #8]		@ SCU Power Status Register
 	mov	r3, #3
 	bic	r2, r2, r3, lsl r0	@ Clear bits of our CPU (Run Mode)
@@ -48,3 +49,8 @@ ENTRY(shmobile_secondary_vector_scu)
 	ldr	pc, 1f
 1:	.long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
 ENDPROC(shmobile_secondary_vector_scu)
+
+	.text
+	.globl	shmobile_scu_base
+shmobile_scu_base:
+	.space	4
--- 0009/arch/arm/mach-shmobile/include/mach/common.h
+++ work/arch/arm/mach-shmobile/include/mach/common.h	2013-02-13 21:54:27.000000000 +0900
@@ -96,6 +96,7 @@ extern int shmobile_cpu_is_dead(unsigned
 static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; }
 #endif
 
+extern void __iomem *shmobile_scu_base;
 extern void shmobile_smp_init_cpus(unsigned int ncores);
 
 static inline void __init shmobile_init_late(void)
--- 0008/arch/arm/mach-shmobile/smp-emev2.c
+++ work/arch/arm/mach-shmobile/smp-emev2.c	2013-02-13 21:54:27.000000000 +0900
@@ -32,8 +32,6 @@
 
 #define EMEV2_SCU_BASE 0x1e000000
 
-static void __iomem *shmobile_scu_base;
-
 static DEFINE_SPINLOCK(scu_lock);
 
 static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
--- 0007/arch/arm/mach-shmobile/smp-r8a7779.c
+++ work/arch/arm/mach-shmobile/smp-r8a7779.c	2013-02-13 21:54:27.000000000 +0900
@@ -33,8 +33,6 @@
 #define AVECR IOMEM(0xfe700040)
 #define R8A7779_SCU_BASE IOMEM(0xf0000000)
 
-static void __iomem *shmobile_scu_base;
-
 static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
 	.chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
 	.chan_bit = 1, /* ARM1 */
--- 0009/arch/arm/mach-shmobile/smp-sh73a0.c
+++ work/arch/arm/mach-shmobile/smp-sh73a0.c	2013-02-13 21:54:27.000000000 +0900
@@ -41,8 +41,6 @@
 
 #define SH73A0_SCU_BASE IOMEM(0xf0000000)
 
-static void __iomem *shmobile_scu_base;
-
 #ifdef CONFIG_HAVE_ARM_TWD
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29);
 void __init sh73a0_register_twd(void)

[PATCH 05/06] ARM: shmobile: Common shmobile_scu_base in headsmp-scu.S

[Bastian Hecht]

Hi,

this breaks the secondary CPU startup when I test it. I think you
can't access shmobile_scu_address this way with the MMU still turned
off.

But instead of
> +       ldr     r1, =shmobile_scu_base
> +       ldr     r1, [r1]                @ SCU base address

try

+        mrc     p15, 4, r1, c15, c0, 0 @ get SCU base address

to get it from the coprocessor.

Cheers,

 Bastian


2013/2/13 Magnus Damm <magnus.damm@gmail.com>:
> From: Magnus Damm <damm@opensource.se>
>
> Update the code in headsmp-scu.S to use a global
> shmobile_scu_base variable both for convenient SCU
> base address storage and for the early SCU setup
> code in shmobile_secondary_vector_scu.
>
> With this patch applied r8a7779, sh73a0 and EMEV2
> all make use of the global shmobile_scu_base
> variable. However only sh73a0 makes use of the SCU
> bring up code in shmobile_secondary_vector_scu.
>
> Signed-off-by: Magnus Damm <damm@opensource.se>
> ---
>
>  arch/arm/mach-shmobile/Makefile              |    4 ++--
>  arch/arm/mach-shmobile/headsmp-scu.S         |    8 +++++++-
>  arch/arm/mach-shmobile/include/mach/common.h |    1 +
>  arch/arm/mach-shmobile/smp-emev2.c           |    2 --
>  arch/arm/mach-shmobile/smp-r8a7779.c         |    2 --
>  arch/arm/mach-shmobile/smp-sh73a0.c          |    2 --
>  6 files changed, 10 insertions(+), 9 deletions(-)
>
> --- 0009/arch/arm/mach-shmobile/Makefile
> +++ work/arch/arm/mach-shmobile/Makefile        2013-02-13 21:54:34.000000000 +0900
> @@ -16,8 +16,8 @@ obj-$(CONFIG_ARCH_EMEV2)      += setup-emev2.
>  smp-y                          := platsmp.o headsmp.o
>  smp-$(CONFIG_HOTPLUG_CPU)      += hotplug.o
>  smp-$(CONFIG_ARCH_SH73A0)      += smp-sh73a0.o headsmp-scu.o
> -smp-$(CONFIG_ARCH_R8A7779)     += smp-r8a7779.o
> -smp-$(CONFIG_ARCH_EMEV2)       += smp-emev2.o
> +smp-$(CONFIG_ARCH_R8A7779)     += smp-r8a7779.o headsmp-scu.o
> +smp-$(CONFIG_ARCH_EMEV2)       += smp-emev2.o headsmp-scu.o
>
>  # IRQ objects
>  obj-$(CONFIG_ARCH_SH7372)      += entry-intc.o
> --- 0009/arch/arm/mach-shmobile/headsmp-scu.S
> +++ work/arch/arm/mach-shmobile/headsmp-scu.S   2013-02-13 21:54:27.000000000 +0900
> @@ -39,7 +39,8 @@ ENTRY(shmobile_secondary_vector_scu)
>         mrc     p15, 0, r0, c0, c0, 5   @ read MIPDR
>         and     r0, r0, #3              @ mask out cpu ID
>         lsl     r0, r0, #3              @ we will shift by cpu_id * 8 bits
> -       mov     r1, #0xf0000000         @ SCU base address
> +       ldr     r1, =shmobile_scu_base
> +       ldr     r1, [r1]                @ SCU base address
>         ldr     r2, [r1, #8]            @ SCU Power Status Register
>         mov     r3, #3
>         bic     r2, r2, r3, lsl r0      @ Clear bits of our CPU (Run Mode)
> @@ -48,3 +49,8 @@ ENTRY(shmobile_secondary_vector_scu)
>         ldr     pc, 1f
>  1:     .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
>  ENDPROC(shmobile_secondary_vector_scu)
> +
> +       .text
> +       .globl  shmobile_scu_base
> +shmobile_scu_base:
> +       .space  4
> --- 0009/arch/arm/mach-shmobile/include/mach/common.h
> +++ work/arch/arm/mach-shmobile/include/mach/common.h   2013-02-13 21:54:27.000000000 +0900
> @@ -96,6 +96,7 @@ extern int shmobile_cpu_is_dead(unsigned
>  static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; }
>  #endif
>
> +extern void __iomem *shmobile_scu_base;
>  extern void shmobile_smp_init_cpus(unsigned int ncores);
>
>  static inline void __init shmobile_init_late(void)
> --- 0008/arch/arm/mach-shmobile/smp-emev2.c
> +++ work/arch/arm/mach-shmobile/smp-emev2.c     2013-02-13 21:54:27.000000000 +0900
> @@ -32,8 +32,6 @@
>
>  #define EMEV2_SCU_BASE 0x1e000000
>
> -static void __iomem *shmobile_scu_base;
> -
>  static DEFINE_SPINLOCK(scu_lock);
>
>  static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
> --- 0007/arch/arm/mach-shmobile/smp-r8a7779.c
> +++ work/arch/arm/mach-shmobile/smp-r8a7779.c   2013-02-13 21:54:27.000000000 +0900
> @@ -33,8 +33,6 @@
>  #define AVECR IOMEM(0xfe700040)
>  #define R8A7779_SCU_BASE IOMEM(0xf0000000)
>
> -static void __iomem *shmobile_scu_base;
> -
>  static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
>         .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
>         .chan_bit = 1, /* ARM1 */
> --- 0009/arch/arm/mach-shmobile/smp-sh73a0.c
> +++ work/arch/arm/mach-shmobile/smp-sh73a0.c    2013-02-13 21:54:27.000000000 +0900
> @@ -41,8 +41,6 @@
>
>  #define SH73A0_SCU_BASE IOMEM(0xf0000000)
>
> -static void __iomem *shmobile_scu_base;
> -
>  #ifdef CONFIG_HAVE_ARM_TWD
>  static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29);
>  void __init sh73a0_register_twd(void)
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 05/06] ARM: shmobile: Common shmobile_scu_base in headsmp-scu.S

[Magnus Damm]

Hello Bastian,

On Mon, Feb 18, 2013 at 7:20 AM, Bastian Hecht <hechtb@gmail.com> wrote:
> Hi,
>
> this breaks the secondary CPU startup when I test it. I think you
> can't access shmobile_scu_address this way with the MMU still turned
> off.
>
> But instead of
>> +       ldr     r1, =shmobile_scu_base
>> +       ldr     r1, [r1]                @ SCU base address
>
> try
>
> +        mrc     p15, 4, r1, c15, c0, 0 @ get SCU base address
>
> to get it from the coprocessor.

Thanks. Can you please let us know which platform you see this?

I've executed this on sh73a0 and KZM9G myself without any issues.

Could it be that you are powering down the power domain in your own code?

Thanks,

/ magnus

[PATCH 05/06] ARM: shmobile: Common shmobile_scu_base in headsmp-scu.S

[Bastian Hecht]

Hi,

2013/2/17 Magnus Damm <magnus.damm@gmail.com>:
> Hello Bastian,
>
> On Mon, Feb 18, 2013 at 7:20 AM, Bastian Hecht <hechtb@gmail.com> wrote:
>> Hi,
>>
>> this breaks the secondary CPU startup when I test it. I think you
>> can't access shmobile_scu_address this way with the MMU still turned
>> off.
>>
>> But instead of
>>> +       ldr     r1, =shmobile_scu_base
>>> +       ldr     r1, [r1]                @ SCU base address
>>
>> try
>>
>> +        mrc     p15, 4, r1, c15, c0, 0 @ get SCU base address
>>
>> to get it from the coprocessor.
>
> Thanks. Can you please let us know which platform you see this?
>
> I've executed this on sh73a0 and KZM9G myself without any issues.
>
> Could it be that you are powering down the power domain in your own code?

I saw it on the current HEAD of the next branch using my KZM9G. I
bisected it down to your commit. The problem appears right at boot
time when the 2nd CPU should be brought up.

Thanks,

 Bastian


> Thanks,
>
> / magnus

[PATCH 06/06] ARM: shmobile: Update EMEV2 to use scu_power_mode()

[Magnus Damm]

From: Magnus Damm <damm@opensource.se>

Update the SMP code for EMEV2 to make use of the
shared SCU function scu_power_mode() together with
the early setup code in shmobile_secondary_vector_scu.

With this patch in place the secondary CPUs modify the
SCU setting during early boot instead of letting other
CPUs deal with the coherency setting before boot. In
other words, we used to setup coherency before boot
in emev2_boot_secondary() but that bit is now instead
handled by the code in shmobile_secondary_vector_scu.

Signed-off-by: Magnus Damm <damm@opensource.se>
---

 Tested on the EMEV2/KZM9D board.

 arch/arm/mach-shmobile/smp-emev2.c |   42 ++++++------------------------------
 1 file changed, 8 insertions(+), 34 deletions(-)

--- 0010/arch/arm/mach-shmobile/smp-emev2.c
+++ work/arch/arm/mach-shmobile/smp-emev2.c	2013-02-13 21:56:10.000000000 +0900
@@ -28,27 +28,9 @@
 #include <mach/emev2.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
-#include <asm/cacheflush.h>
 
 #define EMEV2_SCU_BASE 0x1e000000
 
-static DEFINE_SPINLOCK(scu_lock);
-
-static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
-{
-	unsigned long tmp;
-
-	/* we assume this code is running on a different cpu
-	 * than the one that is changing coherency setting */
-	spin_lock(&scu_lock);
-	tmp = readl(shmobile_scu_base + 8);
-	tmp &= ~clr;
-	tmp |= set;
-	writel(tmp, shmobile_scu_base + 8);
-	spin_unlock(&scu_lock);
-
-}
-
 static void __cpuinit emev2_secondary_init(unsigned int cpu)
 {
 	gic_secondary_init(0);
@@ -56,36 +38,28 @@ static void __cpuinit emev2_secondary_in
 
 static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-	cpu = cpu_logical_map(cpu);
-
-	/* enable cache coherency */
-	modify_scu_cpu_psr(0, 3 << (cpu * 8));
-
-	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+	arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu)));
 	return 0;
 }
 
 static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
 {
-	int cpu = cpu_logical_map(0);
-
 	scu_enable(shmobile_scu_base);
 
-	/* Tell ROM loader about our vector (in headsmp.S) */
-	emev2_set_boot_vector(__pa(shmobile_secondary_vector));
+	/* Tell ROM loader about our vector (in headsmp-scu.S) */
+	emev2_set_boot_vector(__pa(shmobile_secondary_vector_scu));
 
-	/* enable cache coherency on CPU0 */
-	modify_scu_cpu_psr(0, 3 << (cpu * 8));
+	/* enable cache coherency on booting CPU */
+	scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
 }
 
 static void __init emev2_smp_init_cpus(void)
 {
 	unsigned int ncores;
 
-	if (!shmobile_scu_base) {
-		shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
-		emev2_clock_init(); /* need ioremapped SMU */
-	}
+	/* setup EMEV2 specific SCU base */
+	shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
+	emev2_clock_init(); /* need ioremapped SMU */
 
 	ncores = shmobile_scu_base ? scu_get_core_count(shmobile_scu_base) : 1;
 

[PATCH 00/06] ARM: shmobile: SMP Cortex-A9 SCU rework

[Simon Horman]

On Wed, Feb 13, 2013 at 10:46:28PM +0900, Magnus Damm wrote:
> ARM: shmobile: SMP Cortex-A9 SCU rework
> 
> [PATCH 01/06] ARM: shmobile: Kill off sh73a0 scu_base_addr() function
> [PATCH 02/06] ARM: shmobile: Kill off r8a7779 scu_base_addr() function
> [PATCH 03/06] ARM: shmobile: Rework EMEV2 scu_base variable
> [PATCH 04/06] ARM: shmobile: Move headsmp-sh73a0.S to headsmp-scu.S
> [PATCH 05/06] ARM: shmobile: Common shmobile_scu_base in headsmp-scu.S
> [PATCH 06/06] ARM: shmobile: Update EMEV2 to use scu_power_mode()
> 
> Rework the EMEV2 SMP code to make use of common scu_power_mode()
> code together with a shared shmobile_scu_base and early SCU
> setup code in headsmp-scu.S.
> 
> The patches are known to build for sh73a0, r8a7779 and EMEV2.
>
> Note that the code has only been tested on the KZM9D/EMEV2 board,
> and because of that changes to other boards have been kept at
> a minimum. Next target after this is to update the r8a7779 SMP/SCU
> code to make use of scu_base_addr(), but that requires hardware
> access for testing.

I have tested this on the kzm9g/sh73a0, marzen/r8a7779 and kzm9d/emev2.

I have applied the entire series to the soc5 branch thus queued up
for v3.10. It is also in the next branch and thus should appear
in linux-next in the not to distant future.