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Thu, 17 Jul 2025 01:46:59 -0700 (PDT) MIME-Version: 1.0 References: <20250717070006.192765-1-amadeus@jmu.edu.cn> In-Reply-To: <20250717070006.192765-1-amadeus@jmu.edu.cn> From: Alexey Charkov Date: Thu, 17 Jul 2025 12:46:47 +0400 X-Gm-Features: Ac12FXzqkgYPLwPzfI0Wfzx3xJg_aHq911YS94XX9w26rk3khvCHNvT0xMmUc6s Message-ID: Subject: Re: [PATCH v2 1/1] arm64: dts: rockchip: rk3528: Add CPU frequency scaling support To: Chukun Pan Cc: jonas@kwiboo.se, conor+dt@kernel.org, devicetree@vger.kernel.org, heiko@sntech.de, krzk+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, ziyao@disroot.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250717_014700_390106_27150243 X-CRM114-Status: GOOD ( 16.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jul 17, 2025 at 11:01=E2=80=AFAM Chukun Pan wr= ote: > > Hi Jonas, > > > One possible difference here is that the actual CPU rate is controlled > > by a PVTPLL where TF-A will configure a osc ring-length based on the > > requested rate and Linux only configure the regulator voltage. > > > > I have no idea if the configuration made by TF-A will have any affect o= n > > power usage, but I suggest we keep all opp here because both TF-A and > > Linux is involved in configuring the CPU rate. > > > > The measured rate can typically be read from a PVTPLL status reg, it > > will be different depending on the ring-length, voltage and silicon > > quality for the rates >=3D 816 MHz. > > Alexey suggested that we remove 408MHz, 600MHz and 816MHz from the > opp-table. Do you think it is acceptable to use 850mV for 1008MHz? But why 850 mV? Vendor .dtsi [1] implies that chips with leakage values of L0..L4 might be unstable at this frequency with a 850 mV supply and need 875 mV instead. As long as we don't read out OTP leakage values, we should pick a voltage for each OPP that is sufficient for all possible chip characteristics, meaning the maximum of all opp-microvolt* given in each OPP. This will result in higher -L* chips burning more power than they have to, but at least they will be stable. [1] https://github.com/rockchip-linux/kernel/blob/792a7d4273a59e80dafca48ba= 11438f43a6d8bda/arch/arm64/boot/dts/rockchip/rk3528.dtsi#L268 Best regards, Alexey