* [PATCH v8 0/2] Adds PMU and S2R support for exynos5420
@ 2014-09-30 11:02 Vikas Sajjan
2014-09-30 11:02 ` [PATCH v8 1/2] ARM: exynos5: Add PMU support for 5420 Vikas Sajjan
` (2 more replies)
0 siblings, 3 replies; 13+ messages in thread
From: Vikas Sajjan @ 2014-09-30 11:02 UTC (permalink / raw)
To: linux-arm-kernel
Rebased on
1] Kukjin Kim's tree, for-next branch
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next
2] Pankaj Dubey's v8 PMU patchset
https://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg37236.html
changes since v7:
- rebased on pankaj's latest patchset.
changes since v6:
- rebased on 3.17.rc1.
changes since v5:
- Refactored pm.c to use DT based lookup as suggested by Tomasz Figa.
changes since v4:
- Adressed comments from Tomasz figa and rebased on Pankaj Dubey's v5 PMU patchset
changes since v3:
Addressed the following comments from Pankaj Dubey, Bartlomiej Zolnierkiewicz,
Tomasz Figa and Alim Akhtar:
- Moved EXYNOS5420_USE_STANDBY_WFI_ALL define to regs-pmu.h.
- Merged exynos5420_set_core_flag function into powerdown_conf.
- Removed XXTI_DURATION3 register setting.
- Updated the commit message and ordered the clock registers in clock
patch.
- Removed the code for SYS_DISP1_BLK_CFG handling.
- Modified SoC checks to A9 specific checks in PM code.
- Updated some comments in the code and added macros for register offsets.
- Fixed code which was changing pad retention code for older SoCs.
changes since v2:
- Addressed comments from Tomasz figa
- rebased on Pankaj's V3 patchset https://lkml.org/lkml/2014/5/2/612
- dropped patch "ARM: dts: Add node for GPIO keys on SMDK5420",
will be sent separately.
changes since v1:
- Addressed comments from Tomasz figa.
- restructured/consolidated as per Tomasz figa's PM consolidations for exynos
Tested on Kukjin Kim's tree, for-next branch +
1] http://www.spinics.net/lists/linux-samsung-soc/msg33750.html
2] https://lkml.org/lkml/2014/9/30/156
on Exynos5420 based chromebook (peach-pit board)
Below procedures were followed to test S2R:
Procedure A:
1. make multi_v7_defconfig
2 enable MCPM for 5420
3. enable S3C RTC
4. pass "no_console_suspend" in bootargs
5. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state
Procedure B:
1. make exynos_defconfig
2 disable BL_SWITCHER
3. pass "no_console_suspend" in bootargs
4. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state
Abhilash Kesavan (1):
ARM: exynos5: Add PMU support for 5420
Vikas Sajjan (1):
ARM: exynos5: Add Suspend-to-RAM support for 5420
arch/arm/mach-exynos/pmu.c | 287 +++++++++++++++++++++++++++++++++++++++
arch/arm/mach-exynos/regs-pmu.h | 227 +++++++++++++++++++++++++++++++
arch/arm/mach-exynos/suspend.c | 156 ++++++++++++++++++++-
3 files changed, 668 insertions(+), 2 deletions(-)
--
1.7.9.5
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v8 1/2] ARM: exynos5: Add PMU support for 5420 2014-09-30 11:02 [PATCH v8 0/2] Adds PMU and S2R support for exynos5420 Vikas Sajjan @ 2014-09-30 11:02 ` Vikas Sajjan 2014-09-30 11:02 ` [PATCH v8 2/2] ARM: exynos5: Add Suspend-to-RAM " Vikas Sajjan 2014-09-30 13:30 ` [PATCH v8 0/2] Adds PMU and S2R support for exynos5420 Javier Martinez Canillas 2 siblings, 0 replies; 13+ messages in thread From: Vikas Sajjan @ 2014-09-30 11:02 UTC (permalink / raw) To: linux-arm-kernel From: Abhilash Kesavan <a.kesavan@samsung.com> Add intial PMU settings for exynos5420. This is required for future S2R and Switching support. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com> --- arch/arm/mach-exynos/pmu.c | 287 +++++++++++++++++++++++++++++++++++++++ arch/arm/mach-exynos/regs-pmu.h | 227 +++++++++++++++++++++++++++++++ 2 files changed, 514 insertions(+) diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index b68cd29a..4110281 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -12,6 +12,8 @@ #include <linux/io.h> #include <linux/of.h> #include <linux/platform_device.h> +#include <linux/delay.h> + #include "exynos-pmu.h" #include "regs-pmu.h" @@ -348,6 +350,151 @@ static const struct exynos_pmu_conf exynos5250_pmu_config[] = { { PMU_TABLE_END,}, }; +static struct exynos_pmu_conf exynos5420_pmu_config[] = { + /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */ + { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_ARM_CORE2_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_ARM_CORE3_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_KFC_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_KFC_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_KFC_CORE2_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_KFC_CORE3_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5420_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_KFC_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_KFC_L2_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, + { EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, + { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, + { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, + { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, + { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, + { EXYNOS5_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, + { EXYNOS5_TOP_PWR_SYS_PWR_REG, { 0x3, 0x3, 0x0} }, + { EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, + { EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, + { EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, + { EXYNOS5_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, + { EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5420_INTRAM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} }, + { EXYNOS5420_INTROM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} }, + { EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_GSCL_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, + { EXYNOS5_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, + { EXYNOS5_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, + { EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, + { EXYNOS5420_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, + { EXYNOS5420_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} }, + { EXYNOS5420_G2D_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, + { EXYNOS5420_MSC_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, + { EXYNOS5420_FSYS_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, + { EXYNOS5420_FSYS2_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, + { EXYNOS5420_PSGEN_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, + { EXYNOS5420_PERIC_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, + { EXYNOS5420_WCORE_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, + { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { PMU_TABLE_END,}, +}; + static unsigned int const exynos5_list_both_cnt_feed[] = { EXYNOS5_ARM_CORE0_OPTION, EXYNOS5_ARM_CORE1_OPTION, @@ -368,6 +515,75 @@ static unsigned int const exynos5_list_diable_wfi_wfe[] = { EXYNOS5_ISP_ARM_OPTION, }; +static unsigned int const exynos5420_list_disable_pmu_reg[] = { + EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, + EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, + EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, + EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG, + EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG, + EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG, + EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG, + EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG, + EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG, + EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG, + EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG, + EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, + EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, + EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, + EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG, + EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG, + EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG, + EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG, + EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG, + EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG, + EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG, + EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG, + EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG, + EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG, + EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG, + EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG, + EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG, + EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, + EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, + EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, + EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG, + EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG, + EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG, + EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG, + EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG, +}; + +static void exynos5_power_off(void) +{ + unsigned int tmp; + + pr_info("Power down.\n"); + tmp = pmu_raw_readl(EXYNOS_PS_HOLD_CONTROL); + tmp ^= (1 << 8); + pmu_raw_writel(tmp, EXYNOS_PS_HOLD_CONTROL); + + /* Wait a little so we don't give a false warning below */ + mdelay(100); + + pr_err("Power down failed, please power off system manually.\n"); + while (1) + ; +} + +void exynos5420_powerdown_conf(enum sys_powerdown mode) +{ + u32 this_cluster; + + this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1); + + /* + * set the cluster id to IROM register to ensure that we wake + * up with the current cluster. + */ + pmu_raw_writel(this_cluster, EXYNOS_IROM_DATA2); +} + + static void exynos5_powerdown_conf(enum sys_powerdown mode) { unsigned int i; @@ -439,6 +655,68 @@ static void exynos5250_pmu_init(void) pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST); } +static void exynos5420_pmu_init(void) +{ + unsigned int value; + int i; + + /* + * Set the CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers + * for local power blocks to Low initially as per Table 8-4: + * "System-Level Power-Down Configuration Registers". + */ + for (i = 0; i < ARRAY_SIZE(exynos5420_list_disable_pmu_reg); i++) + pmu_raw_writel(0, exynos5420_list_disable_pmu_reg[i]); + + /* Enable USE_STANDBY_WFI for all CORE */ + pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION); + + value = pmu_raw_readl(EXYNOS_L2_OPTION(0)); + value &= ~EXYNOS5_USE_RETENTION; + pmu_raw_writel(value, EXYNOS_L2_OPTION(0)); + + value = pmu_raw_readl(EXYNOS_L2_OPTION(1)); + value &= ~EXYNOS5_USE_RETENTION; + pmu_raw_writel(value, EXYNOS_L2_OPTION(1)); + + /* + * If L2_COMMON is turned off, clocks related to ATB async + * bridge are gated. Thus, when ISP power is gated, LPI + * may get stuck. + */ + value = pmu_raw_readl(EXYNOS5420_LPI_MASK); + value |= EXYNOS5420_ATB_ISP_ARM; + pmu_raw_writel(value, EXYNOS5420_LPI_MASK); + + value = pmu_raw_readl(EXYNOS5420_LPI_MASK1); + value |= EXYNOS5420_ATB_KFC; + pmu_raw_writel(value, EXYNOS5420_LPI_MASK1); + + /* Prevent issue of new bus request from L2 memory */ + value = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION); + value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN; + pmu_raw_writel(value, EXYNOS5420_ARM_COMMON_OPTION); + + value = pmu_raw_readl(EXYNOS5420_KFC_COMMON_OPTION); + value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN; + pmu_raw_writel(value, EXYNOS5420_KFC_COMMON_OPTION); + + /* This setting is to reduce suspend/resume time */ + pmu_raw_writel(DUR_WAIT_RESET, EXYNOS5420_LOGIC_RESET_DURATION3); + + /* Serialized CPU wakeup of Eagle */ + pmu_raw_writel(SPREAD_ENABLE, EXYNOS5420_ARM_INTR_SPREAD_ENABLE); + + pmu_raw_writel(SPREAD_USE_STANDWFI, + EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI); + + pmu_raw_writel(0x1, EXYNOS5420_UP_SCHEDULER); + + pm_power_off = exynos5_power_off; + pr_info("EXYNOS5420 PMU initialized\n"); +} + + static const struct exynos_pmu_data exynos4210_pmu_data = { .pmu_config = exynos4210_pmu_config, }; @@ -458,6 +736,12 @@ static const struct exynos_pmu_data exynos5250_pmu_data = { .powerdown_conf = exynos5_powerdown_conf, }; +static struct exynos_pmu_data exynos5420_pmu_data = { + .pmu_config = exynos5420_pmu_config, + .pmu_init = exynos5420_pmu_init, + .powerdown_conf = exynos5420_powerdown_conf, +}; + /* * PMU platform driver and devicetree bindings. */ @@ -474,6 +758,9 @@ static const struct of_device_id exynos_pmu_of_device_ids[] = { }, { .compatible = "samsung,exynos5250-pmu", .data = &exynos5250_pmu_data, + }, { + .compatible = "samsung,exynos5420-pmu", + .data = &exynos5420_pmu_data, }, { /*sentinel*/ }, }; diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index 322f132..46b973b 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -38,6 +38,7 @@ #define S5P_INFORM7 0x081C #define S5P_PMU_SPARE3 0x090C +#define EXYNOS_IROM_DATA2 0x0988 #define S5P_ARM_CORE0_LOWPWR 0x1000 #define S5P_DIS_IRQ_CORE0 0x1004 #define S5P_DIS_IRQ_CENTRAL0 0x1008 @@ -120,6 +121,31 @@ #define EXYNOS_COMMON_OPTION(_nr) \ (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8) +#define EXYNOS_CORE_LOCAL_PWR_EN 0x3 + +#define EXYNOS_ARM_COMMON_STATUS 0x2504 +#define EXYNOS_COMMON_OPTION(_nr) \ + (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8) + +#define EXYNOS_ARM_L2_CONFIGURATION 0x2600 +#define EXYNOS_L2_CONFIGURATION(_nr) \ + (EXYNOS_ARM_L2_CONFIGURATION + ((_nr) * 0x80)) +#define EXYNOS_L2_STATUS(_nr) \ + (EXYNOS_L2_CONFIGURATION(_nr) + 0x4) +#define EXYNOS_L2_OPTION(_nr) \ + (EXYNOS_L2_CONFIGURATION(_nr) + 0x8) +#define EXYNOS_L2_COMMON_PWR_EN 0x3 + +#define EXYNOS_ARM_CORE_X_STATUS_OFFSET 0x4 + +#define EXYNOS5_APLL_SYSCLK_CONFIGURATION 0x2A00 +#define EXYNOS5_APLL_SYSCLK_STATUS 0x2A04 + +#define EXYNOS5_ARM_L2_OPTION 0x2608 +#define EXYNOS5_USE_RETENTION BIT(4) + +#define EXYNOS5_L2RSTDISABLE_VALUE BIT(3) + #define S5P_PAD_RET_MAUDIO_OPTION 0x3028 #define S5P_PAD_RET_GPIO_OPTION 0x3108 #define S5P_PAD_RET_UART_OPTION 0x3128 @@ -193,6 +219,7 @@ #define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408 #define EXYNOS5_MASK_WDTRESET_REQUEST 0x040C +#define EXYNOS5_USE_RETENTION BIT(4) #define EXYNOS5_SYS_WDTRESET (1 << 20) #define EXYNOS5_ARM_CORE0_SYS_PWR_REG 0x1000 @@ -332,4 +359,204 @@ static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr) + MPIDR_AFFINITY_LEVEL(mpidr, 0)); } +/* Only for EXYNOS5420 */ +#define EXYNOS5420_ISP_ARM_OPTION 0x2488 +#define EXYNOS5420_L2RSTDISABLE_VALUE BIT(3) + +#define EXYNOS5420_LPI_MASK 0x0004 +#define EXYNOS5420_LPI_MASK1 0x0008 +#define EXYNOS5420_UFS BIT(8) +#define EXYNOS5420_ATB_KFC BIT(13) +#define EXYNOS5420_ATB_ISP_ARM BIT(19) +#define EXYNOS5420_EMULATION BIT(31) +#define ATB_ISP_ARM BIT(12) +#define ATB_KFC BIT(13) +#define ATB_NOC BIT(14) + +#define EXYNOS5420_ARM_INTR_SPREAD_ENABLE 0x0100 +#define EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI 0x0104 +#define EXYNOS5420_UP_SCHEDULER 0x0120 +#define SPREAD_ENABLE 0xF +#define SPREAD_USE_STANDWFI 0xF + +#define EXYNOS5420_BB_CON1 0x0784 +#define EXYNOS5420_BB_SEL_EN BIT(31) +#define EXYNOS5420_BB_PMOS_EN BIT(7) +#define EXYNOS5420_BB_1300X 0XF + +#define EXYNOS5420_ARM_CORE2_SYS_PWR_REG 0x1020 +#define EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG 0x1024 +#define EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG 0x1028 +#define EXYNOS5420_ARM_CORE3_SYS_PWR_REG 0x1030 +#define EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG 0x1034 +#define EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG 0x1038 +#define EXYNOS5420_KFC_CORE0_SYS_PWR_REG 0x1040 +#define EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG 0x1044 +#define EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG 0x1048 +#define EXYNOS5420_KFC_CORE1_SYS_PWR_REG 0x1050 +#define EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG 0x1054 +#define EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG 0x1058 +#define EXYNOS5420_KFC_CORE2_SYS_PWR_REG 0x1060 +#define EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG 0x1064 +#define EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG 0x1068 +#define EXYNOS5420_KFC_CORE3_SYS_PWR_REG 0x1070 +#define EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG 0x1074 +#define EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG 0x1078 +#define EXYNOS5420_ISP_ARM_SYS_PWR_REG 0x1090 +#define EXYNOS5420_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1094 +#define EXYNOS5420_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1098 +#define EXYNOS5420_ARM_COMMON_SYS_PWR_REG 0x10A0 +#define EXYNOS5420_KFC_COMMON_SYS_PWR_REG 0x10B0 +#define EXYNOS5420_KFC_L2_SYS_PWR_REG 0x10D0 +#define EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG 0x1158 +#define EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG 0x115C +#define EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG 0x1160 +#define EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG 0x1174 +#define EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG 0x1178 +#define EXYNOS5420_INTRAM_MEM_SYS_PWR_REG 0x11B8 +#define EXYNOS5420_INTROM_MEM_SYS_PWR_REG 0x11BC +#define EXYNOS5420_ONENANDXL_MEM_SYS_PWR 0x11C0 +#define EXYNOS5420_USBDEV_MEM_SYS_PWR 0x11CC +#define EXYNOS5420_USBDEV1_MEM_SYS_PWR 0x11D0 +#define EXYNOS5420_SDMMC_MEM_SYS_PWR 0x11D4 +#define EXYNOS5420_CSSYS_MEM_SYS_PWR 0x11D8 +#define EXYNOS5420_SECSS_MEM_SYS_PWR 0x11DC +#define EXYNOS5420_ROTATOR_MEM_SYS_PWR 0x11E0 +#define EXYNOS5420_INTRAM_MEM_SYS_PWR 0x11E4 +#define EXYNOS5420_INTROM_MEM_SYS_PWR 0x11E8 +#define EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG 0x1208 +#define EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1210 +#define EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG 0x1214 +#define EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG 0x1218 +#define EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG 0x121C +#define EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG 0x1220 +#define EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG 0x1224 +#define EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1228 +#define EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG 0x122C +#define EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG 0x1230 +#define EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG 0x1234 +#define EXYNOS5420_DISP1_SYS_PWR_REG 0x1410 +#define EXYNOS5420_MAU_SYS_PWR_REG 0x1414 +#define EXYNOS5420_G2D_SYS_PWR_REG 0x1418 +#define EXYNOS5420_MSC_SYS_PWR_REG 0x141C +#define EXYNOS5420_FSYS_SYS_PWR_REG 0x1420 +#define EXYNOS5420_FSYS2_SYS_PWR_REG 0x1424 +#define EXYNOS5420_PSGEN_SYS_PWR_REG 0x1428 +#define EXYNOS5420_PERIC_SYS_PWR_REG 0x142C +#define EXYNOS5420_WCORE_SYS_PWR_REG 0x1430 +#define EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1490 +#define EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1494 +#define EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG 0x1498 +#define EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG 0x149C +#define EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG 0x14A0 +#define EXYNOS5420_CMU_CLKSTOP_FSYS2_SYS_PWR_REG 0x14A4 +#define EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG 0x14A8 +#define EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG 0x14AC +#define EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG 0x14B0 +#define EXYNOS5420_CMU_SYSCLK_TOPPWR_SYS_PWR_REG 0x14BC +#define EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D0 +#define EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D4 +#define EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG 0x14D8 +#define EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG 0x14DC +#define EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG 0x14E0 +#define EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG 0x14E4 +#define EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG 0x14E8 +#define EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG 0x14EC +#define EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG 0x14F0 +#define EXYNOS5420_CMU_SYSCLK_SYSMEM_TOPPWR_SYS_PWR_REG 0x14F4 +#define EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG 0x1570 +#define EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG 0x1574 +#define EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG 0x1578 +#define EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG 0x157C +#define EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG 0x1590 +#define EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG 0x1594 +#define EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG 0x1598 +#define EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG 0x159C +#define EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG 0x15A0 +#define EXYNOS5420_SFR_AXI_CGDIS1 0x15E4 +#define EXYNOS_ARM_CORE2_CONFIGURATION 0x2100 +#define EXYNOS5420_ARM_CORE2_OPTION 0x2108 +#define EXYNOS_ARM_CORE3_CONFIGURATION 0x2180 +#define EXYNOS5420_ARM_CORE3_OPTION 0x2188 +#define EXYNOS5420_ARM_COMMON_STATUS 0x2504 +#define EXYNOS5420_ARM_COMMON_OPTION 0x2508 +#define EXYNOS5420_KFC_COMMON_STATUS 0x2584 +#define EXYNOS5420_KFC_COMMON_OPTION 0x2588 +#define EXYNOS5420_LOGIC_RESET_DURATION3 0x2D1C + +#define EXYNOS5420_PAD_RET_GPIO_OPTION 0x30C8 +#define EXYNOS5420_PAD_RET_UART_OPTION 0x30E8 +#define EXYNOS5420_PAD_RET_MMCA_OPTION 0x3108 +#define EXYNOS5420_PAD_RET_MMCB_OPTION 0x3128 +#define EXYNOS5420_PAD_RET_MMCC_OPTION 0x3148 +#define EXYNOS5420_PAD_RET_HSI_OPTION 0x3168 +#define EXYNOS5420_PAD_RET_SPI_OPTION 0x31C8 +#define EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION 0x31E8 +#define EXYNOS_PAD_RET_DRAM_OPTION 0x3008 +#define EXYNOS_PAD_RET_MAUDIO_OPTION 0x3028 +#define EXYNOS_PAD_RET_JTAG_OPTION 0x3048 +#define EXYNOS_PAD_RET_GPIO_OPTION 0x3108 +#define EXYNOS_PAD_RET_UART_OPTION 0x3128 +#define EXYNOS_PAD_RET_MMCA_OPTION 0x3148 +#define EXYNOS_PAD_RET_MMCB_OPTION 0x3168 +#define EXYNOS_PAD_RET_EBIA_OPTION 0x3188 +#define EXYNOS_PAD_RET_EBIB_OPTION 0x31A8 + +#define EXYNOS_PS_HOLD_CONTROL 0x330C + +/* For SYS_PWR_REG */ +#define EXYNOS_SYS_PWR_CFG BIT(0) + +#define EXYNOS5420_MFC_CONFIGURATION 0x4060 +#define EXYNOS5420_MFC_STATUS 0x4064 +#define EXYNOS5420_MFC_OPTION 0x4068 +#define EXYNOS5420_G3D_CONFIGURATION 0x4080 +#define EXYNOS5420_G3D_STATUS 0x4084 +#define EXYNOS5420_G3D_OPTION 0x4088 +#define EXYNOS5420_DISP0_CONFIGURATION 0x40A0 +#define EXYNOS5420_DISP0_STATUS 0x40A4 +#define EXYNOS5420_DISP0_OPTION 0x40A8 +#define EXYNOS5420_DISP1_CONFIGURATION 0x40C0 +#define EXYNOS5420_DISP1_STATUS 0x40C4 +#define EXYNOS5420_DISP1_OPTION 0x40C8 +#define EXYNOS5420_MAU_CONFIGURATION 0x40E0 +#define EXYNOS5420_MAU_STATUS 0x40E4 +#define EXYNOS5420_MAU_OPTION 0x40E8 +#define EXYNOS5420_FSYS2_OPTION 0x4168 +#define EXYNOS5420_PSGEN_OPTION 0x4188 + +/* For EXYNOS_CENTRAL_SEQ_OPTION */ +#define EXYNOS5_USE_STANDBYWFI_ARM_CORE0 BIT(16) +#define EXYNOS5_USE_STANDBYWFI_ARM_CORE1 BUT(17) +#define EXYNOS5_USE_STANDBYWFE_ARM_CORE0 BIT(24) +#define EXYNOS5_USE_STANDBYWFE_ARM_CORE1 BIT(25) + +#define EXYNOS5420_ARM_USE_STANDBY_WFI0 BIT(4) +#define EXYNOS5420_ARM_USE_STANDBY_WFI1 BIT(5) +#define EXYNOS5420_ARM_USE_STANDBY_WFI2 BIT(6) +#define EXYNOS5420_ARM_USE_STANDBY_WFI3 BIT(7) +#define EXYNOS5420_KFC_USE_STANDBY_WFI0 BIT(8) +#define EXYNOS5420_KFC_USE_STANDBY_WFI1 BIT(9) +#define EXYNOS5420_KFC_USE_STANDBY_WFI2 BIT(10) +#define EXYNOS5420_KFC_USE_STANDBY_WFI3 BIT(11) +#define EXYNOS5420_ARM_USE_STANDBY_WFE0 BIT(16) +#define EXYNOS5420_ARM_USE_STANDBY_WFE1 BIT(17) +#define EXYNOS5420_ARM_USE_STANDBY_WFE2 BIT(18) +#define EXYNOS5420_ARM_USE_STANDBY_WFE3 BIT(19) +#define EXYNOS5420_KFC_USE_STANDBY_WFE0 BIT(20) +#define EXYNOS5420_KFC_USE_STANDBY_WFE1 BIT(21) +#define EXYNOS5420_KFC_USE_STANDBY_WFE2 BIT(22) +#define EXYNOS5420_KFC_USE_STANDBY_WFE3 BIT(23) + +#define DUR_WAIT_RESET 0xF + +#define EXYNOS5420_USE_STANDBY_WFI_ALL (EXYNOS5420_ARM_USE_STANDBY_WFI0 \ + | EXYNOS5420_ARM_USE_STANDBY_WFI1 \ + | EXYNOS5420_ARM_USE_STANDBY_WFI2 \ + | EXYNOS5420_ARM_USE_STANDBY_WFI3 \ + | EXYNOS5420_KFC_USE_STANDBY_WFI0 \ + | EXYNOS5420_KFC_USE_STANDBY_WFI1 \ + | EXYNOS5420_KFC_USE_STANDBY_WFI2 \ + | EXYNOS5420_KFC_USE_STANDBY_WFI3) + #endif /* __ASM_ARCH_REGS_PMU_H */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v8 2/2] ARM: exynos5: Add Suspend-to-RAM support for 5420 2014-09-30 11:02 [PATCH v8 0/2] Adds PMU and S2R support for exynos5420 Vikas Sajjan 2014-09-30 11:02 ` [PATCH v8 1/2] ARM: exynos5: Add PMU support for 5420 Vikas Sajjan @ 2014-09-30 11:02 ` Vikas Sajjan 2014-10-06 3:33 ` Abhilash Kesavan 2014-09-30 13:30 ` [PATCH v8 0/2] Adds PMU and S2R support for exynos5420 Javier Martinez Canillas 2 siblings, 1 reply; 13+ messages in thread From: Vikas Sajjan @ 2014-09-30 11:02 UTC (permalink / raw) To: linux-arm-kernel Adds Suspend-to-RAM support for EXYNOS5420 Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> --- arch/arm/mach-exynos/suspend.c | 156 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 154 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c index 079d999..773140c 100644 --- a/arch/arm/mach-exynos/suspend.c +++ b/arch/arm/mach-exynos/suspend.c @@ -39,6 +39,8 @@ #define REG_TABLE_END (-1U) +#define EXYNOS5420_CPU_STATE 0x28 + /** * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping * @hwirq: Hardware IRQ signal of the GIC @@ -77,6 +79,9 @@ struct exynos_pm_data { struct exynos_pm_data *pm_data; +static int exynos5420_cpu_state; +static unsigned int exynos_pmu_spare3; + /* * GIC wake-up support */ @@ -106,6 +111,23 @@ unsigned int exynos_release_ret_regs[] = { REG_TABLE_END, }; +unsigned int exynos5420_release_ret_regs[] = { + EXYNOS_PAD_RET_DRAM_OPTION, + EXYNOS_PAD_RET_MAUDIO_OPTION, + EXYNOS_PAD_RET_JTAG_OPTION, + EXYNOS5420_PAD_RET_GPIO_OPTION, + EXYNOS5420_PAD_RET_UART_OPTION, + EXYNOS5420_PAD_RET_MMCA_OPTION, + EXYNOS5420_PAD_RET_MMCB_OPTION, + EXYNOS5420_PAD_RET_MMCC_OPTION, + EXYNOS5420_PAD_RET_HSI_OPTION, + EXYNOS_PAD_RET_EBIA_OPTION, + EXYNOS_PAD_RET_EBIB_OPTION, + EXYNOS5420_PAD_RET_SPI_OPTION, + EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, + REG_TABLE_END, +}; + static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) { const struct exynos_wkup_irq *wkup_irq; @@ -136,11 +158,22 @@ static int exynos_cpu_do_idle(void) pr_info("Failed to suspend the system\n"); return 1; /* Aborting suspend */ } - -static int exynos_cpu_suspend(unsigned long arg) +static void exynos_flush_cache_all(void) { flush_cache_all(); outer_flush_all(); +} + +static int exynos_cpu_suspend(unsigned long arg) +{ + exynos_flush_cache_all(); + return exynos_cpu_do_idle(); +} + +static int exynos5420_cpu_suspend(unsigned long arg) +{ + exynos_flush_cache_all(); + __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE); return exynos_cpu_do_idle(); } @@ -175,6 +208,50 @@ static void exynos_pm_prepare(void) exynos_pm_enter_sleep_mode(); } +static void exynos5420_pm_prepare(void) +{ + unsigned int tmp; + + /* Set wake-up mask registers */ + exynos_pm_set_wakeup_mask(); + + s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); + + exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3); + /* + * The cpu state needs to be saved and restored so that the + * secondary CPUs will enter low power start. Though the U-Boot + * is setting the cpu state with low power flag, the kernel + * needs to restore it back in case, the primary cpu fails to + * suspend for any reason. + */ + exynos5420_cpu_state = __raw_readl(sysram_base_addr + + EXYNOS5420_CPU_STATE); + + exynos_pm_enter_sleep_mode(); + + tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION); + tmp &= ~EXYNOS5_USE_RETENTION; + pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION); + + tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); + tmp |= EXYNOS5420_UFS; + pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1); + + tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION); + tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE; + pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION); + + tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION); + tmp |= EXYNOS5420_EMULATION; + pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION); + + tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION); + tmp |= EXYNOS5420_EMULATION; + pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION); +} + + static int exynos_pm_suspend(void) { exynos_pm_central_suspend(); @@ -185,6 +262,24 @@ static int exynos_pm_suspend(void) return 0; } +static int exynos5420_pm_suspend(void) +{ + u32 this_cluster; + + exynos_pm_central_suspend(); + + /* Setting SEQ_OPTION register */ + + this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1); + if (!this_cluster) + pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0, + S5P_CENTRAL_SEQ_OPTION); + else + pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0, + S5P_CENTRAL_SEQ_OPTION); + return 0; +} + static void exynos_pm_release_retention(void) { unsigned int i; @@ -223,6 +318,50 @@ early_wakeup: pmu_raw_writel(0x0, S5P_INFORM1); } +static void exynos5420_pm_resume(void) +{ + unsigned long tmp; + + /* Restore the CPU0 low power state register */ + tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG); + pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN, + EXYNOS5_ARM_CORE0_SYS_PWR_REG); + + /* Restore the sysram cpu state register */ + __raw_writel(exynos5420_cpu_state, + sysram_base_addr + EXYNOS5420_CPU_STATE); + + pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, + S5P_CENTRAL_SEQ_OPTION); + + if (exynos_pm_central_resume()) + goto early_wakeup; + + /* For release retention */ + exynos_pm_release_retention(); + + pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3); + + s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); + +early_wakeup: + + tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); + tmp &= ~EXYNOS5420_UFS; + pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1); + + tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION); + tmp &= ~EXYNOS5420_EMULATION; + pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION); + + tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION); + tmp &= ~EXYNOS5420_EMULATION; + pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION); + + /* Clear SLEEP mode set in INFORM1 */ + pmu_raw_writel(0x0, S5P_INFORM1); +} + /* * Suspend Ops */ @@ -310,6 +449,16 @@ static const struct exynos_pm_data exynos5250_pm_data = { .cpu_suspend = exynos_cpu_suspend, }; +static struct exynos_pm_data exynos5420_pm_data = { + .wkup_irq = exynos5250_wkup_irq, + .wake_disable_mask = (0x7F << 7) | (0x1F << 1), + .release_ret_regs = exynos5420_release_ret_regs, + .pm_resume = exynos5420_pm_resume, + .pm_suspend = exynos5420_pm_suspend, + .pm_prepare = exynos5420_pm_prepare, + .cpu_suspend = exynos5420_cpu_suspend, +}; + static struct of_device_id exynos_pmu_of_device_ids[] = { { .compatible = "samsung,exynos4210-pmu", @@ -323,6 +472,9 @@ static struct of_device_id exynos_pmu_of_device_ids[] = { }, { .compatible = "samsung,exynos5250-pmu", .data = &exynos5250_pm_data, + }, { + .compatible = "samsung,exynos5420-pmu", + .data = &exynos5420_pm_data, }, { /*sentinel*/ }, }; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v8 2/2] ARM: exynos5: Add Suspend-to-RAM support for 5420 2014-09-30 11:02 ` [PATCH v8 2/2] ARM: exynos5: Add Suspend-to-RAM " Vikas Sajjan @ 2014-10-06 3:33 ` Abhilash Kesavan 0 siblings, 0 replies; 13+ messages in thread From: Abhilash Kesavan @ 2014-10-06 3:33 UTC (permalink / raw) To: linux-arm-kernel Hi Vikas, [...] > +static void exynos5420_pm_resume(void) > +{ > + unsigned long tmp; > + > + /* Restore the CPU0 low power state register */ > + tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG); > + pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN, > + EXYNOS5_ARM_CORE0_SYS_PWR_REG); I think these lines were accidentally added to this patch, please remove them. I have a couple of changes to make in my s2r patch which I will post once you send a new version. Regards, Abhilash > + > + /* Restore the sysram cpu state register */ > + __raw_writel(exynos5420_cpu_state, > + sysram_base_addr + EXYNOS5420_CPU_STATE); > + > + pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, > + S5P_CENTRAL_SEQ_OPTION); > + > + if (exynos_pm_central_resume()) > + goto early_wakeup; > + > + /* For release retention */ > + exynos_pm_release_retention(); > + > + pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3); > + > + s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); > + > +early_wakeup: > + > + tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); > + tmp &= ~EXYNOS5420_UFS; > + pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1); > + > + tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION); > + tmp &= ~EXYNOS5420_EMULATION; > + pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION); > + > + tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION); > + tmp &= ~EXYNOS5420_EMULATION; > + pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION); > + > + /* Clear SLEEP mode set in INFORM1 */ > + pmu_raw_writel(0x0, S5P_INFORM1); > +} > + > /* > * Suspend Ops > */ > @@ -310,6 +449,16 @@ static const struct exynos_pm_data exynos5250_pm_data = { > .cpu_suspend = exynos_cpu_suspend, > }; > > +static struct exynos_pm_data exynos5420_pm_data = { > + .wkup_irq = exynos5250_wkup_irq, > + .wake_disable_mask = (0x7F << 7) | (0x1F << 1), > + .release_ret_regs = exynos5420_release_ret_regs, > + .pm_resume = exynos5420_pm_resume, > + .pm_suspend = exynos5420_pm_suspend, > + .pm_prepare = exynos5420_pm_prepare, > + .cpu_suspend = exynos5420_cpu_suspend, > +}; > + > static struct of_device_id exynos_pmu_of_device_ids[] = { > { > .compatible = "samsung,exynos4210-pmu", > @@ -323,6 +472,9 @@ static struct of_device_id exynos_pmu_of_device_ids[] = { > }, { > .compatible = "samsung,exynos5250-pmu", > .data = &exynos5250_pm_data, > + }, { > + .compatible = "samsung,exynos5420-pmu", > + .data = &exynos5420_pm_data, > }, > { /*sentinel*/ }, > }; > -- > 1.7.9.5 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel at lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v8 0/2] Adds PMU and S2R support for exynos5420 2014-09-30 11:02 [PATCH v8 0/2] Adds PMU and S2R support for exynos5420 Vikas Sajjan 2014-09-30 11:02 ` [PATCH v8 1/2] ARM: exynos5: Add PMU support for 5420 Vikas Sajjan 2014-09-30 11:02 ` [PATCH v8 2/2] ARM: exynos5: Add Suspend-to-RAM " Vikas Sajjan @ 2014-09-30 13:30 ` Javier Martinez Canillas 2014-09-30 14:24 ` Abhilash Kesavan 2014-10-01 10:23 ` Vikas Sajjan 2 siblings, 2 replies; 13+ messages in thread From: Javier Martinez Canillas @ 2014-09-30 13:30 UTC (permalink / raw) To: linux-arm-kernel Hello Vikas, Thanks a lot for the re-spin. On Tue, Sep 30, 2014 at 1:02 PM, Vikas Sajjan <vikas.sajjan@samsung.com> wrote: > > Tested on Kukjin Kim's tree, for-next branch + > 1] http://www.spinics.net/lists/linux-samsung-soc/msg33750.html > 2] https://lkml.org/lkml/2014/9/30/156 I wanted to test your series but I noticed that Abhilash's patch: "[PATCH v7] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420" does not apply cleanly on Kukjin's for-next branch. I see that all the dependencies mentioned (modulo $subject or course) have already been merged though. Did you rebase Abhilash's to test your series?. I can forward port as well but just want to be sure that I'm not missing any other dependency. These are the patches I've on top of Kukjin's for-next branch fyi: 663dfa7 ARM: exynos5: Add Suspend-to-RAM support for 5420 b4b3b76 ARM: exynos5: Add PMU support for 5420 6c0e381 ARM: EXYNOS: Move PMU specific definitions from common.h cdf79fe ARM: EXYNOS: Add platform driver support for Exynos PMU d2d8bc6 mfd: syscon: Decouple syscon interface from platform devices Best regards, Javier ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v8 0/2] Adds PMU and S2R support for exynos5420 2014-09-30 13:30 ` [PATCH v8 0/2] Adds PMU and S2R support for exynos5420 Javier Martinez Canillas @ 2014-09-30 14:24 ` Abhilash Kesavan 2014-09-30 14:42 ` Javier Martinez Canillas 2014-10-01 10:23 ` Vikas Sajjan 1 sibling, 1 reply; 13+ messages in thread From: Abhilash Kesavan @ 2014-09-30 14:24 UTC (permalink / raw) To: linux-arm-kernel Hi Javier, On Tue, Sep 30, 2014 at 7:00 PM, Javier Martinez Canillas <javier@dowhile0.org> wrote: > Hello Vikas, > > Thanks a lot for the re-spin. > > On Tue, Sep 30, 2014 at 1:02 PM, Vikas Sajjan <vikas.sajjan@samsung.com> wrote: >> >> Tested on Kukjin Kim's tree, for-next branch + >> 1] http://www.spinics.net/lists/linux-samsung-soc/msg33750.html >> 2] https://lkml.org/lkml/2014/9/30/156 > > I wanted to test your series but I noticed that Abhilash's patch: > > "[PATCH v7] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420" > > does not apply cleanly on Kukjin's for-next branch. I see that all the > dependencies mentioned (modulo $subject or course) have already been > merged though. If you are looking to test this series right now then I can post an untested rebased version. Otherwise, I will test it tomorrow and post. Regards, Abhilash > > Did you rebase Abhilash's to test your series?. I can forward port as > well but just want to be sure that I'm not missing any other > dependency. > > These are the patches I've on top of Kukjin's for-next branch fyi: > > 663dfa7 ARM: exynos5: Add Suspend-to-RAM support for 5420 > b4b3b76 ARM: exynos5: Add PMU support for 5420 > 6c0e381 ARM: EXYNOS: Move PMU specific definitions from common.h > cdf79fe ARM: EXYNOS: Add platform driver support for Exynos PMU > d2d8bc6 mfd: syscon: Decouple syscon interface from platform devices > > Best regards, > Javier > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel at lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v8 0/2] Adds PMU and S2R support for exynos5420 2014-09-30 14:24 ` Abhilash Kesavan @ 2014-09-30 14:42 ` Javier Martinez Canillas 2014-09-30 14:58 ` Abhilash Kesavan 0 siblings, 1 reply; 13+ messages in thread From: Javier Martinez Canillas @ 2014-09-30 14:42 UTC (permalink / raw) To: linux-arm-kernel Hello Abhilash, Thanks a lot for your quick reply. On Tue, Sep 30, 2014 at 4:24 PM, Abhilash Kesavan <kesavan.abhilash@gmail.com> wrote: > Hi Javier, > > On Tue, Sep 30, 2014 at 7:00 PM, Javier Martinez Canillas > <javier@dowhile0.org> wrote: >> Hello Vikas, >> >> Thanks a lot for the re-spin. >> >> On Tue, Sep 30, 2014 at 1:02 PM, Vikas Sajjan <vikas.sajjan@samsung.com> wrote: >>> >>> Tested on Kukjin Kim's tree, for-next branch + >>> 1] http://www.spinics.net/lists/linux-samsung-soc/msg33750.html >>> 2] https://lkml.org/lkml/2014/9/30/156 >> >> I wanted to test your series but I noticed that Abhilash's patch: >> >> "[PATCH v7] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420" >> >> does not apply cleanly on Kukjin's for-next branch. I see that all the >> dependencies mentioned (modulo $subject or course) have already been >> merged though. > > If you are looking to test this series right now then I can post an > untested rebased version. Otherwise, I will test it tomorrow and post. > Up to you. If is easy for you to post an untested version, that would be great and I can test it. But is OK if you prefer to do it tomorrow too. > Regards, > Abhilash >> Best regards, Javier ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v8 0/2] Adds PMU and S2R support for exynos5420 2014-09-30 14:42 ` Javier Martinez Canillas @ 2014-09-30 14:58 ` Abhilash Kesavan 2014-09-30 15:12 ` Javier Martinez Canillas 0 siblings, 1 reply; 13+ messages in thread From: Abhilash Kesavan @ 2014-09-30 14:58 UTC (permalink / raw) To: linux-arm-kernel HI Javier, On Tue, Sep 30, 2014 at 8:12 PM, Javier Martinez Canillas <javier@dowhile0.org> wrote: > Hello Abhilash, > > Thanks a lot for your quick reply. > > On Tue, Sep 30, 2014 at 4:24 PM, Abhilash Kesavan > <kesavan.abhilash@gmail.com> wrote: >> Hi Javier, >> >> On Tue, Sep 30, 2014 at 7:00 PM, Javier Martinez Canillas >> <javier@dowhile0.org> wrote: >>> Hello Vikas, >>> >>> Thanks a lot for the re-spin. >>> >>> On Tue, Sep 30, 2014 at 1:02 PM, Vikas Sajjan <vikas.sajjan@samsung.com> wrote: >>>> >>>> Tested on Kukjin Kim's tree, for-next branch + >>>> 1] http://www.spinics.net/lists/linux-samsung-soc/msg33750.html >>>> 2] https://lkml.org/lkml/2014/9/30/156 >>> >>> I wanted to test your series but I noticed that Abhilash's patch: >>> >>> "[PATCH v7] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420" >>> >>> does not apply cleanly on Kukjin's for-next branch. I see that all the >>> dependencies mentioned (modulo $subject or course) have already been >>> merged though. >> >> If you are looking to test this series right now then I can post an >> untested rebased version. Otherwise, I will test it tomorrow and post. >> > > Up to you. If is easy for you to post an untested version, that would > be great and I can test it. But is OK if you prefer to do it tomorrow > too. Just posted the rebased patch. Regards, Abhilash > >> Regards, >> Abhilash >>> > > Best regards, > Javier ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v8 0/2] Adds PMU and S2R support for exynos5420 2014-09-30 14:58 ` Abhilash Kesavan @ 2014-09-30 15:12 ` Javier Martinez Canillas 0 siblings, 0 replies; 13+ messages in thread From: Javier Martinez Canillas @ 2014-09-30 15:12 UTC (permalink / raw) To: linux-arm-kernel Hello Abhilash, On Tue, Sep 30, 2014 at 4:58 PM, Abhilash Kesavan <kesavan.abhilash@gmail.com> wrote: >>> >>> If you are looking to test this series right now then I can post an >>> untested rebased version. Otherwise, I will test it tomorrow and post. >>> >> >> Up to you. If is easy for you to post an untested version, that would >> be great and I can test it. But is OK if you prefer to do it tomorrow >> too. > > Just posted the rebased patch. > Perfect, thanks a lot for your help! Best regards, Javier ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v8 0/2] Adds PMU and S2R support for exynos5420 2014-09-30 13:30 ` [PATCH v8 0/2] Adds PMU and S2R support for exynos5420 Javier Martinez Canillas 2014-09-30 14:24 ` Abhilash Kesavan @ 2014-10-01 10:23 ` Vikas Sajjan 2014-10-01 13:50 ` Javier Martinez Canillas 1 sibling, 1 reply; 13+ messages in thread From: Vikas Sajjan @ 2014-10-01 10:23 UTC (permalink / raw) To: linux-arm-kernel HI Javier, On Tue, Sep 30, 2014 at 7:15 PM, Javier Martinez Canillas <javier@dowhile0.org> wrote: > Hello Vikas, > > Thanks a lot for the re-spin. > > On Tue, Sep 30, 2014 at 1:02 PM, Vikas Sajjan <vikas.sajjan@samsung.com> wrote: >> >> Tested on Kukjin Kim's tree, for-next branch + >> 1] http://www.spinics.net/lists/linux-samsung-soc/msg33750.html >> 2] https://lkml.org/lkml/2014/9/30/156 > > I wanted to test your series but I noticed that Abhilash's patch: > > "[PATCH v7] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420" > > does not apply cleanly on Kukjin's for-next branch. I see that all the > dependencies mentioned (modulo $subject or course) have already been > merged though. > > Did you rebase Abhilash's to test your series?. I can forward port as > well but just want to be sure that I'm not missing any other > dependency. > Yea, I did rebase abhilash's MCPM patch to test my series. > These are the patches I've on top of Kukjin's for-next branch fyi: > > 663dfa7 ARM: exynos5: Add Suspend-to-RAM support for 5420 > b4b3b76 ARM: exynos5: Add PMU support for 5420 > 6c0e381 ARM: EXYNOS: Move PMU specific definitions from common.h > cdf79fe ARM: EXYNOS: Add platform driver support for Exynos PMU > d2d8bc6 mfd: syscon: Decouple syscon interface from platform devices > My git log looks like below on top of Kukjin's for-next branch, d861ddd clk: exynos: Add CLK_IGNORE_UNUSED to aclk200_disp1 and aclk300_disp1 adc14dc POSTED: ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420 d61fc43 ARM: exynos5: Add Suspend-to-RAM support for 5420 3d1d7bd ARM: exynos5: Add PMU support for 5420 a8887b3 mfd: syscon: Decouple syscon interface from platform devices 072e2bc ARM: EXYNOS: Move PMU specific definitions from common.h ec2f950 ARM: EXYNOS: Add platform driver support for Exynos PMU recently I noticed that, without the CLK_IGNORE_UNUSED flag for aclk200_disp1 and aclk300_disp1 CLK, the system is NOT suspending, which was NOT the case when i had posted my previous revisions. diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 848d602..d8b6633 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -932,14 +932,14 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = { GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", GATE_BUS_TOP, 17, 0, 0), GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", - GATE_BUS_TOP, 18, 0, 0), + GATE_BUS_TOP, 18, CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", GATE_BUS_TOP, 28, 0, 0), GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m", GATE_BUS_TOP, 29, 0, 0), GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", - SRC_MASK_TOP2, 24, 0, 0), + SRC_MASK_TOP2, 24, CLK_IGNORE_UNUSED, 0), GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", SRC_MASK_TOP7, 20, 0, 0), Regards Vikas Sajjan > Best regards, > Javier ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v8 0/2] Adds PMU and S2R support for exynos5420 2014-10-01 10:23 ` Vikas Sajjan @ 2014-10-01 13:50 ` Javier Martinez Canillas 2014-10-02 14:24 ` Vikas Sajjan 0 siblings, 1 reply; 13+ messages in thread From: Javier Martinez Canillas @ 2014-10-01 13:50 UTC (permalink / raw) To: linux-arm-kernel Hello Vikas, On Wed, Oct 1, 2014 at 12:23 PM, Vikas Sajjan <vikas.sajjan@samsung.com> wrote: > > My git log looks like below on top of Kukjin's for-next branch, > > d861ddd clk: exynos: Add CLK_IGNORE_UNUSED to aclk200_disp1 and aclk300_disp1 > adc14dc POSTED: ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420 > d61fc43 ARM: exynos5: Add Suspend-to-RAM support for 5420 > 3d1d7bd ARM: exynos5: Add PMU support for 5420 > a8887b3 mfd: syscon: Decouple syscon interface from platform devices > 072e2bc ARM: EXYNOS: Move PMU specific definitions from common.h > ec2f950 ARM: EXYNOS: Add platform driver support for Exynos PMU > I tested Kukjin's for-next branch (HEAD in commit a84aaa7) + the patches you mentioned and the system enters in suspend mode but the RTC alarm IRQ does not make it resume. Is the branch you are using to test public so I can give it a try? > recently I noticed that, without the CLK_IGNORE_UNUSED flag for > aclk200_disp1 and aclk300_disp1 CLK, the system is NOT suspending, > which was NOT the case when i had posted my previous revisions. > I tried both with and without your patch that adds the CLK_IGNORE_UNUSED to aclk200_disp1 and aclk300_disp1 and in both cases it behaves the same, the system seems to go into suspend mode but never resumes: # echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state [ 105.376596] PM: Syncing filesystems ... done. [ 105.383207] Freezing user space processes ... (elapsed 0.001 seconds) done. [ 105.388681] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. [ 105.488589] wake enabled for irq 281 [ 105.491609] wake enabled for irq 280 [ 105.498102] wake enabled for irq 284 [ 105.554736] PM: suspend of devices complete after 155.406 msecs [ 105.562572] PM: late suspend of devices complete after 3.361 msecs [ 105.570389] PM: noirq suspend of devices complete after 3.102 msecs [ 105.575185] Disabling non-boot CPUs ... [ 105.579706] IRQ153 no longer affine to CPU1 [ 105.580008] CPU1: shutdown [ 105.587230] IRQ154 no longer affine to CPU2 [ 105.587472] CPU2: shutdown [ 105.594953] IRQ155 no longer affine to CPU3 [ 105.595190] CPU3: shutdown [ 105.602464] IRQ160 no longer affine to CPU4 [ 105.602979] CPU4: shutdown [ 105.609996] IRQ161 no longer affine to CPU5 [ 105.610424] CPU5: shutdown [ 105.617116] IRQ162 no longer affine to CPU6 [ 105.617557] CPU6: shutdown [ 105.625163] IRQ163 no longer affine to CPU7 [ 105.625596] CPU7: shutdown I'm testing on a Exynos5420 Peach Pit using exynos_defconfig and disabling CONFIG_BL_SWITCHER as you suggested. My bootargs is: console=ttySAC3,115200 debug earlyprintk root=/dev/mmcblk1p2 rootwait rw no_console_suspend And I'm booting using a chained nv-uboot with built version: U-Boot 2013.04-gb98ed09 (Mar 07 2014 - 12:25:37) for Peach I checked that the s3c2410-rtc alarm IRQ is fired correctly by looking at /sys/class/rtc/rtc0/wakealarm and also /proc/interrupts. Any ideas before I dig into this? Thanks a lot and best regards, Javier ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v8 0/2] Adds PMU and S2R support for exynos5420 2014-10-01 13:50 ` Javier Martinez Canillas @ 2014-10-02 14:24 ` Vikas Sajjan 2014-10-02 16:59 ` Javier Martinez Canillas 0 siblings, 1 reply; 13+ messages in thread From: Vikas Sajjan @ 2014-10-02 14:24 UTC (permalink / raw) To: linux-arm-kernel Hi Javier, On Wed, Oct 1, 2014 at 7:20 PM, Javier Martinez Canillas <javier@dowhile0.org> wrote: > Hello Vikas, > > On Wed, Oct 1, 2014 at 12:23 PM, Vikas Sajjan <vikas.sajjan@samsung.com> wrote: >> >> My git log looks like below on top of Kukjin's for-next branch, >> >> d861ddd clk: exynos: Add CLK_IGNORE_UNUSED to aclk200_disp1 and aclk300_disp1 >> adc14dc POSTED: ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420 >> d61fc43 ARM: exynos5: Add Suspend-to-RAM support for 5420 >> 3d1d7bd ARM: exynos5: Add PMU support for 5420 >> a8887b3 mfd: syscon: Decouple syscon interface from platform devices >> 072e2bc ARM: EXYNOS: Move PMU specific definitions from common.h >> ec2f950 ARM: EXYNOS: Add platform driver support for Exynos PMU >> > > I tested Kukjin's for-next branch (HEAD in commit a84aaa7) + the > patches you mentioned and the system enters in suspend mode but the > RTC alarm IRQ does not make it resume. Is the branch you are using to > test public so I can give it a try? > Not yet, but as I mentioned, I have only above mentioned 7 patches atop kukjin's for-next. only difference is the patch " ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420" which I had rebased myself. I am out of office till 7th October, once I am back, I can send you all those 7 patches, config file and S2R log. >> recently I noticed that, without the CLK_IGNORE_UNUSED flag for >> aclk200_disp1 and aclk300_disp1 CLK, the system is NOT suspending, >> which was NOT the case when i had posted my previous revisions. >> > > I tried both with and without your patch that adds the > CLK_IGNORE_UNUSED to aclk200_disp1 and aclk300_disp1 and in both cases > it behaves the same, the system seems to go into suspend mode but > never resumes: Can you confirm that the system has really suspended, I mean can you measure VDD_EGL or VDD_KFC and check or by any other method you know of. > > # echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state > [ 105.376596] PM: Syncing filesystems ... done. > [ 105.383207] Freezing user space processes ... (elapsed 0.001 seconds) done. > [ 105.388681] Freezing remaining freezable tasks ... (elapsed 0.001 > seconds) done. > [ 105.488589] wake enabled for irq 281 > [ 105.491609] wake enabled for irq 280 > [ 105.498102] wake enabled for irq 284 > [ 105.554736] PM: suspend of devices complete after 155.406 msecs > [ 105.562572] PM: late suspend of devices complete after 3.361 msecs > [ 105.570389] PM: noirq suspend of devices complete after 3.102 msecs > [ 105.575185] Disabling non-boot CPUs ... > [ 105.579706] IRQ153 no longer affine to CPU1 > [ 105.580008] CPU1: shutdown > [ 105.587230] IRQ154 no longer affine to CPU2 > [ 105.587472] CPU2: shutdown > [ 105.594953] IRQ155 no longer affine to CPU3 > [ 105.595190] CPU3: shutdown > [ 105.602464] IRQ160 no longer affine to CPU4 > [ 105.602979] CPU4: shutdown > [ 105.609996] IRQ161 no longer affine to CPU5 > [ 105.610424] CPU5: shutdown > [ 105.617116] IRQ162 no longer affine to CPU6 > [ 105.617557] CPU6: shutdown > [ 105.625163] IRQ163 no longer affine to CPU7 > [ 105.625596] CPU7: shutdown > > I'm testing on a Exynos5420 Peach Pit using exynos_defconfig and > disabling CONFIG_BL_SWITCHER as you suggested. My bootargs is: > I too tested on 5420 based peach-pit board with exynos_defconfig + disabled CONFIG_BL_SWITCHER. It did suspend and resume gracefully. > console=ttySAC3,115200 debug earlyprintk root=/dev/mmcblk1p2 rootwait > rw no_console_suspend > looks fine. > And I'm booting using a chained nv-uboot with built version: > > U-Boot 2013.04-gb98ed09 (Mar 07 2014 - 12:25:37) for Peach > I shall update my U-Boot build version, once I am back at office. > I checked that the s3c2410-rtc alarm IRQ is fired correctly by looking > at /sys/class/rtc/rtc0/wakealarm and also /proc/interrupts. > > Any ideas before I dig into this? > > Thanks a lot and best regards, > Javier > -- > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in > the body of a message to majordomo at vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v8 0/2] Adds PMU and S2R support for exynos5420 2014-10-02 14:24 ` Vikas Sajjan @ 2014-10-02 16:59 ` Javier Martinez Canillas 0 siblings, 0 replies; 13+ messages in thread From: Javier Martinez Canillas @ 2014-10-02 16:59 UTC (permalink / raw) To: linux-arm-kernel Hello Vikas, On Thu, Oct 2, 2014 at 4:24 PM, Vikas Sajjan <vikas.sajjan@samsung.com> wrote: > Hi Javier, > > On Wed, Oct 1, 2014 at 7:20 PM, Javier Martinez Canillas > <javier@dowhile0.org> wrote: >> Hello Vikas, >> >> On Wed, Oct 1, 2014 at 12:23 PM, Vikas Sajjan <vikas.sajjan@samsung.com> wrote: >>> >>> My git log looks like below on top of Kukjin's for-next branch, >>> >>> d861ddd clk: exynos: Add CLK_IGNORE_UNUSED to aclk200_disp1 and aclk300_disp1 >>> adc14dc POSTED: ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420 >>> d61fc43 ARM: exynos5: Add Suspend-to-RAM support for 5420 >>> 3d1d7bd ARM: exynos5: Add PMU support for 5420 >>> a8887b3 mfd: syscon: Decouple syscon interface from platform devices >>> 072e2bc ARM: EXYNOS: Move PMU specific definitions from common.h >>> ec2f950 ARM: EXYNOS: Add platform driver support for Exynos PMU >>> >> >> I tested Kukjin's for-next branch (HEAD in commit a84aaa7) + the >> patches you mentioned and the system enters in suspend mode but the >> RTC alarm IRQ does not make it resume. Is the branch you are using to >> test public so I can give it a try? >> > > Not yet, but as I mentioned, I have only above mentioned 7 patches > atop kukjin's for-next. > only difference is the patch " ARM: EXYNOS: Use MCPM call-backs to > support S2R on Exynos5420" > which I had rebased myself. > Yeah, I still don't know why is behaving differently. > I am out of office till 7th October, once I am back, I can send you > all those 7 patches, config file and S2R log. > Ok, thanks a lot. >>> recently I noticed that, without the CLK_IGNORE_UNUSED flag for >>> aclk200_disp1 and aclk300_disp1 CLK, the system is NOT suspending, >>> which was NOT the case when i had posted my previous revisions. >>> >> >> I tried both with and without your patch that adds the >> CLK_IGNORE_UNUSED to aclk200_disp1 and aclk300_disp1 and in both cases >> it behaves the same, the system seems to go into suspend mode but >> never resumes: > > Can you confirm that the system has really suspended, I mean can you > measure VDD_EGL or VDD_KFC and check or by any other method you know > of. > I'll see how I can measure but it seems the system is suspended correctly and the problem is on resuming (more on that below). >> >> # echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state >> [ 105.376596] PM: Syncing filesystems ... done. >> [ 105.383207] Freezing user space processes ... (elapsed 0.001 seconds) done. >> [ 105.388681] Freezing remaining freezable tasks ... (elapsed 0.001 >> seconds) done. >> [ 105.488589] wake enabled for irq 281 >> [ 105.491609] wake enabled for irq 280 >> [ 105.498102] wake enabled for irq 284 >> [ 105.554736] PM: suspend of devices complete after 155.406 msecs >> [ 105.562572] PM: late suspend of devices complete after 3.361 msecs >> [ 105.570389] PM: noirq suspend of devices complete after 3.102 msecs >> [ 105.575185] Disabling non-boot CPUs ... >> [ 105.579706] IRQ153 no longer affine to CPU1 >> [ 105.580008] CPU1: shutdown >> [ 105.587230] IRQ154 no longer affine to CPU2 >> [ 105.587472] CPU2: shutdown >> [ 105.594953] IRQ155 no longer affine to CPU3 >> [ 105.595190] CPU3: shutdown >> [ 105.602464] IRQ160 no longer affine to CPU4 >> [ 105.602979] CPU4: shutdown >> [ 105.609996] IRQ161 no longer affine to CPU5 >> [ 105.610424] CPU5: shutdown >> [ 105.617116] IRQ162 no longer affine to CPU6 >> [ 105.617557] CPU6: shutdown >> [ 105.625163] IRQ163 no longer affine to CPU7 >> [ 105.625596] CPU7: shutdown >> >> I'm testing on a Exynos5420 Peach Pit using exynos_defconfig and >> disabling CONFIG_BL_SWITCHER as you suggested. My bootargs is: >> > > I too tested on 5420 based peach-pit board with exynos_defconfig + > disabled CONFIG_BL_SWITCHER. > > It did suspend and resume gracefully. > I did further testing by enabling some PM debug options (CONFIG_PM_DEBUG and CONFIG_PM_ADVANCED_DEBUG) and tested different suspend modes (freezer, devices, processors and core). With the three first modes, s2r worked correctly but when trying the core mode the non-boot CPUs failed to come online again. I tested that this works on other Exynos SoCs (5250 and 4412): # grep -c processor /proc/cpuinfo 8 # echo core > /sys/power/pm_test # echo mem > /sys/power/state ... Enabling non-boot CPUs ... CPU1: failed to come online Error taking CPU1 up: -5 CPU2: failed to come online Error taking CPU2 up: -5 CPU3: failed to come online Error taking CPU3 up: -5 CPU4: failed to come online Error taking CPU4 up: -5 CPU5: failed to come online Error taking CPU5 up: -5 CPU6: failed to come online Error taking CPU6 up: -5 CPU7: failed to come online Error taking CPU7 up: -5 ... # grep -c processor /proc/cpuinfo 1 The -5 (-EIO) error is because even though the call to exynos_boot_secondary() succeeds in _cpu_up() [0], secondary_start_kernel() [1] is never called so the CPU is not marked as online nor the cpu_running completion handler is waked up. So waiting for it in _cpu_up() times out and cpu_online(cpu) is false. I still didn't figure out why the secondary CPUs are not jumping into their expected entry point so any hints are welcomed. >> console=ttySAC3,115200 debug earlyprintk root=/dev/mmcblk1p2 rootwait >> rw no_console_suspend >> > > looks fine. > >> And I'm booting using a chained nv-uboot with built version: >> >> U-Boot 2013.04-gb98ed09 (Mar 07 2014 - 12:25:37) for Peach >> > > I shall update my U-Boot build version, once I am back at office. > > Maybe that is the difference in our setups... Best regards, Javier [0]: http://lxr.free-electrons.com/source/arch/arm/kernel/smp.c#L91 [1]: http://lxr.free-electrons.com/source/arch/arm/kernel/smp.c#L330 ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2014-10-06 3:33 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-09-30 11:02 [PATCH v8 0/2] Adds PMU and S2R support for exynos5420 Vikas Sajjan 2014-09-30 11:02 ` [PATCH v8 1/2] ARM: exynos5: Add PMU support for 5420 Vikas Sajjan 2014-09-30 11:02 ` [PATCH v8 2/2] ARM: exynos5: Add Suspend-to-RAM " Vikas Sajjan 2014-10-06 3:33 ` Abhilash Kesavan 2014-09-30 13:30 ` [PATCH v8 0/2] Adds PMU and S2R support for exynos5420 Javier Martinez Canillas 2014-09-30 14:24 ` Abhilash Kesavan 2014-09-30 14:42 ` Javier Martinez Canillas 2014-09-30 14:58 ` Abhilash Kesavan 2014-09-30 15:12 ` Javier Martinez Canillas 2014-10-01 10:23 ` Vikas Sajjan 2014-10-01 13:50 ` Javier Martinez Canillas 2014-10-02 14:24 ` Vikas Sajjan 2014-10-02 16:59 ` Javier Martinez Canillas
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