[PATCH v2 0/2] ARM: implement cacheinfo support (for v7/v7m)

[PATCH v2 0/2] ARM: implement cacheinfo support (for v7/v7m)

[Dmitry Baryshkov]

Follow the ARM64 platform and implement simple cache information driver.
As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is
limited to the ARMv7 / ARMv7M, providing simple fallback or just
returning -EOPNOTSUPP in case of older platforms.

In theory we should be able to skip CLIDR reading and assume that Dcache
and Icache (or unified L1 cache) always exist if CTR is supported and
returns sensible value. However I think this better be handled by the
maintainers of corresponding platforms.

Other than just providing information to the userspace, this patchset is
required in order to implement L2 cache driver (and in the end CPU
frequency scaling) on ARMv7-based Qualcomm devices.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Changes in v2:
- Handle cores like ARM1176, which have cpu_architecture() ==
  CPU_ARCH_ARMv7 (because of VMSAv7 implementation), but no CLIDR
  register (because they are ARMv6) (Arnd).
- Link to v1: https://lore.kernel.org/r/20231231-armv7-cacheinfo-v1-0-9e8d440b59d9@linaro.org

---
Dmitry Baryshkov (2):
      ARM: add CLIDR accessor functions
      ARM: implement cacheinfo support

 arch/arm/Kconfig                 |   1 +
 arch/arm/include/asm/cache.h     |   6 ++
 arch/arm/include/asm/cachetype.h |  13 +++
 arch/arm/kernel/Makefile         |   1 +
 arch/arm/kernel/cacheinfo.c      | 173 +++++++++++++++++++++++++++++++++++++++
 include/linux/cacheinfo.h        |   2 +-
 6 files changed, 195 insertions(+), 1 deletion(-)
---
base-commit: 7f773fd61baa9b136faa5c4e6555aa64c758d07c
change-id: 20231231-armv7-cacheinfo-9fa533ae371e

Best regards,
-- 
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

[PATCH v2 1/2] ARM: add CLIDR accessor functions

[Dmitry Baryshkov]

Add functions to read the CLIDR, Cache Level ID Register.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/include/asm/cachetype.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/include/asm/cachetype.h b/arch/arm/include/asm/cachetype.h
index b9dbe1d4c8fe..b01c59076b84 100644
--- a/arch/arm/include/asm/cachetype.h
+++ b/arch/arm/include/asm/cachetype.h
@@ -83,6 +83,14 @@ static inline unsigned int read_ccsidr(void)
 	asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));
 	return val;
 }
+
+static inline unsigned int read_clidr(void)
+{
+	unsigned int val;
+
+	asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (val));
+	return val;
+}
 #else /* CONFIG_CPU_V7M */
 #include <linux/io.h>
 #include "asm/v7m.h"
@@ -96,6 +104,11 @@ static inline unsigned int read_ccsidr(void)
 {
 	return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR);
 }
+
+static inline unsigned int read_clidr(void)
+{
+	return readl(BASEADDR_V7M_SCB + V7M_SCB_CLIDR);
+}
 #endif
 
 #endif

-- 
2.39.5

Re: [PATCH v2 1/2] ARM: add CLIDR accessor functions

[Linus Walleij]

On Mon, Oct 14, 2024 at 3:55 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:

> Add functions to read the CLIDR, Cache Level ID Register.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

[PATCH v2 2/2] ARM: implement cacheinfo support

[Dmitry Baryshkov]

On ARMv7 / v7m machines read CTR and CLIDR registers to provide
information regarding the cache topology. Earlier machines should
describe full cache topology in the device tree.

Note, this follows the ARM64 cacheinfo support and provides only minimal
support required to bootstrap cache info. All useful properties should
be decribed in Device Tree.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/Kconfig             |   1 +
 arch/arm/include/asm/cache.h |   6 ++
 arch/arm/kernel/Makefile     |   1 +
 arch/arm/kernel/cacheinfo.c  | 173 +++++++++++++++++++++++++++++++++++++++++++
 include/linux/cacheinfo.h    |   2 +-
 5 files changed, 182 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 749179a1d162..e790543c3eaf 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -5,6 +5,7 @@ config ARM
 	select ARCH_32BIT_OFF_T
 	select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND
 	select ARCH_HAS_BINFMT_FLAT
+	select ARCH_HAS_CACHE_LINE_SIZE if OF
 	select ARCH_HAS_CPU_CACHE_ALIASING
 	select ARCH_HAS_CPU_FINALIZE_INIT if MMU
 	select ARCH_HAS_CURRENT_STACK_POINTER
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index e3ea34558ada..ecbc100d22a5 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -26,4 +26,10 @@
 
 #define __read_mostly __section(".data..read_mostly")
 
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_ARCH_HAS_CACHE_LINE_SIZE
+int cache_line_size(void);
+#endif
+#endif
+
 #endif
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index aaae31b8c4a5..b3333d070390 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -40,6 +40,7 @@ obj-y		+= entry-armv.o
 endif
 
 obj-$(CONFIG_MMU)		+= bugs.o
+obj-$(CONFIG_OF)		+= cacheinfo.o
 obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
 obj-$(CONFIG_ISA_DMA_API)	+= dma.o
 obj-$(CONFIG_FIQ)		+= fiq.o fiqasm.o
diff --git a/arch/arm/kernel/cacheinfo.c b/arch/arm/kernel/cacheinfo.c
new file mode 100644
index 000000000000..a8eabcaa18d8
--- /dev/null
+++ b/arch/arm/kernel/cacheinfo.c
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ *  ARM cacheinfo support
+ *
+ *  Copyright (C) 2023 Linaro Ltd.
+ *  Copyright (C) 2015 ARM Ltd.
+ *  All Rights Reserved
+ */
+
+#include <linux/bitfield.h>
+#include <linux/cacheinfo.h>
+#include <linux/of.h>
+
+#include <asm/cachetype.h>
+#include <asm/cputype.h>
+#include <asm/system_info.h>
+
+/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
+#define CLIDR_CTYPE_SHIFT(level)	(3 * (level - 1))
+#define CLIDR_CTYPE_MASK(level)		(7 << CLIDR_CTYPE_SHIFT(level))
+#define CLIDR_CTYPE(clidr, level)	\
+	(((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
+
+#define MAX_CACHE_LEVEL			7	/* Max 7 level supported */
+
+#define CTR_FORMAT_MASK	GENMASK(27, 24)
+#define CTR_FORMAT_ARMV6 0
+#define CTR_FORMAT_ARMV7 4
+#define CTR_CWG_MASK	GENMASK(27, 24)
+#define CTR_DSIZE_LEN_MASK GENMASK(13, 12)
+#define CTR_ISIZE_LEN_MASK GENMASK(1, 0)
+
+/* Also valid for v7m */
+static inline int cache_line_size_cp15(void)
+{
+	u32 ctr = read_cpuid_cachetype();
+	u32 format = FIELD_GET(CTR_FORMAT_MASK, ctr);
+
+	if (format == CTR_FORMAT_ARMV7) {
+		u32 cwg = FIELD_GET(CTR_CWG_MASK, ctr);
+
+		return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
+	} else if (WARN_ON_ONCE(format != CTR_FORMAT_ARMV6)) {
+		return ARCH_DMA_MINALIGN;
+	}
+
+	return 8 << max(FIELD_GET(CTR_ISIZE_LEN_MASK, ctr),
+			FIELD_GET(CTR_DSIZE_LEN_MASK, ctr));
+}
+
+int cache_line_size(void)
+{
+	if (coherency_max_size != 0)
+		return coherency_max_size;
+
+	/* CP15 is optional / implementation defined before ARMv6 */
+	if (cpu_architecture() < CPU_ARCH_ARMv6)
+		return ARCH_DMA_MINALIGN;
+
+	return cache_line_size_cp15();
+}
+EXPORT_SYMBOL_GPL(cache_line_size);
+
+static inline enum cache_type get_cache_type(int level)
+{
+	u32 clidr;
+
+	if (level > MAX_CACHE_LEVEL)
+		return CACHE_TYPE_NOCACHE;
+
+	clidr = read_clidr();
+
+	return CLIDR_CTYPE(clidr, level);
+}
+
+static void ci_leaf_init(struct cacheinfo *this_leaf,
+			 enum cache_type type, unsigned int level)
+{
+	this_leaf->level = level;
+	this_leaf->type = type;
+}
+
+static int detect_cache_level(unsigned int *level_p, unsigned int *leaves_p)
+{
+	unsigned int ctype, level, leaves;
+	u32 ctr, format;
+
+	/* CLIDR is not present before ARMv7/v7m */
+	if (cpu_architecture() < CPU_ARCH_ARMv7)
+		return -EOPNOTSUPP;
+
+	/* Don't try reading CLIDR if CTR declares old format */
+	ctr = read_cpuid_cachetype();
+	format = FIELD_GET(CTR_FORMAT_MASK, ctr);
+	if (format != CTR_FORMAT_ARMV7)
+		return -EOPNOTSUPP;
+
+	for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) {
+		ctype = get_cache_type(level);
+		if (ctype == CACHE_TYPE_NOCACHE) {
+			level--;
+			break;
+		}
+		/* Separate instruction and data caches */
+		leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1;
+	}
+
+	*level_p = level;
+	*leaves_p = leaves;
+
+	return 0;
+}
+
+int early_cache_level(unsigned int cpu)
+{
+	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
+
+	return detect_cache_level(&this_cpu_ci->num_levels, &this_cpu_ci->num_leaves);
+}
+
+int init_cache_level(unsigned int cpu)
+{
+	unsigned int level, leaves;
+	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
+	int fw_level;
+	int ret;
+
+	ret = detect_cache_level(&level, &leaves);
+	if (ret)
+		return ret;
+
+	fw_level = of_find_last_cache_level(cpu);
+
+	if (level < fw_level) {
+		/*
+		 * some external caches not specified in CLIDR_EL1
+		 * the information may be available in the device tree
+		 * only unified external caches are considered here
+		 */
+		leaves += (fw_level - level);
+		level = fw_level;
+	}
+
+	this_cpu_ci->num_levels = level;
+	this_cpu_ci->num_leaves = leaves;
+	return 0;
+}
+
+int populate_cache_leaves(unsigned int cpu)
+{
+	unsigned int level, idx;
+	enum cache_type type;
+	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
+	struct cacheinfo *this_leaf = this_cpu_ci->info_list;
+	unsigned int arch = cpu_architecture();
+
+	/* CLIDR is not present before ARMv7/v7m */
+	if (arch < CPU_ARCH_ARMv7)
+		return -EOPNOTSUPP;
+
+	for (idx = 0, level = 1; level <= this_cpu_ci->num_levels &&
+	     idx < this_cpu_ci->num_leaves; idx++, level++) {
+		type = get_cache_type(level);
+		if (type == CACHE_TYPE_SEPARATE) {
+			ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
+			ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
+		} else {
+			ci_leaf_init(this_leaf++, type, level);
+		}
+	}
+
+	return 0;
+}
diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h
index 108060612bb8..1e7061549fc7 100644
--- a/include/linux/cacheinfo.h
+++ b/include/linux/cacheinfo.h
@@ -147,7 +147,7 @@ static inline int get_cpu_cacheinfo_id(int cpu, int level)
 	return ci ? ci->id : -1;
 }
 
-#ifdef CONFIG_ARM64
+#if defined(CONFIG_ARM64) || defined(CONFIG_ARM)
 #define use_arch_cache_info()	(true)
 #else
 #define use_arch_cache_info()	(false)

-- 
2.39.5

Re: [PATCH v2 2/2] ARM: implement cacheinfo support

[Linus Walleij]

On Mon, Oct 14, 2024 at 3:56 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:

> On ARMv7 / v7m machines read CTR and CLIDR registers to provide
> information regarding the cache topology. Earlier machines should
> describe full cache topology in the device tree.
>
> Note, this follows the ARM64 cacheinfo support and provides only minimal
> support required to bootstrap cache info. All useful properties should
> be decribed in Device Tree.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

It's really neat actually!

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

Re: [PATCH v2 2/2] ARM: implement cacheinfo support

[Marek Szyprowski]

On 14.10.2024 15:55, Dmitry Baryshkov wrote:
> On ARMv7 / v7m machines read CTR and CLIDR registers to provide
> information regarding the cache topology. Earlier machines should
> describe full cache topology in the device tree.
>
> Note, this follows the ARM64 cacheinfo support and provides only minimal
> support required to bootstrap cache info. All useful properties should
> be decribed in Device Tree.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>   arch/arm/Kconfig             |   1 +
>   arch/arm/include/asm/cache.h |   6 ++
>   arch/arm/kernel/Makefile     |   1 +
>   arch/arm/kernel/cacheinfo.c  | 173 +++++++++++++++++++++++++++++++++++++++++++
>   include/linux/cacheinfo.h    |   2 +-
>   5 files changed, 182 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 749179a1d162..e790543c3eaf 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -5,6 +5,7 @@ config ARM
>   	select ARCH_32BIT_OFF_T
>   	select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND
>   	select ARCH_HAS_BINFMT_FLAT
> +	select ARCH_HAS_CACHE_LINE_SIZE if OF
>   	select ARCH_HAS_CPU_CACHE_ALIASING
>   	select ARCH_HAS_CPU_FINALIZE_INIT if MMU
>   	select ARCH_HAS_CURRENT_STACK_POINTER
> diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
> index e3ea34558ada..ecbc100d22a5 100644
> --- a/arch/arm/include/asm/cache.h
> +++ b/arch/arm/include/asm/cache.h
> @@ -26,4 +26,10 @@
>   
>   #define __read_mostly __section(".data..read_mostly")
>   
> +#ifndef __ASSEMBLY__
> +#ifdef CONFIG_ARCH_HAS_CACHE_LINE_SIZE
> +int cache_line_size(void);
> +#endif
> +#endif
> +
>   #endif
> diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
> index aaae31b8c4a5..b3333d070390 100644
> --- a/arch/arm/kernel/Makefile
> +++ b/arch/arm/kernel/Makefile
> @@ -40,6 +40,7 @@ obj-y		+= entry-armv.o
>   endif
>   
>   obj-$(CONFIG_MMU)		+= bugs.o
> +obj-$(CONFIG_OF)		+= cacheinfo.o
>   obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
>   obj-$(CONFIG_ISA_DMA_API)	+= dma.o
>   obj-$(CONFIG_FIQ)		+= fiq.o fiqasm.o
> diff --git a/arch/arm/kernel/cacheinfo.c b/arch/arm/kernel/cacheinfo.c
> new file mode 100644
> index 000000000000..a8eabcaa18d8
> --- /dev/null
> +++ b/arch/arm/kernel/cacheinfo.c
> @@ -0,0 +1,173 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + *  ARM cacheinfo support
> + *
> + *  Copyright (C) 2023 Linaro Ltd.
> + *  Copyright (C) 2015 ARM Ltd.
> + *  All Rights Reserved
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/cacheinfo.h>
> +#include <linux/of.h>
> +
> +#include <asm/cachetype.h>
> +#include <asm/cputype.h>
> +#include <asm/system_info.h>
> +
> +/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
> +#define CLIDR_CTYPE_SHIFT(level)	(3 * (level - 1))
> +#define CLIDR_CTYPE_MASK(level)		(7 << CLIDR_CTYPE_SHIFT(level))
> +#define CLIDR_CTYPE(clidr, level)	\
> +	(((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
> +
> +#define MAX_CACHE_LEVEL			7	/* Max 7 level supported */
> +
> +#define CTR_FORMAT_MASK	GENMASK(27, 24)
> +#define CTR_FORMAT_ARMV6 0
> +#define CTR_FORMAT_ARMV7 4
> +#define CTR_CWG_MASK	GENMASK(27, 24)
> +#define CTR_DSIZE_LEN_MASK GENMASK(13, 12)
> +#define CTR_ISIZE_LEN_MASK GENMASK(1, 0)
> +
> +/* Also valid for v7m */
> +static inline int cache_line_size_cp15(void)
> +{
> +	u32 ctr = read_cpuid_cachetype();
> +	u32 format = FIELD_GET(CTR_FORMAT_MASK, ctr);
> +

On Samsung Exynos421x (CortexA9 based) format is read as 0x3, which 
causes a warning later in the code. How such value should be handled to 
avoid warning?

> +	if (format == CTR_FORMAT_ARMV7) {
> +		u32 cwg = FIELD_GET(CTR_CWG_MASK, ctr);
> +
> +		return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
> +	} else if (WARN_ON_ONCE(format != CTR_FORMAT_ARMV6)) {
> +		return ARCH_DMA_MINALIGN;
> +	}
> +
> +	return 8 << max(FIELD_GET(CTR_ISIZE_LEN_MASK, ctr),
> +			FIELD_GET(CTR_DSIZE_LEN_MASK, ctr));
> +}
> +

> >...

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Re: [PATCH v2 2/2] ARM: implement cacheinfo support

[Dmitry Baryshkov]

On Wed, Jan 15, 2025 at 11:11:57AM +0100, Marek Szyprowski wrote:
> On 14.10.2024 15:55, Dmitry Baryshkov wrote:
> > On ARMv7 / v7m machines read CTR and CLIDR registers to provide
> > information regarding the cache topology. Earlier machines should
> > describe full cache topology in the device tree.
> >
> > Note, this follows the ARM64 cacheinfo support and provides only minimal
> > support required to bootstrap cache info. All useful properties should
> > be decribed in Device Tree.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> >   arch/arm/Kconfig             |   1 +
> >   arch/arm/include/asm/cache.h |   6 ++
> >   arch/arm/kernel/Makefile     |   1 +
> >   arch/arm/kernel/cacheinfo.c  | 173 +++++++++++++++++++++++++++++++++++++++++++
> >   include/linux/cacheinfo.h    |   2 +-
> >   5 files changed, 182 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index 749179a1d162..e790543c3eaf 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -5,6 +5,7 @@ config ARM
> >   	select ARCH_32BIT_OFF_T
> >   	select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND
> >   	select ARCH_HAS_BINFMT_FLAT
> > +	select ARCH_HAS_CACHE_LINE_SIZE if OF
> >   	select ARCH_HAS_CPU_CACHE_ALIASING
> >   	select ARCH_HAS_CPU_FINALIZE_INIT if MMU
> >   	select ARCH_HAS_CURRENT_STACK_POINTER
> > diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
> > index e3ea34558ada..ecbc100d22a5 100644
> > --- a/arch/arm/include/asm/cache.h
> > +++ b/arch/arm/include/asm/cache.h
> > @@ -26,4 +26,10 @@
> >   
> >   #define __read_mostly __section(".data..read_mostly")
> >   
> > +#ifndef __ASSEMBLY__
> > +#ifdef CONFIG_ARCH_HAS_CACHE_LINE_SIZE
> > +int cache_line_size(void);
> > +#endif
> > +#endif
> > +
> >   #endif
> > diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
> > index aaae31b8c4a5..b3333d070390 100644
> > --- a/arch/arm/kernel/Makefile
> > +++ b/arch/arm/kernel/Makefile
> > @@ -40,6 +40,7 @@ obj-y		+= entry-armv.o
> >   endif
> >   
> >   obj-$(CONFIG_MMU)		+= bugs.o
> > +obj-$(CONFIG_OF)		+= cacheinfo.o
> >   obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
> >   obj-$(CONFIG_ISA_DMA_API)	+= dma.o
> >   obj-$(CONFIG_FIQ)		+= fiq.o fiqasm.o
> > diff --git a/arch/arm/kernel/cacheinfo.c b/arch/arm/kernel/cacheinfo.c
> > new file mode 100644
> > index 000000000000..a8eabcaa18d8
> > --- /dev/null
> > +++ b/arch/arm/kernel/cacheinfo.c
> > @@ -0,0 +1,173 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + *  ARM cacheinfo support
> > + *
> > + *  Copyright (C) 2023 Linaro Ltd.
> > + *  Copyright (C) 2015 ARM Ltd.
> > + *  All Rights Reserved
> > + */
> > +
> > +#include <linux/bitfield.h>
> > +#include <linux/cacheinfo.h>
> > +#include <linux/of.h>
> > +
> > +#include <asm/cachetype.h>
> > +#include <asm/cputype.h>
> > +#include <asm/system_info.h>
> > +
> > +/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
> > +#define CLIDR_CTYPE_SHIFT(level)	(3 * (level - 1))
> > +#define CLIDR_CTYPE_MASK(level)		(7 << CLIDR_CTYPE_SHIFT(level))
> > +#define CLIDR_CTYPE(clidr, level)	\
> > +	(((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
> > +
> > +#define MAX_CACHE_LEVEL			7	/* Max 7 level supported */
> > +
> > +#define CTR_FORMAT_MASK	GENMASK(27, 24)
> > +#define CTR_FORMAT_ARMV6 0
> > +#define CTR_FORMAT_ARMV7 4
> > +#define CTR_CWG_MASK	GENMASK(27, 24)
> > +#define CTR_DSIZE_LEN_MASK GENMASK(13, 12)
> > +#define CTR_ISIZE_LEN_MASK GENMASK(1, 0)
> > +
> > +/* Also valid for v7m */
> > +static inline int cache_line_size_cp15(void)
> > +{
> > +	u32 ctr = read_cpuid_cachetype();
> > +	u32 format = FIELD_GET(CTR_FORMAT_MASK, ctr);
> > +
> 
> On Samsung Exynos421x (CortexA9 based) format is read as 0x3, which 
> causes a warning later in the code. How such value should be handled to 
> avoid warning?

I should be more carefull when doing c&p. I've posted the fix at
https://lore.kernel.org/r/20250115-arm-cacheinfo-fix-v1-1-5f30eeb4e463@linaro.org

> 
> > +	if (format == CTR_FORMAT_ARMV7) {
> > +		u32 cwg = FIELD_GET(CTR_CWG_MASK, ctr);
> > +
> > +		return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
> > +	} else if (WARN_ON_ONCE(format != CTR_FORMAT_ARMV6)) {
> > +		return ARCH_DMA_MINALIGN;
> > +	}
> > +
> > +	return 8 << max(FIELD_GET(CTR_ISIZE_LEN_MASK, ctr),
> > +			FIELD_GET(CTR_DSIZE_LEN_MASK, ctr));
> > +}
> > +
> 
> > >...
> 
> Best regards
> -- 
> Marek Szyprowski, PhD
> Samsung R&D Institute Poland
> 

-- 
With best wishes
Dmitry

Re: [PATCH v2 0/2] ARM: implement cacheinfo support (for v7/v7m)

[Dmitry Baryshkov]

On Mon, Oct 14, 2024 at 04:55:19PM +0300, Dmitry Baryshkov wrote:
> Follow the ARM64 platform and implement simple cache information driver.
> As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is
> limited to the ARMv7 / ARMv7M, providing simple fallback or just
> returning -EOPNOTSUPP in case of older platforms.
> 
> In theory we should be able to skip CLIDR reading and assume that Dcache
> and Icache (or unified L1 cache) always exist if CTR is supported and
> returns sensible value. However I think this better be handled by the
> maintainers of corresponding platforms.
> 
> Other than just providing information to the userspace, this patchset is
> required in order to implement L2 cache driver (and in the end CPU
> frequency scaling) on ARMv7-based Qualcomm devices.

Sudeep, Ard, Arnd, Russell, I have been struggling to get reviews for
this for several months. Is there a chance to hear anything? I'd really
like to scratch this off my 'pending' list.

> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> Changes in v2:
> - Handle cores like ARM1176, which have cpu_architecture() ==
>   CPU_ARCH_ARMv7 (because of VMSAv7 implementation), but no CLIDR
>   register (because they are ARMv6) (Arnd).
> - Link to v1: https://lore.kernel.org/r/20231231-armv7-cacheinfo-v1-0-9e8d440b59d9@linaro.org

-- 
With best wishes
Dmitry

Re: [PATCH v2 0/2] ARM: implement cacheinfo support (for v7/v7m)

[Ard Biesheuvel]

(cc Linus)

On Mon, 4 Nov 2024 at 12:51, Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On Mon, Oct 14, 2024 at 04:55:19PM +0300, Dmitry Baryshkov wrote:
> > Follow the ARM64 platform and implement simple cache information driver.
> > As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is
> > limited to the ARMv7 / ARMv7M, providing simple fallback or just
> > returning -EOPNOTSUPP in case of older platforms.
> >
> > In theory we should be able to skip CLIDR reading and assume that Dcache
> > and Icache (or unified L1 cache) always exist if CTR is supported and
> > returns sensible value. However I think this better be handled by the
> > maintainers of corresponding platforms.
> >
> > Other than just providing information to the userspace, this patchset is
> > required in order to implement L2 cache driver (and in the end CPU
> > frequency scaling) on ARMv7-based Qualcomm devices.
>
> Sudeep, Ard, Arnd, Russell, I have been struggling to get reviews for
> this for several months. Is there a chance to hear anything? I'd really
> like to scratch this off my 'pending' list.
>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > Changes in v2:
> > - Handle cores like ARM1176, which have cpu_architecture() ==
> >   CPU_ARCH_ARMv7 (because of VMSAv7 implementation), but no CLIDR
> >   register (because they are ARMv6) (Arnd).
> > - Link to v1: https://lore.kernel.org/r/20231231-armv7-cacheinfo-v1-0-9e8d440b59d9@linaro.org
>
> --
> With best wishes
> Dmitry

Re: [PATCH v2 0/2] ARM: implement cacheinfo support (for v7/v7m)

[Linus Walleij]

Hi Dmitry,

On Mon, Oct 14, 2024 at 3:55 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:

> Follow the ARM64 platform and implement simple cache information driver.
> As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is
> limited to the ARMv7 / ARMv7M, providing simple fallback or just
> returning -EOPNOTSUPP in case of older platforms.
>
> In theory we should be able to skip CLIDR reading and assume that Dcache
> and Icache (or unified L1 cache) always exist if CTR is supported and
> returns sensible value. However I think this better be handled by the
> maintainers of corresponding platforms.
>
> Other than just providing information to the userspace, this patchset is
> required in order to implement L2 cache driver (and in the end CPU
> frequency scaling) on ARMv7-based Qualcomm devices.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

I added my review tags to the v2 patches, can you put them
into Russell's patch tracker?

Yours,
Linus Walleij

Re: [PATCH v2 0/2] ARM: implement cacheinfo support (for v7/v7m)

[Dmitry Baryshkov]

On Thu, Nov 07, 2024 at 02:55:55PM +0100, Linus Walleij wrote:
> Hi Dmitry,
> 
> On Mon, Oct 14, 2024 at 3:55 PM Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
> 
> > Follow the ARM64 platform and implement simple cache information driver.
> > As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is
> > limited to the ARMv7 / ARMv7M, providing simple fallback or just
> > returning -EOPNOTSUPP in case of older platforms.
> >
> > In theory we should be able to skip CLIDR reading and assume that Dcache
> > and Icache (or unified L1 cache) always exist if CTR is supported and
> > returns sensible value. However I think this better be handled by the
> > maintainers of corresponding platforms.
> >
> > Other than just providing information to the userspace, this patchset is
> > required in order to implement L2 cache driver (and in the end CPU
> > frequency scaling) on ARMv7-based Qualcomm devices.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> 
> I added my review tags to the v2 patches, can you put them
> into Russell's patch tracker?

Done, 9432/1 and 9433/1, thank you!

-- 
With best wishes
Dmitry

Re: [PATCH v2 0/2] ARM: implement cacheinfo support (for v7/v7m)

[Dmitry Baryshkov]

On Thu, Nov 07, 2024 at 04:34:36PM +0200, Dmitry Baryshkov wrote:
> On Thu, Nov 07, 2024 at 02:55:55PM +0100, Linus Walleij wrote:
> > Hi Dmitry,
> > 
> > On Mon, Oct 14, 2024 at 3:55 PM Dmitry Baryshkov
> > <dmitry.baryshkov@linaro.org> wrote:
> > 
> > > Follow the ARM64 platform and implement simple cache information driver.
> > > As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is
> > > limited to the ARMv7 / ARMv7M, providing simple fallback or just
> > > returning -EOPNOTSUPP in case of older platforms.
> > >
> > > In theory we should be able to skip CLIDR reading and assume that Dcache
> > > and Icache (or unified L1 cache) always exist if CTR is supported and
> > > returns sensible value. However I think this better be handled by the
> > > maintainers of corresponding platforms.
> > >
> > > Other than just providing information to the userspace, this patchset is
> > > required in order to implement L2 cache driver (and in the end CPU
> > > frequency scaling) on ARMv7-based Qualcomm devices.
> > >
> > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > 
> > I added my review tags to the v2 patches, can you put them
> > into Russell's patch tracker?
> 
> Done, 9432/1 and 9433/1, thank you!

These patches are still in the patch tracker in the "Incoming" state.

Russell, Linus (and Sudeep, Ard, Arnd), is there anything blocking them
from being accepted?

-- 
With best wishes
Dmitry

Re: [PATCH v2 0/2] ARM: implement cacheinfo support (for v7/v7m)

[Linus Walleij]

On Fri, Jan 3, 2025 at 6:55 AM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
> On Thu, Nov 07, 2024 at 04:34:36PM +0200, Dmitry Baryshkov wrote:
> > On Thu, Nov 07, 2024 at 02:55:55PM +0100, Linus Walleij wrote:
> > > Hi Dmitry,
> > >
> > > On Mon, Oct 14, 2024 at 3:55 PM Dmitry Baryshkov
> > > <dmitry.baryshkov@linaro.org> wrote:
> > >
> > > > Follow the ARM64 platform and implement simple cache information driver.
> > > > As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is
> > > > limited to the ARMv7 / ARMv7M, providing simple fallback or just
> > > > returning -EOPNOTSUPP in case of older platforms.
> > > >
> > > > In theory we should be able to skip CLIDR reading and assume that Dcache
> > > > and Icache (or unified L1 cache) always exist if CTR is supported and
> > > > returns sensible value. However I think this better be handled by the
> > > > maintainers of corresponding platforms.
> > > >
> > > > Other than just providing information to the userspace, this patchset is
> > > > required in order to implement L2 cache driver (and in the end CPU
> > > > frequency scaling) on ARMv7-based Qualcomm devices.
> > > >
> > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > >
> > > I added my review tags to the v2 patches, can you put them
> > > into Russell's patch tracker?
> >
> > Done, 9432/1 and 9433/1, thank you!
>
> These patches are still in the patch tracker in the "Incoming" state.
>
> Russell, Linus (and Sudeep, Ard, Arnd), is there anything blocking them
> from being accepted?

I added my Reviewed-by, perhaps rebase them on v6.13-rc1 so
Russell knows it applies cleanly? (It's pretty straight-forward to
supercede a patch in the tracker.)

Yours,
Linus Walleij

Re: [PATCH v2 0/2] ARM: implement cacheinfo support (for v7/v7m)

[Dmitry Baryshkov]

On Mon, Jan 13, 2025 at 04:07:36PM +0100, Linus Walleij wrote:
> On Fri, Jan 3, 2025 at 6:55 AM Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
> > On Thu, Nov 07, 2024 at 04:34:36PM +0200, Dmitry Baryshkov wrote:
> > > On Thu, Nov 07, 2024 at 02:55:55PM +0100, Linus Walleij wrote:
> > > > Hi Dmitry,
> > > >
> > > > On Mon, Oct 14, 2024 at 3:55 PM Dmitry Baryshkov
> > > > <dmitry.baryshkov@linaro.org> wrote:
> > > >
> > > > > Follow the ARM64 platform and implement simple cache information driver.
> > > > > As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is
> > > > > limited to the ARMv7 / ARMv7M, providing simple fallback or just
> > > > > returning -EOPNOTSUPP in case of older platforms.
> > > > >
> > > > > In theory we should be able to skip CLIDR reading and assume that Dcache
> > > > > and Icache (or unified L1 cache) always exist if CTR is supported and
> > > > > returns sensible value. However I think this better be handled by the
> > > > > maintainers of corresponding platforms.
> > > > >
> > > > > Other than just providing information to the userspace, this patchset is
> > > > > required in order to implement L2 cache driver (and in the end CPU
> > > > > frequency scaling) on ARMv7-based Qualcomm devices.
> > > > >
> > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > >
> > > > I added my review tags to the v2 patches, can you put them
> > > > into Russell's patch tracker?
> > >
> > > Done, 9432/1 and 9433/1, thank you!
> >
> > These patches are still in the patch tracker in the "Incoming" state.
> >
> > Russell, Linus (and Sudeep, Ard, Arnd), is there anything blocking them
> > from being accepted?
> 
> I added my Reviewed-by, perhaps rebase them on v6.13-rc1 so
> Russell knows it applies cleanly? (It's pretty straight-forward to
> supercede a patch in the tracker.)

Done, let's hope they finally get picked up by Russell.

-- 
With best wishes
Dmitry