* [PATCH 0/3] ARM: EXYNOS: Add support for GPIO on Exynos4x12
@ 2012-08-28 10:01 Tomasz Figa
2012-08-28 10:06 ` [PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx Tomasz Figa
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: Tomasz Figa @ 2012-08-28 10:01 UTC (permalink / raw)
To: linux-arm-kernel
This patch series makes necessary preparations and adds support for GPIO on
Exynos4x12 SoCs.
Tomasz Figa (3):
ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
gpio: samsung: Add support for Exynos4x12 SoCs
ARM: EXYNOS: Add support for FIMC cam port B GPIO setup on Exynos4x12
arch/arm/mach-exynos/include/mach/gpio.h | 58 ++++--
arch/arm/mach-exynos/include/mach/irqs.h | 6 -
arch/arm/mach-exynos/mach-nuri.c | 16 +-
arch/arm/mach-exynos/mach-origen.c | 6 +-
arch/arm/mach-exynos/mach-trats.c | 4 +-
arch/arm/mach-exynos/mach-universal_c210.c | 32 ++--
arch/arm/mach-exynos/setup-fimc.c | 21 ++-
drivers/gpio/gpio-samsung.c | 351
++++++++++++++++++++++++----
8 files changed, 399 insertions(+), 95 deletions(-)
--
1.7.8.6
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
2012-08-28 10:01 [PATCH 0/3] ARM: EXYNOS: Add support for GPIO on Exynos4x12 Tomasz Figa
@ 2012-08-28 10:06 ` Tomasz Figa
2012-08-28 14:48 ` Thomas Abraham
2012-08-28 23:44 ` Kukjin Kim
2012-08-28 10:06 ` [PATCH 2/3] gpio: samsung: Add support for Exynos4x12 SoCs Tomasz Figa
` (2 subsequent siblings)
3 siblings, 2 replies; 12+ messages in thread
From: Tomasz Figa @ 2012-08-28 10:06 UTC (permalink / raw)
To: linux-arm-kernel
The GPEx gpios are specific to Exynos4210 and do not exist on Exynos4x12.
Redefine them to use the exact SoC name.
Based on "ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx" by
Joonyoung Shim, see:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/100738.html
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
---
arch/arm/mach-exynos/include/mach/gpio.h | 32 +++++++++++++++---------------
arch/arm/mach-exynos/mach-nuri.c | 16 +++++++--------
arch/arm/mach-exynos/mach-origen.c | 6 +++---
arch/arm/mach-exynos/mach-trats.c | 4 ++--
arch/arm/mach-exynos/mach-universal_c210.c | 32 +++++++++++++++---------------
arch/arm/mach-exynos/setup-fimc.c | 4 ++--
drivers/gpio/gpio-samsung.c | 20 +++++++++----------
7 files changed, 57 insertions(+), 57 deletions(-)
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index eb24f1e..21c9bf1 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -26,11 +26,11 @@
#define EXYNOS4_GPIO_C1_NR (5)
#define EXYNOS4_GPIO_D0_NR (4)
#define EXYNOS4_GPIO_D1_NR (4)
-#define EXYNOS4_GPIO_E0_NR (5)
-#define EXYNOS4_GPIO_E1_NR (8)
-#define EXYNOS4_GPIO_E2_NR (6)
-#define EXYNOS4_GPIO_E3_NR (8)
-#define EXYNOS4_GPIO_E4_NR (8)
+#define EXYNOS4210_GPIO_E0_NR (5)
+#define EXYNOS4210_GPIO_E1_NR (8)
+#define EXYNOS4210_GPIO_E2_NR (6)
+#define EXYNOS4210_GPIO_E3_NR (8)
+#define EXYNOS4210_GPIO_E4_NR (8)
#define EXYNOS4_GPIO_F0_NR (8)
#define EXYNOS4_GPIO_F1_NR (8)
#define EXYNOS4_GPIO_F2_NR (8)
@@ -67,12 +67,12 @@ enum exynos4_gpio_number {
EXYNOS4_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
EXYNOS4_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
EXYNOS4_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
- EXYNOS4_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
- EXYNOS4_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0),
- EXYNOS4_GPIO_E2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1),
- EXYNOS4_GPIO_E3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2),
- EXYNOS4_GPIO_E4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3),
- EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4),
+ EXYNOS4210_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
+ EXYNOS4210_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E0),
+ EXYNOS4210_GPIO_E2_START = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E1),
+ EXYNOS4210_GPIO_E3_START = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E2),
+ EXYNOS4210_GPIO_E4_START = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E3),
+ EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E4),
EXYNOS4_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
EXYNOS4_GPIO_F2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
@@ -108,11 +108,11 @@ enum exynos4_gpio_number {
#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr))
#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr))
#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr))
-#define EXYNOS4_GPE0(_nr) (EXYNOS4_GPIO_E0_START + (_nr))
-#define EXYNOS4_GPE1(_nr) (EXYNOS4_GPIO_E1_START + (_nr))
-#define EXYNOS4_GPE2(_nr) (EXYNOS4_GPIO_E2_START + (_nr))
-#define EXYNOS4_GPE3(_nr) (EXYNOS4_GPIO_E3_START + (_nr))
-#define EXYNOS4_GPE4(_nr) (EXYNOS4_GPIO_E4_START + (_nr))
+#define EXYNOS4210_GPE0(_nr) (EXYNOS4210_GPIO_E0_START + (_nr))
+#define EXYNOS4210_GPE1(_nr) (EXYNOS4210_GPIO_E1_START + (_nr))
+#define EXYNOS4210_GPE2(_nr) (EXYNOS4210_GPIO_E2_START + (_nr))
+#define EXYNOS4210_GPE3(_nr) (EXYNOS4210_GPIO_E3_START + (_nr))
+#define EXYNOS4210_GPE4(_nr) (EXYNOS4210_GPIO_E4_START + (_nr))
#define EXYNOS4_GPF0(_nr) (EXYNOS4_GPIO_F0_START + (_nr))
#define EXYNOS4_GPF1(_nr) (EXYNOS4_GPIO_F1_START + (_nr))
#define EXYNOS4_GPF2(_nr) (EXYNOS4_GPIO_F2_START + (_nr))
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index ea785fc..426bb79 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -268,7 +268,7 @@ static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
{
- int gpio = EXYNOS4_GPE1(5);
+ int gpio = EXYNOS4210_GPE1(5);
gpio_request(gpio, "LVDS_nSHDN");
gpio_direction_output(gpio, power);
@@ -277,7 +277,7 @@ static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
static int nuri_bl_init(struct device *dev)
{
- return gpio_request_one(EXYNOS4_GPE2(3), GPIOF_OUT_INIT_LOW,
+ return gpio_request_one(EXYNOS4210_GPE2(3), GPIOF_OUT_INIT_LOW,
"LCD_LD0_EN");
}
@@ -286,14 +286,14 @@ static int nuri_bl_notify(struct device *dev, int brightness)
if (brightness < 1)
brightness = 0;
- gpio_set_value(EXYNOS4_GPE2(3), 1);
+ gpio_set_value(EXYNOS4210_GPE2(3), 1);
return brightness;
}
static void nuri_bl_exit(struct device *dev)
{
- gpio_free(EXYNOS4_GPE2(3));
+ gpio_free(EXYNOS4210_GPE2(3));
}
/* nuri pwm backlight */
@@ -1048,7 +1048,7 @@ static struct max8903_pdata nuri_max8903 = {
*/
.dok = EXYNOS4_GPX1(4), /* TA_nCONNECTED */
/* uok, usus: not connected */
- .chg = EXYNOS4_GPE2(0), /* TA_nCHG */
+ .chg = EXYNOS4210_GPE2(0), /* TA_nCHG */
/* flt: vcc_1.8V_pda */
.dcm = EXYNOS4_GPL0(1), /* CURR_ADJ */
@@ -1119,7 +1119,7 @@ static struct regulator_init_data cam_vt_cam15_reg_init_data = {
static struct fixed_voltage_config cam_vt_cam15_fixed_voltage_cfg = {
.supply_name = "VT_CAM_1.5V",
.microvolts = 1500000,
- .gpio = EXYNOS4_GPE2(2), /* VT_CAM_1.5V_EN */
+ .gpio = EXYNOS4210_GPE2(2), /* VT_CAM_1.5V_EN */
.enable_high = 1,
.init_data = &cam_vt_cam15_reg_init_data,
};
@@ -1143,7 +1143,7 @@ static struct regulator_init_data cam_vdda_reg_init_data = {
static struct fixed_voltage_config cam_vdda_fixed_voltage_cfg = {
.supply_name = "CAM_IO_EN",
.microvolts = 2800000,
- .gpio = EXYNOS4_GPE2(1), /* CAM_IO_EN */
+ .gpio = EXYNOS4210_GPE2(1), /* CAM_IO_EN */
.enable_high = 1,
.init_data = &cam_vdda_reg_init_data,
};
@@ -1167,7 +1167,7 @@ static struct regulator_init_data cam_8m_12v_reg_init_data = {
static struct fixed_voltage_config cam_8m_12v_fixed_voltage_cfg = {
.supply_name = "8M_1.2V",
.microvolts = 1200000,
- .gpio = EXYNOS4_GPE2(5), /* 8M_1.2V_EN */
+ .gpio = EXYNOS4210_GPE2(5), /* 8M_1.2V_EN */
.enable_high = 1,
.init_data = &cam_8m_12v_reg_init_data,
};
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 5ca8030..13424fc 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -591,13 +591,13 @@ static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power)
int ret;
if (power)
- ret = gpio_request_one(EXYNOS4_GPE3(4),
+ ret = gpio_request_one(EXYNOS4210_GPE3(4),
GPIOF_OUT_INIT_HIGH, "GPE3_4");
else
- ret = gpio_request_one(EXYNOS4_GPE3(4),
+ ret = gpio_request_one(EXYNOS4210_GPE3(4),
GPIOF_OUT_INIT_LOW, "GPE3_4");
- gpio_free(EXYNOS4_GPE3(4));
+ gpio_free(EXYNOS4210_GPE3(4));
if (ret)
pr_err("failed to request gpio for LCD power: %d\n", ret);
diff --git a/arch/arm/mach-exynos/mach-trats.c b/arch/arm/mach-exynos/mach-trats.c
index fdcbcbd..d2c9787 100644
--- a/arch/arm/mach-exynos/mach-trats.c
+++ b/arch/arm/mach-exynos/mach-trats.c
@@ -770,7 +770,7 @@ static struct regulator_init_data cam_vdda_reg_init_data = {
static struct fixed_voltage_config cam_vdda_fixed_voltage_cfg = {
.supply_name = "CAM_IO_EN",
.microvolts = 2800000,
- .gpio = EXYNOS4_GPE2(1), /* CAM_IO_EN */
+ .gpio = EXYNOS4210_GPE2(1), /* CAM_IO_EN */
.enable_high = 1,
.init_data = &cam_vdda_reg_init_data,
};
@@ -794,7 +794,7 @@ static struct regulator_init_data cam_8m_12v_reg_init_data = {
static struct fixed_voltage_config cam_8m_12v_fixed_voltage_cfg = {
.supply_name = "8M_1.2V_EN",
.microvolts = 1200000,
- .gpio = EXYNOS4_GPE2(5), /* 8M_1.2V_EN */
+ .gpio = EXYNOS4210_GPE2(5), /* 8M_1.2V_EN */
.enable_high = 1,
.init_data = &cam_8m_12v_reg_init_data,
};
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 8951bcc..9c60e66 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -552,7 +552,7 @@ static struct max8998_platform_data universal_lp3974_pdata = {
.buck2_voltage1 = 1200000, /* G3D */
.buck2_voltage2 = 1100000,
.buck1_default_idx = 0,
- .buck2_set3 = EXYNOS4_GPE2(0),
+ .buck2_set3 = EXYNOS4210_GPE2(0),
.buck2_default_idx = 0,
.wakeup = true,
};
@@ -581,7 +581,7 @@ static struct regulator_init_data hdmi_fixed_voltage_init_data = {
static struct fixed_voltage_config hdmi_fixed_voltage_config = {
.supply_name = "HDMI_EN1",
.microvolts = 5000000,
- .gpio = EXYNOS4_GPE0(1),
+ .gpio = EXYNOS4210_GPE0(1),
.enable_high = true,
.init_data = &hdmi_fixed_voltage_init_data,
};
@@ -630,12 +630,12 @@ static void __init universal_tsp_init(void)
int gpio;
/* TSP_LDO_ON: XMDMADDR_11 */
- gpio = EXYNOS4_GPE2(3);
+ gpio = EXYNOS4210_GPE2(3);
gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON");
gpio_export(gpio, 0);
/* TSP_INT: XMDMADDR_7 */
- gpio = EXYNOS4_GPE1(7);
+ gpio = EXYNOS4210_GPE1(7);
gpio_request(gpio, "TSP_INT");
s5p_register_gpio_interrupt(gpio);
@@ -661,8 +661,8 @@ static struct mcs_platform_data touchkey_data = {
/* GPIO I2C 3_TOUCH 2.8V */
#define I2C_GPIO_BUS_12 12
static struct i2c_gpio_platform_data i2c_gpio12_data = {
- .sda_pin = EXYNOS4_GPE4(0), /* XMDMDATA_8 */
- .scl_pin = EXYNOS4_GPE4(1), /* XMDMDATA_9 */
+ .sda_pin = EXYNOS4210_GPE4(0), /* XMDMDATA_8 */
+ .scl_pin = EXYNOS4210_GPE4(1), /* XMDMDATA_9 */
};
static struct platform_device i2c_gpio12 = {
@@ -684,13 +684,13 @@ static void __init universal_touchkey_init(void)
{
int gpio;
- gpio = EXYNOS4_GPE3(7); /* XMDMDATA_7 */
+ gpio = EXYNOS4210_GPE3(7); /* XMDMDATA_7 */
gpio_request(gpio, "3_TOUCH_INT");
s5p_register_gpio_interrupt(gpio);
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
- gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */
+ gpio = EXYNOS4210_GPE3(3); /* XMDMDATA_3 */
gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "3_TOUCH_EN");
}
@@ -776,7 +776,7 @@ static struct regulator_init_data mmc0_fixed_voltage_init_data = {
static struct fixed_voltage_config mmc0_fixed_voltage_config = {
.supply_name = "MASSMEMORY_EN",
.microvolts = 2800000,
- .gpio = EXYNOS4_GPE1(3),
+ .gpio = EXYNOS4210_GPE1(3),
.enable_high = true,
.init_data = &mmc0_fixed_voltage_init_data,
};
@@ -887,7 +887,7 @@ static struct regulator_init_data cam_vt_dio_reg_init_data = {
static struct fixed_voltage_config cam_vt_dio_fixed_voltage_cfg = {
.supply_name = "CAM_VT_D_IO",
.microvolts = 2800000,
- .gpio = EXYNOS4_GPE2(1), /* CAM_PWR_EN2 */
+ .gpio = EXYNOS4210_GPE2(1), /* CAM_PWR_EN2 */
.enable_high = 1,
.init_data = &cam_vt_dio_reg_init_data,
};
@@ -909,7 +909,7 @@ static struct regulator_init_data cam_i_core_reg_init_data = {
static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = {
.supply_name = "CAM_I_CORE_1.2V",
.microvolts = 1200000,
- .gpio = EXYNOS4_GPE2(2), /* CAM_8M_CORE_EN */
+ .gpio = EXYNOS4210_GPE2(2), /* CAM_8M_CORE_EN */
.enable_high = 1,
.init_data = &cam_i_core_reg_init_data,
};
@@ -931,7 +931,7 @@ static struct regulator_init_data cam_s_if_reg_init_data = {
static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = {
.supply_name = "CAM_S_IF_1.8V",
.microvolts = 1800000,
- .gpio = EXYNOS4_GPE3(0), /* CAM_PWR_EN1 */
+ .gpio = EXYNOS4210_GPE3(0), /* CAM_PWR_EN1 */
.enable_high = 1,
.init_data = &cam_s_if_reg_init_data,
};
@@ -949,11 +949,11 @@ static struct s5p_platform_mipi_csis mipi_csis_platdata = {
.phy_enable = s5p_csis_phy_enable,
};
-#define GPIO_CAM_LEVEL_EN(n) EXYNOS4_GPE4(n + 3)
+#define GPIO_CAM_LEVEL_EN(n) EXYNOS4210_GPE4(n + 3)
#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPX1(5) /* XEINT_13 */
-#define GPIO_CAM_MEGA_nRST EXYNOS4_GPE2(5)
-#define GPIO_CAM_VGA_NRST EXYNOS4_GPE4(7)
-#define GPIO_CAM_VGA_NSTBY EXYNOS4_GPE4(6)
+#define GPIO_CAM_MEGA_nRST EXYNOS4210_GPE2(5)
+#define GPIO_CAM_VGA_NRST EXYNOS4210_GPE4(7)
+#define GPIO_CAM_VGA_NSTBY EXYNOS4210_GPE4(6)
static int s5k6aa_set_power(int on)
{
diff --git a/arch/arm/mach-exynos/setup-fimc.c b/arch/arm/mach-exynos/setup-fimc.c
index 6a45078..d74843e 100644
--- a/arch/arm/mach-exynos/setup-fimc.c
+++ b/arch/arm/mach-exynos/setup-fimc.c
@@ -26,8 +26,8 @@ int exynos4_fimc_setup_gpio(enum s5p_camport_id id)
break;
case S5P_CAMPORT_B:
- gpio8 = EXYNOS4_GPE0(0); /* DATA[0:7] */
- gpio5 = EXYNOS4_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */
+ gpio8 = EXYNOS4210_GPE0(0); /* DATA[0:7] */
+ gpio5 = EXYNOS4210_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */
sfn = S3C_GPIO_SFN(3);
break;
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index ba126cc..c996440 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -2171,32 +2171,32 @@ static struct samsung_gpio_chip exynos4_gpios_1[] = {
},
}, {
.chip = {
- .base = EXYNOS4_GPE0(0),
- .ngpio = EXYNOS4_GPIO_E0_NR,
+ .base = EXYNOS4210_GPE0(0),
+ .ngpio = EXYNOS4210_GPIO_E0_NR,
.label = "GPE0",
},
}, {
.chip = {
- .base = EXYNOS4_GPE1(0),
- .ngpio = EXYNOS4_GPIO_E1_NR,
+ .base = EXYNOS4210_GPE1(0),
+ .ngpio = EXYNOS4210_GPIO_E1_NR,
.label = "GPE1",
},
}, {
.chip = {
- .base = EXYNOS4_GPE2(0),
- .ngpio = EXYNOS4_GPIO_E2_NR,
+ .base = EXYNOS4210_GPE2(0),
+ .ngpio = EXYNOS4210_GPIO_E2_NR,
.label = "GPE2",
},
}, {
.chip = {
- .base = EXYNOS4_GPE3(0),
- .ngpio = EXYNOS4_GPIO_E3_NR,
+ .base = EXYNOS4210_GPE3(0),
+ .ngpio = EXYNOS4210_GPIO_E3_NR,
.label = "GPE3",
},
}, {
.chip = {
- .base = EXYNOS4_GPE4(0),
- .ngpio = EXYNOS4_GPIO_E4_NR,
+ .base = EXYNOS4210_GPE4(0),
+ .ngpio = EXYNOS4210_GPIO_E4_NR,
.label = "GPE4",
},
}, {
--
1.7.12
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/3] gpio: samsung: Add support for Exynos4x12 SoCs
2012-08-28 10:01 [PATCH 0/3] ARM: EXYNOS: Add support for GPIO on Exynos4x12 Tomasz Figa
2012-08-28 10:06 ` [PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx Tomasz Figa
@ 2012-08-28 10:06 ` Tomasz Figa
2012-08-28 14:55 ` Thomas Abraham
2012-08-28 10:07 ` [PATCH 3/3] ARM: EXYNOS: Add support for FIMC cam port B GPIO setup on Exynos4x12 Tomasz Figa
2012-08-28 14:58 ` [PATCH 0/3] ARM: EXYNOS: Add support for GPIO " Thomas Abraham
3 siblings, 1 reply; 12+ messages in thread
From: Tomasz Figa @ 2012-08-28 10:06 UTC (permalink / raw)
To: linux-arm-kernel
Based on patch "gpio/exynos: Add support for Exynos4x12 SoC" by Joonyoung Shim.
See: http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/100737.html
Exynos4x12 GPIO part1 and part2 have different layout than Exynos4210,
so the initialization code has to be modified to support Exynos4x12 SoC.
GPVx Exynos4x12 GPIO part4 is not supported yet.
In the Exynos4x12 GPIO part1 and part2, the interval of base register
offset is 0x20 but GPF0, GPJ0, GPK0 and GPM0 have different offsets. Same goes
for the interrupt reg offset of GPF0 and GPK0. Refer to the layout below.
- Exynos4x12 GPIO Part1
GPIO Base offset Interrupt reg offset
GPA0 0x000 0x00
GPA1 0x020 0x04
GPB 0x040 0x08
GPC0 0x060 0x0C
GPC1 0x080 0x10
GPD0 0x0A0 0x14
GPD1 0x0C0 0x18
...
GPF0 0x180 0x30
GPF1 0x1A0 0x34
GPF2 0x1C0 0x38
GPF3 0x1E0 0x3C
...
GPJ0 0x240 0x40
GPJ1 0x260 0x44
- Exynos4x12 GPIO Part2
...
GPK0 0x040 0x08
GPK1 0x060 0x0C
GPK2 0x080 0x10
GPK3 0x0A0 0x14
GPL0 0x0C0 0x18
GPL1 0x0E0 0x1C
GPL2 0x100 0x20
GPY0 0x120 x
GPY1 0x140 x
GPY2 0x160 x
GPY3 0x180 x
GPY4 0x1A0 x
GPY5 0x1C0 x
GPY6 0x1E0 x
...
GPM0 0x260 0x24
GPM1 0x280 0x28
GPM2 0x2A0 0x2C
GPM3 0x2C0 0x30
GPM4 0x2E0 0x34
GPX0 0xC00 x
GPX1 0xC20 x
GPX2 0xC40 x
GPX3 0xC60 x
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
---
arch/arm/mach-exynos/include/mach/gpio.h | 28 ++-
arch/arm/mach-exynos/include/mach/irqs.h | 6 -
drivers/gpio/gpio-samsung.c | 330 ++++++++++++++++++++++++++++---
3 files changed, 326 insertions(+), 38 deletions(-)
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index 21c9bf1..2103d14 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -26,11 +26,13 @@
#define EXYNOS4_GPIO_C1_NR (5)
#define EXYNOS4_GPIO_D0_NR (4)
#define EXYNOS4_GPIO_D1_NR (4)
+
#define EXYNOS4210_GPIO_E0_NR (5)
#define EXYNOS4210_GPIO_E1_NR (8)
#define EXYNOS4210_GPIO_E2_NR (6)
#define EXYNOS4210_GPIO_E3_NR (8)
#define EXYNOS4210_GPIO_E4_NR (8)
+
#define EXYNOS4_GPIO_F0_NR (8)
#define EXYNOS4_GPIO_F1_NR (8)
#define EXYNOS4_GPIO_F2_NR (8)
@@ -44,6 +46,13 @@
#define EXYNOS4_GPIO_L0_NR (8)
#define EXYNOS4_GPIO_L1_NR (3)
#define EXYNOS4_GPIO_L2_NR (8)
+
+#define EXYNOS4X12_GPIO_M0_NR (8)
+#define EXYNOS4X12_GPIO_M1_NR (7)
+#define EXYNOS4X12_GPIO_M2_NR (5)
+#define EXYNOS4X12_GPIO_M3_NR (8)
+#define EXYNOS4X12_GPIO_M4_NR (8)
+
#define EXYNOS4_GPIO_X0_NR (8)
#define EXYNOS4_GPIO_X1_NR (8)
#define EXYNOS4_GPIO_X2_NR (8)
@@ -67,12 +76,20 @@ enum exynos4_gpio_number {
EXYNOS4_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
EXYNOS4_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
EXYNOS4_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
+
EXYNOS4210_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
EXYNOS4210_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E0),
EXYNOS4210_GPIO_E2_START = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E1),
EXYNOS4210_GPIO_E3_START = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E2),
EXYNOS4210_GPIO_E4_START = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E3),
- EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E4),
+
+ EXYNOS4X12_GPIO_M0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
+ EXYNOS4X12_GPIO_M1_START = EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M0),
+ EXYNOS4X12_GPIO_M2_START = EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M1),
+ EXYNOS4X12_GPIO_M3_START = EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M2),
+ EXYNOS4X12_GPIO_M4_START = EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M3),
+
+ EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M4),
EXYNOS4_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
EXYNOS4_GPIO_F2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
@@ -108,11 +125,13 @@ enum exynos4_gpio_number {
#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr))
#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr))
#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr))
+
#define EXYNOS4210_GPE0(_nr) (EXYNOS4210_GPIO_E0_START + (_nr))
#define EXYNOS4210_GPE1(_nr) (EXYNOS4210_GPIO_E1_START + (_nr))
#define EXYNOS4210_GPE2(_nr) (EXYNOS4210_GPIO_E2_START + (_nr))
#define EXYNOS4210_GPE3(_nr) (EXYNOS4210_GPIO_E3_START + (_nr))
#define EXYNOS4210_GPE4(_nr) (EXYNOS4210_GPIO_E4_START + (_nr))
+
#define EXYNOS4_GPF0(_nr) (EXYNOS4_GPIO_F0_START + (_nr))
#define EXYNOS4_GPF1(_nr) (EXYNOS4_GPIO_F1_START + (_nr))
#define EXYNOS4_GPF2(_nr) (EXYNOS4_GPIO_F2_START + (_nr))
@@ -126,6 +145,13 @@ enum exynos4_gpio_number {
#define EXYNOS4_GPL0(_nr) (EXYNOS4_GPIO_L0_START + (_nr))
#define EXYNOS4_GPL1(_nr) (EXYNOS4_GPIO_L1_START + (_nr))
#define EXYNOS4_GPL2(_nr) (EXYNOS4_GPIO_L2_START + (_nr))
+
+#define EXYNOS4X12_GPM0(_nr) (EXYNOS4X12_GPIO_M0_START + (_nr))
+#define EXYNOS4X12_GPM1(_nr) (EXYNOS4X12_GPIO_M1_START + (_nr))
+#define EXYNOS4X12_GPM2(_nr) (EXYNOS4X12_GPIO_M2_START + (_nr))
+#define EXYNOS4X12_GPM3(_nr) (EXYNOS4X12_GPIO_M3_START + (_nr))
+#define EXYNOS4X12_GPM4(_nr) (EXYNOS4X12_GPIO_M4_START + (_nr))
+
#define EXYNOS4_GPX0(_nr) (EXYNOS4_GPIO_X0_START + (_nr))
#define EXYNOS4_GPX1(_nr) (EXYNOS4_GPIO_X1_START + (_nr))
#define EXYNOS4_GPX2(_nr) (EXYNOS4_GPIO_X2_START + (_nr))
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 315aa14..c2ad2be 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -168,9 +168,6 @@
#define EXYNOS4_MAX_COMBINER_NR 16
-#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16
-#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9
-
/*
* For Compatibility:
* the default is for EXYNOS4, and
@@ -238,9 +235,6 @@
#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM
-#define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS
-#define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS
-
/* For EXYNOS5 SoCs */
#define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33)
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index c996440..b5048f5 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -2126,7 +2126,7 @@ static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
*/
#ifdef CONFIG_ARCH_EXYNOS4
-static struct samsung_gpio_chip exynos4_gpios_1[] = {
+static struct samsung_gpio_chip exynos4210_gpios_1[] = {
{
.chip = {
.base = EXYNOS4_GPA0(0),
@@ -2225,10 +2225,93 @@ static struct samsung_gpio_chip exynos4_gpios_1[] = {
},
},
};
-#endif
-#ifdef CONFIG_ARCH_EXYNOS4
-static struct samsung_gpio_chip exynos4_gpios_2[] = {
+static struct samsung_gpio_chip exynos4x12_gpios_1[] = {
+ {
+ .chip = {
+ .base = EXYNOS4_GPA0(0),
+ .ngpio = EXYNOS4_GPIO_A0_NR,
+ .label = "GPA0",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4_GPA1(0),
+ .ngpio = EXYNOS4_GPIO_A1_NR,
+ .label = "GPA1",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4_GPB(0),
+ .ngpio = EXYNOS4_GPIO_B_NR,
+ .label = "GPB",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4_GPC0(0),
+ .ngpio = EXYNOS4_GPIO_C0_NR,
+ .label = "GPC0",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4_GPC1(0),
+ .ngpio = EXYNOS4_GPIO_C1_NR,
+ .label = "GPC1",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4_GPD0(0),
+ .ngpio = EXYNOS4_GPIO_D0_NR,
+ .label = "GPD0",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4_GPD1(0),
+ .ngpio = EXYNOS4_GPIO_D1_NR,
+ .label = "GPD1",
+ },
+ }, {
+ .base = (void *)0x180,
+ .group = 12,
+ .chip = {
+ .base = EXYNOS4_GPF0(0),
+ .ngpio = EXYNOS4_GPIO_F0_NR,
+ .label = "GPF0",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4_GPF1(0),
+ .ngpio = EXYNOS4_GPIO_F1_NR,
+ .label = "GPF1",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4_GPF2(0),
+ .ngpio = EXYNOS4_GPIO_F2_NR,
+ .label = "GPF2",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4_GPF3(0),
+ .ngpio = EXYNOS4_GPIO_F3_NR,
+ .label = "GPF3",
+ },
+ }, {
+ .base = (void *)0x240,
+ .chip = {
+ .base = EXYNOS4_GPJ0(0),
+ .ngpio = EXYNOS4_GPIO_J0_NR,
+ .label = "GPJ0",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4_GPJ1(0),
+ .ngpio = EXYNOS4_GPIO_J1_NR,
+ .label = "GPJ1",
+ },
+ },
+};
+
+static struct samsung_gpio_chip exynos4210_gpios_2[] = {
{
.chip = {
.base = EXYNOS4_GPJ0(0),
@@ -2333,6 +2416,172 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
.label = "GPY6",
},
}, {
+ .base = (void *)0xC00,
+ .config = &samsung_gpio_cfgs[9],
+ .irq_base = IRQ_EINT(0),
+ .chip = {
+ .base = EXYNOS4_GPX0(0),
+ .ngpio = EXYNOS4_GPIO_X0_NR,
+ .label = "GPX0",
+ .to_irq = samsung_gpiolib_to_irq,
+ },
+ }, {
+ .config = &samsung_gpio_cfgs[9],
+ .irq_base = IRQ_EINT(8),
+ .chip = {
+ .base = EXYNOS4_GPX1(0),
+ .ngpio = EXYNOS4_GPIO_X1_NR,
+ .label = "GPX1",
+ .to_irq = samsung_gpiolib_to_irq,
+ },
+ }, {
+ .config = &samsung_gpio_cfgs[9],
+ .irq_base = IRQ_EINT(16),
+ .chip = {
+ .base = EXYNOS4_GPX2(0),
+ .ngpio = EXYNOS4_GPIO_X2_NR,
+ .label = "GPX2",
+ .to_irq = samsung_gpiolib_to_irq,
+ },
+ }, {
+ .config = &samsung_gpio_cfgs[9],
+ .irq_base = IRQ_EINT(24),
+ .chip = {
+ .base = EXYNOS4_GPX3(0),
+ .ngpio = EXYNOS4_GPIO_X3_NR,
+ .label = "GPX3",
+ .to_irq = samsung_gpiolib_to_irq,
+ },
+ },
+};
+
+static struct samsung_gpio_chip exynos4x12_gpios_2[] = {
+ {
+ .base = (void *)0x040,
+ .group = 20,
+ .chip = {
+ .base = EXYNOS4_GPK0(0),
+ .ngpio = EXYNOS4_GPIO_K0_NR,
+ .label = "GPK0",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4_GPK1(0),
+ .ngpio = EXYNOS4_GPIO_K1_NR,
+ .label = "GPK1",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4_GPK2(0),
+ .ngpio = EXYNOS4_GPIO_K2_NR,
+ .label = "GPK2",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4_GPK3(0),
+ .ngpio = EXYNOS4_GPIO_K3_NR,
+ .label = "GPK3",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4_GPL0(0),
+ .ngpio = EXYNOS4_GPIO_L0_NR,
+ .label = "GPL0",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4_GPL1(0),
+ .ngpio = EXYNOS4_GPIO_L1_NR,
+ .label = "GPL1",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4_GPL2(0),
+ .ngpio = EXYNOS4_GPIO_L2_NR,
+ .label = "GPL2",
+ },
+ }, {
+ .config = &samsung_gpio_cfgs[8],
+ .chip = {
+ .base = EXYNOS4_GPY0(0),
+ .ngpio = EXYNOS4_GPIO_Y0_NR,
+ .label = "GPY0",
+ },
+ }, {
+ .config = &samsung_gpio_cfgs[8],
+ .chip = {
+ .base = EXYNOS4_GPY1(0),
+ .ngpio = EXYNOS4_GPIO_Y1_NR,
+ .label = "GPY1",
+ },
+ }, {
+ .config = &samsung_gpio_cfgs[8],
+ .chip = {
+ .base = EXYNOS4_GPY2(0),
+ .ngpio = EXYNOS4_GPIO_Y2_NR,
+ .label = "GPY2",
+ },
+ }, {
+ .config = &samsung_gpio_cfgs[8],
+ .chip = {
+ .base = EXYNOS4_GPY3(0),
+ .ngpio = EXYNOS4_GPIO_Y3_NR,
+ .label = "GPY3",
+ },
+ }, {
+ .config = &samsung_gpio_cfgs[8],
+ .chip = {
+ .base = EXYNOS4_GPY4(0),
+ .ngpio = EXYNOS4_GPIO_Y4_NR,
+ .label = "GPY4",
+ },
+ }, {
+ .config = &samsung_gpio_cfgs[8],
+ .chip = {
+ .base = EXYNOS4_GPY5(0),
+ .ngpio = EXYNOS4_GPIO_Y5_NR,
+ .label = "GPY5",
+ },
+ }, {
+ .config = &samsung_gpio_cfgs[8],
+ .chip = {
+ .base = EXYNOS4_GPY6(0),
+ .ngpio = EXYNOS4_GPIO_Y6_NR,
+ .label = "GPY6",
+ },
+ }, {
+ .base = (void *)0x260,
+ .chip = {
+ .base = EXYNOS4X12_GPM0(0),
+ .ngpio = EXYNOS4X12_GPIO_M0_NR,
+ .label = "GPM0",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4X12_GPM1(0),
+ .ngpio = EXYNOS4X12_GPIO_M1_NR,
+ .label = "GPM1",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4X12_GPM2(0),
+ .ngpio = EXYNOS4X12_GPIO_M2_NR,
+ .label = "GPM2",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4X12_GPM3(0),
+ .ngpio = EXYNOS4X12_GPIO_M3_NR,
+ .label = "GPM3",
+ },
+ }, {
+ .chip = {
+ .base = EXYNOS4X12_GPM4(0),
+ .ngpio = EXYNOS4X12_GPIO_M4_NR,
+ .label = "GPM4",
+ },
+ }, {
+ .base = (void *)0xC00,
.config = &samsung_gpio_cfgs[9],
.irq_base = IRQ_EINT(0),
.chip = {
@@ -2370,9 +2619,7 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
},
},
};
-#endif
-#ifdef CONFIG_ARCH_EXYNOS4
static struct samsung_gpio_chip exynos4_gpios_3[] = {
{
.chip = {
@@ -2727,12 +2974,15 @@ static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
static __init void exynos4_gpiolib_init(void)
{
-#ifdef CONFIG_CPU_EXYNOS4210
+#ifdef CONFIG_ARCH_EXYNOS4
struct samsung_gpio_chip *chip;
int i, nr_chips;
void __iomem *gpio_base1, *gpio_base2, *gpio_base3;
int group = 0;
void __iomem *gpx_base;
+ struct samsung_gpio_chip *chip_p;
+ int offset = 0;
+ int group1 = 0;
/* gpio part1 */
gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
@@ -2741,19 +2991,31 @@ static __init void exynos4_gpiolib_init(void)
goto err_ioremap1;
}
- chip = exynos4_gpios_1;
- nr_chips = ARRAY_SIZE(exynos4_gpios_1);
+ if (soc_is_exynos4210()) {
+ chip = chip_p = exynos4210_gpios_1;
+ nr_chips = ARRAY_SIZE(exynos4210_gpios_1);
+ } else {
+ chip = chip_p = exynos4x12_gpios_1;
+ nr_chips = ARRAY_SIZE(exynos4x12_gpios_1);
+ }
for (i = 0; i < nr_chips; i++, chip++) {
if (!chip->config) {
chip->config = &exynos_gpio_cfg;
+ if (chip->group)
+ group = chip->group;
chip->group = group++;
}
- exynos_gpiolib_attach_ofnode(chip,
- EXYNOS4_PA_GPIO1, i * 0x20);
+
+ if (chip->base)
+ offset = (u32)chip->base;
+ chip->base = gpio_base1 + offset;
+ offset += 0x20;
+
+ exynos_gpiolib_attach_ofnode(chip, EXYNOS4_PA_GPIO1, 0);
}
- samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
- nr_chips, gpio_base1);
+ samsung_gpiolib_add_4bit_chips(chip_p, nr_chips, gpio_base1);
+ group1 = group;
/* gpio part2 */
gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
@@ -2762,25 +3024,32 @@ static __init void exynos4_gpiolib_init(void)
goto err_ioremap2;
}
- /* need to set base address for gpx */
- chip = &exynos4_gpios_2[16];
- gpx_base = gpio_base2 + 0xC00;
- for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
- chip->base = gpx_base;
+ if (soc_is_exynos4210()) {
+ chip = chip_p = exynos4210_gpios_2;
+ nr_chips = ARRAY_SIZE(exynos4210_gpios_2);
+ } else {
+ chip = chip_p = exynos4x12_gpios_2;
+ nr_chips = ARRAY_SIZE(exynos4x12_gpios_2);
+ }
- chip = exynos4_gpios_2;
- nr_chips = ARRAY_SIZE(exynos4_gpios_2);
+ offset = 0;
for (i = 0; i < nr_chips; i++, chip++) {
if (!chip->config) {
chip->config = &exynos_gpio_cfg;
+ if (chip->group)
+ group = chip->group;
chip->group = group++;
}
- exynos_gpiolib_attach_ofnode(chip,
- EXYNOS4_PA_GPIO2, i * 0x20);
+
+ if (chip->base)
+ offset = (u32)chip->base;
+ chip->base = gpio_base2 + offset;
+ offset += 0x20;
+
+ exynos_gpiolib_attach_ofnode(chip, EXYNOS4_PA_GPIO2, 0);
}
- samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
- nr_chips, gpio_base2);
+ samsung_gpiolib_add_4bit_chips(chip_p, nr_chips, gpio_base2);
/* gpio part3 */
gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
@@ -2801,12 +3070,10 @@ static __init void exynos4_gpiolib_init(void)
EXYNOS4_PA_GPIO3, i * 0x20);
}
samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
- nr_chips, gpio_base3);
+ nr_chips, gpio_base3);
-#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
- s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
- s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
-#endif
+ s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, group1);
+ s5p_register_gpioint_bank(IRQ_GPIO_XB, group1, group - group1);
return;
@@ -2816,7 +3083,7 @@ err_ioremap2:
iounmap(gpio_base1);
err_ioremap1:
return;
-#endif /* CONFIG_CPU_EXYNOS4210 */
+#endif /* CONFIG_ARCH_EXYNOS4 */
}
static __init void exynos5_gpiolib_init(void)
@@ -3010,7 +3277,8 @@ static __init int samsung_gpiolib_init(void)
#if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
#endif
- } else if (soc_is_exynos4210()) {
+ } else if (soc_is_exynos4210() || soc_is_exynos4212() ||
+ soc_is_exynos4412()) {
exynos4_gpiolib_init();
} else if (soc_is_exynos5250()) {
exynos5_gpiolib_init();
--
1.7.12
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/3] ARM: EXYNOS: Add support for FIMC cam port B GPIO setup on Exynos4x12
2012-08-28 10:01 [PATCH 0/3] ARM: EXYNOS: Add support for GPIO on Exynos4x12 Tomasz Figa
2012-08-28 10:06 ` [PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx Tomasz Figa
2012-08-28 10:06 ` [PATCH 2/3] gpio: samsung: Add support for Exynos4x12 SoCs Tomasz Figa
@ 2012-08-28 10:07 ` Tomasz Figa
2012-08-28 14:58 ` [PATCH 0/3] ARM: EXYNOS: Add support for GPIO " Thomas Abraham
3 siblings, 0 replies; 12+ messages in thread
From: Tomasz Figa @ 2012-08-28 10:07 UTC (permalink / raw)
To: linux-arm-kernel
Exynos4x12 SoCs use different GPIO pins for FIMC cam port B and this patch
modifies the setup code to take it into account.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
---
arch/arm/mach-exynos/setup-fimc.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/mach-exynos/setup-fimc.c b/arch/arm/mach-exynos/setup-fimc.c
index d74843e..4b0cce5 100644
--- a/arch/arm/mach-exynos/setup-fimc.c
+++ b/arch/arm/mach-exynos/setup-fimc.c
@@ -11,6 +11,7 @@
#include <linux/gpio.h>
#include <plat/gpio-cfg.h>
#include <plat/camport.h>
+#include <plat/cpu.h>
int exynos4_fimc_setup_gpio(enum s5p_camport_id id)
{
@@ -26,6 +27,22 @@ int exynos4_fimc_setup_gpio(enum s5p_camport_id id)
break;
case S5P_CAMPORT_B:
+ if (soc_is_exynos4212() || soc_is_exynos4412()) {
+ sfn = S3C_GPIO_SFN(3);
+
+ /* PCLK, DATA[0-6] */
+ ret = s3c_gpio_cfgrange_nopull(EXYNOS4X12_GPM0(0), 8, sfn);
+ /* FIELD, DATA[7]*/
+ if (!ret)
+ ret = s3c_gpio_cfgrange_nopull(EXYNOS4X12_GPM1(0),
+ 2, sfn);
+ /* VSYNC, HREF, CLKOUT*/
+ if (!ret)
+ ret = s3c_gpio_cfgrange_nopull(EXYNOS4X12_GPM2(0),
+ 3, sfn);
+ return ret;
+ }
+
gpio8 = EXYNOS4210_GPE0(0); /* DATA[0:7] */
gpio5 = EXYNOS4210_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */
sfn = S3C_GPIO_SFN(3);
--
1.7.12
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
2012-08-28 10:06 ` [PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx Tomasz Figa
@ 2012-08-28 14:48 ` Thomas Abraham
2012-08-28 23:44 ` Kukjin Kim
1 sibling, 0 replies; 12+ messages in thread
From: Thomas Abraham @ 2012-08-28 14:48 UTC (permalink / raw)
To: linux-arm-kernel
On 28 August 2012 15:36, Tomasz Figa <t.figa@samsung.com> wrote:
> The GPEx gpios are specific to Exynos4210 and do not exist on Exynos4x12.
> Redefine them to use the exact SoC name.
>
> Based on "ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx" by
> Joonyoung Shim, see:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/100738.html
>
> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> ---
> arch/arm/mach-exynos/include/mach/gpio.h | 32 +++++++++++++++---------------
> arch/arm/mach-exynos/mach-nuri.c | 16 +++++++--------
> arch/arm/mach-exynos/mach-origen.c | 6 +++---
> arch/arm/mach-exynos/mach-trats.c | 4 ++--
> arch/arm/mach-exynos/mach-universal_c210.c | 32 +++++++++++++++---------------
> arch/arm/mach-exynos/setup-fimc.c | 4 ++--
> drivers/gpio/gpio-samsung.c | 20 +++++++++----------
> 7 files changed, 57 insertions(+), 57 deletions(-)
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
[...]
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/3] gpio: samsung: Add support for Exynos4x12 SoCs
2012-08-28 10:06 ` [PATCH 2/3] gpio: samsung: Add support for Exynos4x12 SoCs Tomasz Figa
@ 2012-08-28 14:55 ` Thomas Abraham
2012-08-28 17:27 ` Tomasz Figa
0 siblings, 1 reply; 12+ messages in thread
From: Thomas Abraham @ 2012-08-28 14:55 UTC (permalink / raw)
To: linux-arm-kernel
On 28 August 2012 15:36, Tomasz Figa <t.figa@samsung.com> wrote:
> Based on patch "gpio/exynos: Add support for Exynos4x12 SoC" by Joonyoung Shim.
> See: http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/100737.html
>
> Exynos4x12 GPIO part1 and part2 have different layout than Exynos4210,
> so the initialization code has to be modified to support Exynos4x12 SoC.
> GPVx Exynos4x12 GPIO part4 is not supported yet.
>
> In the Exynos4x12 GPIO part1 and part2, the interval of base register
> offset is 0x20 but GPF0, GPJ0, GPK0 and GPM0 have different offsets. Same goes
> for the interrupt reg offset of GPF0 and GPK0. Refer to the layout below.
>
> - Exynos4x12 GPIO Part1
> GPIO Base offset Interrupt reg offset
> GPA0 0x000 0x00
> GPA1 0x020 0x04
> GPB 0x040 0x08
> GPC0 0x060 0x0C
> GPC1 0x080 0x10
> GPD0 0x0A0 0x14
> GPD1 0x0C0 0x18
> ...
> GPF0 0x180 0x30
> GPF1 0x1A0 0x34
> GPF2 0x1C0 0x38
> GPF3 0x1E0 0x3C
> ...
> GPJ0 0x240 0x40
> GPJ1 0x260 0x44
>
> - Exynos4x12 GPIO Part2
> ...
> GPK0 0x040 0x08
> GPK1 0x060 0x0C
> GPK2 0x080 0x10
> GPK3 0x0A0 0x14
> GPL0 0x0C0 0x18
> GPL1 0x0E0 0x1C
> GPL2 0x100 0x20
> GPY0 0x120 x
> GPY1 0x140 x
> GPY2 0x160 x
> GPY3 0x180 x
> GPY4 0x1A0 x
> GPY5 0x1C0 x
> GPY6 0x1E0 x
> ...
> GPM0 0x260 0x24
> GPM1 0x280 0x28
> GPM2 0x2A0 0x2C
> GPM3 0x2C0 0x30
> GPM4 0x2E0 0x34
> GPX0 0xC00 x
> GPX1 0xC20 x
> GPX2 0xC40 x
> GPX3 0xC60 x
>
> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> ---
> arch/arm/mach-exynos/include/mach/gpio.h | 28 ++-
> arch/arm/mach-exynos/include/mach/irqs.h | 6 -
> drivers/gpio/gpio-samsung.c | 330 ++++++++++++++++++++++++++++---
> 3 files changed, 326 insertions(+), 38 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
> index 21c9bf1..2103d14 100644
> --- a/arch/arm/mach-exynos/include/mach/gpio.h
> +++ b/arch/arm/mach-exynos/include/mach/gpio.h
> @@ -26,11 +26,13 @@
> #define EXYNOS4_GPIO_C1_NR (5)
> #define EXYNOS4_GPIO_D0_NR (4)
> #define EXYNOS4_GPIO_D1_NR (4)
> +
> #define EXYNOS4210_GPIO_E0_NR (5)
> #define EXYNOS4210_GPIO_E1_NR (8)
> #define EXYNOS4210_GPIO_E2_NR (6)
> #define EXYNOS4210_GPIO_E3_NR (8)
> #define EXYNOS4210_GPIO_E4_NR (8)
> +
> #define EXYNOS4_GPIO_F0_NR (8)
> #define EXYNOS4_GPIO_F1_NR (8)
> #define EXYNOS4_GPIO_F2_NR (8)
> @@ -44,6 +46,13 @@
> #define EXYNOS4_GPIO_L0_NR (8)
> #define EXYNOS4_GPIO_L1_NR (3)
> #define EXYNOS4_GPIO_L2_NR (8)
> +
> +#define EXYNOS4X12_GPIO_M0_NR (8)
> +#define EXYNOS4X12_GPIO_M1_NR (7)
> +#define EXYNOS4X12_GPIO_M2_NR (5)
> +#define EXYNOS4X12_GPIO_M3_NR (8)
> +#define EXYNOS4X12_GPIO_M4_NR (8)
> +
> #define EXYNOS4_GPIO_X0_NR (8)
> #define EXYNOS4_GPIO_X1_NR (8)
> #define EXYNOS4_GPIO_X2_NR (8)
> @@ -67,12 +76,20 @@ enum exynos4_gpio_number {
> EXYNOS4_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
> EXYNOS4_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
> EXYNOS4_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
> +
> EXYNOS4210_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
> EXYNOS4210_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E0),
> EXYNOS4210_GPIO_E2_START = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E1),
> EXYNOS4210_GPIO_E3_START = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E2),
> EXYNOS4210_GPIO_E4_START = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E3),
> - EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E4),
> +
> + EXYNOS4X12_GPIO_M0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
> + EXYNOS4X12_GPIO_M1_START = EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M0),
> + EXYNOS4X12_GPIO_M2_START = EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M1),
> + EXYNOS4X12_GPIO_M3_START = EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M2),
> + EXYNOS4X12_GPIO_M4_START = EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M3),
> +
> + EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M4),
> EXYNOS4_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
> EXYNOS4_GPIO_F2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
> EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
> @@ -108,11 +125,13 @@ enum exynos4_gpio_number {
> #define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr))
> #define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr))
> #define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr))
> +
> #define EXYNOS4210_GPE0(_nr) (EXYNOS4210_GPIO_E0_START + (_nr))
> #define EXYNOS4210_GPE1(_nr) (EXYNOS4210_GPIO_E1_START + (_nr))
> #define EXYNOS4210_GPE2(_nr) (EXYNOS4210_GPIO_E2_START + (_nr))
> #define EXYNOS4210_GPE3(_nr) (EXYNOS4210_GPIO_E3_START + (_nr))
> #define EXYNOS4210_GPE4(_nr) (EXYNOS4210_GPIO_E4_START + (_nr))
> +
> #define EXYNOS4_GPF0(_nr) (EXYNOS4_GPIO_F0_START + (_nr))
> #define EXYNOS4_GPF1(_nr) (EXYNOS4_GPIO_F1_START + (_nr))
> #define EXYNOS4_GPF2(_nr) (EXYNOS4_GPIO_F2_START + (_nr))
> @@ -126,6 +145,13 @@ enum exynos4_gpio_number {
> #define EXYNOS4_GPL0(_nr) (EXYNOS4_GPIO_L0_START + (_nr))
> #define EXYNOS4_GPL1(_nr) (EXYNOS4_GPIO_L1_START + (_nr))
> #define EXYNOS4_GPL2(_nr) (EXYNOS4_GPIO_L2_START + (_nr))
> +
> +#define EXYNOS4X12_GPM0(_nr) (EXYNOS4X12_GPIO_M0_START + (_nr))
> +#define EXYNOS4X12_GPM1(_nr) (EXYNOS4X12_GPIO_M1_START + (_nr))
> +#define EXYNOS4X12_GPM2(_nr) (EXYNOS4X12_GPIO_M2_START + (_nr))
> +#define EXYNOS4X12_GPM3(_nr) (EXYNOS4X12_GPIO_M3_START + (_nr))
> +#define EXYNOS4X12_GPM4(_nr) (EXYNOS4X12_GPIO_M4_START + (_nr))
> +
> #define EXYNOS4_GPX0(_nr) (EXYNOS4_GPIO_X0_START + (_nr))
> #define EXYNOS4_GPX1(_nr) (EXYNOS4_GPIO_X1_START + (_nr))
> #define EXYNOS4_GPX2(_nr) (EXYNOS4_GPIO_X2_START + (_nr))
> diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
> index 315aa14..c2ad2be 100644
> --- a/arch/arm/mach-exynos/include/mach/irqs.h
> +++ b/arch/arm/mach-exynos/include/mach/irqs.h
> @@ -168,9 +168,6 @@
>
> #define EXYNOS4_MAX_COMBINER_NR 16
>
> -#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16
> -#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9
> -
> /*
> * For Compatibility:
> * the default is for EXYNOS4, and
> @@ -238,9 +235,6 @@
> #define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
> #define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM
>
> -#define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS
> -#define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS
> -
> /* For EXYNOS5 SoCs */
>
> #define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33)
> diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
> index c996440..b5048f5 100644
> --- a/drivers/gpio/gpio-samsung.c
> +++ b/drivers/gpio/gpio-samsung.c
> @@ -2126,7 +2126,7 @@ static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
> */
>
> #ifdef CONFIG_ARCH_EXYNOS4
> -static struct samsung_gpio_chip exynos4_gpios_1[] = {
> +static struct samsung_gpio_chip exynos4210_gpios_1[] = {
> {
> .chip = {
> .base = EXYNOS4_GPA0(0),
> @@ -2225,10 +2225,93 @@ static struct samsung_gpio_chip exynos4_gpios_1[] = {
> },
> },
> };
> -#endif
>
> -#ifdef CONFIG_ARCH_EXYNOS4
> -static struct samsung_gpio_chip exynos4_gpios_2[] = {
> +static struct samsung_gpio_chip exynos4x12_gpios_1[] = {
> + {
> + .chip = {
> + .base = EXYNOS4_GPA0(0),
> + .ngpio = EXYNOS4_GPIO_A0_NR,
> + .label = "GPA0",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4_GPA1(0),
> + .ngpio = EXYNOS4_GPIO_A1_NR,
> + .label = "GPA1",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4_GPB(0),
> + .ngpio = EXYNOS4_GPIO_B_NR,
> + .label = "GPB",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4_GPC0(0),
> + .ngpio = EXYNOS4_GPIO_C0_NR,
> + .label = "GPC0",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4_GPC1(0),
> + .ngpio = EXYNOS4_GPIO_C1_NR,
> + .label = "GPC1",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4_GPD0(0),
> + .ngpio = EXYNOS4_GPIO_D0_NR,
> + .label = "GPD0",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4_GPD1(0),
> + .ngpio = EXYNOS4_GPIO_D1_NR,
> + .label = "GPD1",
> + },
> + }, {
> + .base = (void *)0x180,
> + .group = 12,
> + .chip = {
> + .base = EXYNOS4_GPF0(0),
> + .ngpio = EXYNOS4_GPIO_F0_NR,
> + .label = "GPF0",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4_GPF1(0),
> + .ngpio = EXYNOS4_GPIO_F1_NR,
> + .label = "GPF1",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4_GPF2(0),
> + .ngpio = EXYNOS4_GPIO_F2_NR,
> + .label = "GPF2",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4_GPF3(0),
> + .ngpio = EXYNOS4_GPIO_F3_NR,
> + .label = "GPF3",
> + },
> + }, {
> + .base = (void *)0x240,
> + .chip = {
> + .base = EXYNOS4_GPJ0(0),
> + .ngpio = EXYNOS4_GPIO_J0_NR,
> + .label = "GPJ0",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4_GPJ1(0),
> + .ngpio = EXYNOS4_GPIO_J1_NR,
> + .label = "GPJ1",
> + },
> + },
> +};
> +
> +static struct samsung_gpio_chip exynos4210_gpios_2[] = {
> {
> .chip = {
> .base = EXYNOS4_GPJ0(0),
> @@ -2333,6 +2416,172 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
> .label = "GPY6",
> },
> }, {
> + .base = (void *)0xC00,
> + .config = &samsung_gpio_cfgs[9],
> + .irq_base = IRQ_EINT(0),
> + .chip = {
> + .base = EXYNOS4_GPX0(0),
> + .ngpio = EXYNOS4_GPIO_X0_NR,
> + .label = "GPX0",
> + .to_irq = samsung_gpiolib_to_irq,
> + },
> + }, {
> + .config = &samsung_gpio_cfgs[9],
> + .irq_base = IRQ_EINT(8),
> + .chip = {
> + .base = EXYNOS4_GPX1(0),
> + .ngpio = EXYNOS4_GPIO_X1_NR,
> + .label = "GPX1",
> + .to_irq = samsung_gpiolib_to_irq,
> + },
> + }, {
> + .config = &samsung_gpio_cfgs[9],
> + .irq_base = IRQ_EINT(16),
> + .chip = {
> + .base = EXYNOS4_GPX2(0),
> + .ngpio = EXYNOS4_GPIO_X2_NR,
> + .label = "GPX2",
> + .to_irq = samsung_gpiolib_to_irq,
> + },
> + }, {
> + .config = &samsung_gpio_cfgs[9],
> + .irq_base = IRQ_EINT(24),
> + .chip = {
> + .base = EXYNOS4_GPX3(0),
> + .ngpio = EXYNOS4_GPIO_X3_NR,
> + .label = "GPX3",
> + .to_irq = samsung_gpiolib_to_irq,
> + },
> + },
> +};
I see that GPX0, GPX1, GPX2 and GPX3 bank instances are already part
of mainline kernel. How is that this is being added here.
> +
> +static struct samsung_gpio_chip exynos4x12_gpios_2[] = {
> + {
> + .base = (void *)0x040,
> + .group = 20,
> + .chip = {
> + .base = EXYNOS4_GPK0(0),
> + .ngpio = EXYNOS4_GPIO_K0_NR,
> + .label = "GPK0",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4_GPK1(0),
> + .ngpio = EXYNOS4_GPIO_K1_NR,
> + .label = "GPK1",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4_GPK2(0),
> + .ngpio = EXYNOS4_GPIO_K2_NR,
> + .label = "GPK2",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4_GPK3(0),
> + .ngpio = EXYNOS4_GPIO_K3_NR,
> + .label = "GPK3",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4_GPL0(0),
> + .ngpio = EXYNOS4_GPIO_L0_NR,
> + .label = "GPL0",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4_GPL1(0),
> + .ngpio = EXYNOS4_GPIO_L1_NR,
> + .label = "GPL1",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4_GPL2(0),
> + .ngpio = EXYNOS4_GPIO_L2_NR,
> + .label = "GPL2",
> + },
> + }, {
> + .config = &samsung_gpio_cfgs[8],
> + .chip = {
> + .base = EXYNOS4_GPY0(0),
> + .ngpio = EXYNOS4_GPIO_Y0_NR,
> + .label = "GPY0",
> + },
> + }, {
> + .config = &samsung_gpio_cfgs[8],
> + .chip = {
> + .base = EXYNOS4_GPY1(0),
> + .ngpio = EXYNOS4_GPIO_Y1_NR,
> + .label = "GPY1",
> + },
> + }, {
> + .config = &samsung_gpio_cfgs[8],
> + .chip = {
> + .base = EXYNOS4_GPY2(0),
> + .ngpio = EXYNOS4_GPIO_Y2_NR,
> + .label = "GPY2",
> + },
> + }, {
> + .config = &samsung_gpio_cfgs[8],
> + .chip = {
> + .base = EXYNOS4_GPY3(0),
> + .ngpio = EXYNOS4_GPIO_Y3_NR,
> + .label = "GPY3",
> + },
> + }, {
> + .config = &samsung_gpio_cfgs[8],
> + .chip = {
> + .base = EXYNOS4_GPY4(0),
> + .ngpio = EXYNOS4_GPIO_Y4_NR,
> + .label = "GPY4",
> + },
> + }, {
> + .config = &samsung_gpio_cfgs[8],
> + .chip = {
> + .base = EXYNOS4_GPY5(0),
> + .ngpio = EXYNOS4_GPIO_Y5_NR,
> + .label = "GPY5",
> + },
> + }, {
> + .config = &samsung_gpio_cfgs[8],
> + .chip = {
> + .base = EXYNOS4_GPY6(0),
> + .ngpio = EXYNOS4_GPIO_Y6_NR,
> + .label = "GPY6",
> + },
> + }, {
> + .base = (void *)0x260,
> + .chip = {
> + .base = EXYNOS4X12_GPM0(0),
> + .ngpio = EXYNOS4X12_GPIO_M0_NR,
> + .label = "GPM0",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4X12_GPM1(0),
> + .ngpio = EXYNOS4X12_GPIO_M1_NR,
> + .label = "GPM1",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4X12_GPM2(0),
> + .ngpio = EXYNOS4X12_GPIO_M2_NR,
> + .label = "GPM2",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4X12_GPM3(0),
> + .ngpio = EXYNOS4X12_GPIO_M3_NR,
> + .label = "GPM3",
> + },
> + }, {
> + .chip = {
> + .base = EXYNOS4X12_GPM4(0),
> + .ngpio = EXYNOS4X12_GPIO_M4_NR,
> + .label = "GPM4",
> + },
> + }, {
> + .base = (void *)0xC00,
> .config = &samsung_gpio_cfgs[9],
> .irq_base = IRQ_EINT(0),
> .chip = {
> @@ -2370,9 +2619,7 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
> },
> },
> };
There are no GPX banks instantiated here for 4x12. What is the reason for that?
> -#endif
>
> -#ifdef CONFIG_ARCH_EXYNOS4
> static struct samsung_gpio_chip exynos4_gpios_3[] = {
> {
> .chip = {
> @@ -2727,12 +2974,15 @@ static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
What is the limitation in adding support for GPVx as well for 4x12 ?
>
> static __init void exynos4_gpiolib_init(void)
> {
> -#ifdef CONFIG_CPU_EXYNOS4210
> +#ifdef CONFIG_ARCH_EXYNOS4
> struct samsung_gpio_chip *chip;
> int i, nr_chips;
> void __iomem *gpio_base1, *gpio_base2, *gpio_base3;
> int group = 0;
> void __iomem *gpx_base;
> + struct samsung_gpio_chip *chip_p;
> + int offset = 0;
> + int group1 = 0;
>
> /* gpio part1 */
> gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
> @@ -2741,19 +2991,31 @@ static __init void exynos4_gpiolib_init(void)
> goto err_ioremap1;
> }
>
> - chip = exynos4_gpios_1;
> - nr_chips = ARRAY_SIZE(exynos4_gpios_1);
> + if (soc_is_exynos4210()) {
> + chip = chip_p = exynos4210_gpios_1;
> + nr_chips = ARRAY_SIZE(exynos4210_gpios_1);
> + } else {
> + chip = chip_p = exynos4x12_gpios_1;
> + nr_chips = ARRAY_SIZE(exynos4x12_gpios_1);
> + }
>
> for (i = 0; i < nr_chips; i++, chip++) {
> if (!chip->config) {
> chip->config = &exynos_gpio_cfg;
> + if (chip->group)
> + group = chip->group;
> chip->group = group++;
> }
> - exynos_gpiolib_attach_ofnode(chip,
> - EXYNOS4_PA_GPIO1, i * 0x20);
> +
> + if (chip->base)
> + offset = (u32)chip->base;
> + chip->base = gpio_base1 + offset;
> + offset += 0x20;
> +
> + exynos_gpiolib_attach_ofnode(chip, EXYNOS4_PA_GPIO1, 0);
> }
> - samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
> - nr_chips, gpio_base1);
> + samsung_gpiolib_add_4bit_chips(chip_p, nr_chips, gpio_base1);
> + group1 = group;
>
> /* gpio part2 */
> gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
> @@ -2762,25 +3024,32 @@ static __init void exynos4_gpiolib_init(void)
> goto err_ioremap2;
> }
>
> - /* need to set base address for gpx */
> - chip = &exynos4_gpios_2[16];
> - gpx_base = gpio_base2 + 0xC00;
> - for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
> - chip->base = gpx_base;
> + if (soc_is_exynos4210()) {
> + chip = chip_p = exynos4210_gpios_2;
> + nr_chips = ARRAY_SIZE(exynos4210_gpios_2);
> + } else {
> + chip = chip_p = exynos4x12_gpios_2;
> + nr_chips = ARRAY_SIZE(exynos4x12_gpios_2);
> + }
>
> - chip = exynos4_gpios_2;
> - nr_chips = ARRAY_SIZE(exynos4_gpios_2);
> + offset = 0;
>
> for (i = 0; i < nr_chips; i++, chip++) {
> if (!chip->config) {
> chip->config = &exynos_gpio_cfg;
> + if (chip->group)
> + group = chip->group;
> chip->group = group++;
> }
> - exynos_gpiolib_attach_ofnode(chip,
> - EXYNOS4_PA_GPIO2, i * 0x20);
> +
> + if (chip->base)
> + offset = (u32)chip->base;
> + chip->base = gpio_base2 + offset;
> + offset += 0x20;
> +
> + exynos_gpiolib_attach_ofnode(chip, EXYNOS4_PA_GPIO2, 0);
> }
> - samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
> - nr_chips, gpio_base2);
> + samsung_gpiolib_add_4bit_chips(chip_p, nr_chips, gpio_base2);
>
> /* gpio part3 */
> gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
> @@ -2801,12 +3070,10 @@ static __init void exynos4_gpiolib_init(void)
> EXYNOS4_PA_GPIO3, i * 0x20);
> }
> samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
> - nr_chips, gpio_base3);
> + nr_chips, gpio_base3);
>
> -#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
> - s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
> - s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
> -#endif
> + s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, group1);
> + s5p_register_gpioint_bank(IRQ_GPIO_XB, group1, group - group1);
>
> return;
>
> @@ -2816,7 +3083,7 @@ err_ioremap2:
> iounmap(gpio_base1);
> err_ioremap1:
> return;
> -#endif /* CONFIG_CPU_EXYNOS4210 */
> +#endif /* CONFIG_ARCH_EXYNOS4 */
> }
>
> static __init void exynos5_gpiolib_init(void)
> @@ -3010,7 +3277,8 @@ static __init int samsung_gpiolib_init(void)
> #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
> s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
> #endif
> - } else if (soc_is_exynos4210()) {
> + } else if (soc_is_exynos4210() || soc_is_exynos4212() ||
> + soc_is_exynos4412()) {
> exynos4_gpiolib_init();
> } else if (soc_is_exynos5250()) {
> exynos5_gpiolib_init();
> --
> 1.7.12
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 0/3] ARM: EXYNOS: Add support for GPIO on Exynos4x12
2012-08-28 10:01 [PATCH 0/3] ARM: EXYNOS: Add support for GPIO on Exynos4x12 Tomasz Figa
` (2 preceding siblings ...)
2012-08-28 10:07 ` [PATCH 3/3] ARM: EXYNOS: Add support for FIMC cam port B GPIO setup on Exynos4x12 Tomasz Figa
@ 2012-08-28 14:58 ` Thomas Abraham
2012-08-31 22:46 ` Linus Walleij
3 siblings, 1 reply; 12+ messages in thread
From: Thomas Abraham @ 2012-08-28 14:58 UTC (permalink / raw)
To: linux-arm-kernel
On 28 August 2012 15:31, Tomasz Figa <t.figa@samsung.com> wrote:
> This patch series makes necessary preparations and adds support for GPIO on
> Exynos4x12 SoCs.
>
> Tomasz Figa (3):
> ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
> gpio: samsung: Add support for Exynos4x12 SoCs
> ARM: EXYNOS: Add support for FIMC cam port B GPIO setup on Exynos4x12
>
> arch/arm/mach-exynos/include/mach/gpio.h | 58 ++++--
> arch/arm/mach-exynos/include/mach/irqs.h | 6 -
> arch/arm/mach-exynos/mach-nuri.c | 16 +-
> arch/arm/mach-exynos/mach-origen.c | 6 +-
> arch/arm/mach-exynos/mach-trats.c | 4 +-
> arch/arm/mach-exynos/mach-universal_c210.c | 32 ++--
> arch/arm/mach-exynos/setup-fimc.c | 21 ++-
> drivers/gpio/gpio-samsung.c | 351
> ++++++++++++++++++++++++----
> 8 files changed, 399 insertions(+), 95 deletions(-)
>
> --
> 1.7.8.6
Hopefully, we can get device tree support merged for Exynos4412 soon
and then switch over to using pinctrl driver. That can simplfy the
gpio/pinmux support for Exynos4 SoC's.
Thanks,
Thomas.
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/3] gpio: samsung: Add support for Exynos4x12 SoCs
2012-08-28 14:55 ` Thomas Abraham
@ 2012-08-28 17:27 ` Tomasz Figa
0 siblings, 0 replies; 12+ messages in thread
From: Tomasz Figa @ 2012-08-28 17:27 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Thanks for reviewing the patch.
On Tuesday 28 of August 2012 20:25:34 Thomas Abraham wrote:
> > + }, {
> > + .config = &samsung_gpio_cfgs[9],
> > + .irq_base = IRQ_EINT(24),
> > + .chip = {
> > + .base = EXYNOS4_GPX3(0),
> > + .ngpio = EXYNOS4_GPIO_X3_NR,
> > + .label = "GPX3",
> > + .to_irq = samsung_gpiolib_to_irq,
> > + },
> > + },
> > +};
>
> I see that GPX0, GPX1, GPX2 and GPX3 bank instances are already part
> of mainline kernel. How is that this is being added here.
It seems like somehow GPXx are added to exynos4210_gpios_2 again and the
already present part is used for exynos4x12_gpios_2. I guess that it's
because of adding ".base = (void *)0xC00" to GPX0, which might be an
accidental mistake. I will recheck that.
> > + }, {
> > + .base = (void *)0xC00,
> >
> > .config = &samsung_gpio_cfgs[9],
> > .irq_base = IRQ_EINT(0),
> > .chip = {
> >
> > @@ -2370,9 +2619,7 @@ static struct samsung_gpio_chip exynos4_gpios_2[]
> > = {>
> > },
> >
> > },
> >
> > };
>
> There are no GPX banks instantiated here for 4x12. What is the reason for
> that?
See previous point. GPXx which have been part of exynos4_gpios_2 become
part of exynos4210_gpios_2.
> > -#endif
> >
> > -#ifdef CONFIG_ARCH_EXYNOS4
> >
> > static struct samsung_gpio_chip exynos4_gpios_3[] = {
> >
> > {
> >
> > .chip = {
> >
> > @@ -2727,12 +2974,15 @@ static __init void
> > exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
> What is the limitation in adding support for GPVx as well for 4x12 ?
I'm not sure, I might have simply overlooked GPVx. I will recheck that
tomorrow.
Best regards,
--
Tomasz Figa
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
2012-08-28 10:06 ` [PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx Tomasz Figa
2012-08-28 14:48 ` Thomas Abraham
@ 2012-08-28 23:44 ` Kukjin Kim
2012-08-29 0:03 ` Kyungmin Park
1 sibling, 1 reply; 12+ messages in thread
From: Kukjin Kim @ 2012-08-28 23:44 UTC (permalink / raw)
To: linux-arm-kernel
On 08/28/12 03:06, Tomasz Figa wrote:
> The GPEx gpios are specific to Exynos4210 and do not exist on Exynos4x12.
> Redefine them to use the exact SoC name.
>
> Based on "ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx" by
> Joonyoung Shim, see:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/100738.html
>
> Signed-off-by: Tomasz Figa<t.figa@samsung.com>
> ---
> arch/arm/mach-exynos/include/mach/gpio.h | 32 +++++++++++++++---------------
> arch/arm/mach-exynos/mach-nuri.c | 16 +++++++--------
> arch/arm/mach-exynos/mach-origen.c | 6 +++---
> arch/arm/mach-exynos/mach-trats.c | 4 ++--
> arch/arm/mach-exynos/mach-universal_c210.c | 32 +++++++++++++++---------------
> arch/arm/mach-exynos/setup-fimc.c | 4 ++--
> drivers/gpio/gpio-samsung.c | 20 +++++++++----------
> 7 files changed, 57 insertions(+), 57 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
> index eb24f1e..21c9bf1 100644
> --- a/arch/arm/mach-exynos/include/mach/gpio.h
> +++ b/arch/arm/mach-exynos/include/mach/gpio.h
> @@ -26,11 +26,11 @@
> #define EXYNOS4_GPIO_C1_NR (5)
> #define EXYNOS4_GPIO_D0_NR (4)
> #define EXYNOS4_GPIO_D1_NR (4)
> -#define EXYNOS4_GPIO_E0_NR (5)
> -#define EXYNOS4_GPIO_E1_NR (8)
> -#define EXYNOS4_GPIO_E2_NR (6)
> -#define EXYNOS4_GPIO_E3_NR (8)
> -#define EXYNOS4_GPIO_E4_NR (8)
> +#define EXYNOS4210_GPIO_E0_NR (5)
> +#define EXYNOS4210_GPIO_E1_NR (8)
> +#define EXYNOS4210_GPIO_E2_NR (6)
> +#define EXYNOS4210_GPIO_E3_NR (8)
> +#define EXYNOS4210_GPIO_E4_NR (8)
Please see my comments on Joonyoung Shim's previous patch...
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/101522.html
[...]
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
2012-08-28 23:44 ` Kukjin Kim
@ 2012-08-29 0:03 ` Kyungmin Park
2012-08-29 13:52 ` Tomasz Figa
0 siblings, 1 reply; 12+ messages in thread
From: Kyungmin Park @ 2012-08-29 0:03 UTC (permalink / raw)
To: linux-arm-kernel
On 8/29/12, Kukjin Kim <kgene.kim@samsung.com> wrote:
> On 08/28/12 03:06, Tomasz Figa wrote:
>> The GPEx gpios are specific to Exynos4210 and do not exist on Exynos4x12.
>> Redefine them to use the exact SoC name.
>>
>> Based on "ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx" by
>> Joonyoung Shim, see:
>> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/100738.html
>>
>> Signed-off-by: Tomasz Figa<t.figa@samsung.com>
>> ---
>> arch/arm/mach-exynos/include/mach/gpio.h | 32
>> +++++++++++++++---------------
>> arch/arm/mach-exynos/mach-nuri.c | 16 +++++++--------
>> arch/arm/mach-exynos/mach-origen.c | 6 +++---
>> arch/arm/mach-exynos/mach-trats.c | 4 ++--
>> arch/arm/mach-exynos/mach-universal_c210.c | 32
>> +++++++++++++++---------------
>> arch/arm/mach-exynos/setup-fimc.c | 4 ++--
>> drivers/gpio/gpio-samsung.c | 20 +++++++++----------
>> 7 files changed, 57 insertions(+), 57 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/include/mach/gpio.h
>> b/arch/arm/mach-exynos/include/mach/gpio.h
>> index eb24f1e..21c9bf1 100644
>> --- a/arch/arm/mach-exynos/include/mach/gpio.h
>> +++ b/arch/arm/mach-exynos/include/mach/gpio.h
>> @@ -26,11 +26,11 @@
>> #define EXYNOS4_GPIO_C1_NR (5)
>> #define EXYNOS4_GPIO_D0_NR (4)
>> #define EXYNOS4_GPIO_D1_NR (4)
>> -#define EXYNOS4_GPIO_E0_NR (5)
>> -#define EXYNOS4_GPIO_E1_NR (8)
>> -#define EXYNOS4_GPIO_E2_NR (6)
>> -#define EXYNOS4_GPIO_E3_NR (8)
>> -#define EXYNOS4_GPIO_E4_NR (8)
>> +#define EXYNOS4210_GPIO_E0_NR (5)
>> +#define EXYNOS4210_GPIO_E1_NR (8)
>> +#define EXYNOS4210_GPIO_E2_NR (6)
>> +#define EXYNOS4210_GPIO_E3_NR (8)
>> +#define EXYNOS4210_GPIO_E4_NR (8)
>
> Please see my comments on Joonyoung Shim's previous patch...
> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/101522.html
It's perference issue. some person like this style. others doesn't.
Moreever vender, System LSI, provided codes have whole different style.
It lists up whole gpios for each SoCs.
EXYNOS4210_{A0, .... Z}
EXYNOS4412_{A0, .... V4}
EXYNOS5250_{A0, .... Z}
anyway, just remain it as broken, and try to use pinctl as Thomas mentioned.
Thank you,
Kyungmin Park
>
> [...]
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
2012-08-29 0:03 ` Kyungmin Park
@ 2012-08-29 13:52 ` Tomasz Figa
0 siblings, 0 replies; 12+ messages in thread
From: Tomasz Figa @ 2012-08-29 13:52 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Wednesday 29 of August 2012 09:03:12 Kyungmin Park wrote:
> On 8/29/12, Kukjin Kim <kgene.kim@samsung.com> wrote:
> > Please see my comments on Joonyoung Shim's previous patch...
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/101522.h
> > tml
> It's perference issue. some person like this style. others doesn't.
> Moreever vender, System LSI, provided codes have whole different style.
> It lists up whole gpios for each SoCs.
>
> EXYNOS4210_{A0, .... Z}
> EXYNOS4412_{A0, .... V4}
> EXYNOS5250_{A0, .... Z}
>
> anyway, just remain it as broken, and try to use pinctl as Thomas
> mentioned.
OK, I will drop this patchset for the time being. Let's get the pinctrl
driver merged first and then investigate Exynos4x12 support in it.
Best regards,
--
Tomasz Figa
Samsung Poland R&D Center
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 0/3] ARM: EXYNOS: Add support for GPIO on Exynos4x12
2012-08-28 14:58 ` [PATCH 0/3] ARM: EXYNOS: Add support for GPIO " Thomas Abraham
@ 2012-08-31 22:46 ` Linus Walleij
0 siblings, 0 replies; 12+ messages in thread
From: Linus Walleij @ 2012-08-31 22:46 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Aug 28, 2012 at 4:58 PM, Thomas Abraham
<thomas.abraham@linaro.org> wrote:
> On 28 August 2012 15:31, Tomasz Figa <t.figa@samsung.com> wrote:
>> This patch series makes necessary preparations and adds support for GPIO on
>> Exynos4x12 SoCs.
>
> Hopefully, we can get device tree support merged for Exynos4412 soon
> and then switch over to using pinctrl driver. That can simplfy the
> gpio/pinmux support for Exynos4 SoC's.
This sounds like a NACK.
I will not merge these patches until Ben or Kukjin (the Samsung
maintainers listed in MAINTAINERS) ACK it.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2012-08-31 22:46 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-08-28 10:01 [PATCH 0/3] ARM: EXYNOS: Add support for GPIO on Exynos4x12 Tomasz Figa
2012-08-28 10:06 ` [PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx Tomasz Figa
2012-08-28 14:48 ` Thomas Abraham
2012-08-28 23:44 ` Kukjin Kim
2012-08-29 0:03 ` Kyungmin Park
2012-08-29 13:52 ` Tomasz Figa
2012-08-28 10:06 ` [PATCH 2/3] gpio: samsung: Add support for Exynos4x12 SoCs Tomasz Figa
2012-08-28 14:55 ` Thomas Abraham
2012-08-28 17:27 ` Tomasz Figa
2012-08-28 10:07 ` [PATCH 3/3] ARM: EXYNOS: Add support for FIMC cam port B GPIO setup on Exynos4x12 Tomasz Figa
2012-08-28 14:58 ` [PATCH 0/3] ARM: EXYNOS: Add support for GPIO " Thomas Abraham
2012-08-31 22:46 ` Linus Walleij
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).