* [PATCH 1/3]: Support cpu frequency scaling and power management for iMX6SL
@ 2013-12-17 1:40 John Tobias
2013-12-17 2:37 ` John Tobias
2013-12-17 14:04 ` Shawn Guo
0 siblings, 2 replies; 6+ messages in thread
From: John Tobias @ 2013-12-17 1:40 UTC (permalink / raw)
To: linux-arm-kernel
iMX6SL device tree doesn't have a configuration settings to enable the
frequency scaling and power management.
From: John Tobias <john.tobias.ph@gmail.com>
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 28558f1..0ad2f6a 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -38,6 +38,19 @@
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
+ operating-points = <
+ /* kHz uV */
+ 1000000 1275000
+ 792000 1150000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = <&clks IMX6SL_CLK_ARM>, <&clks
IMX6SL_CLK_PLL2_PFD2>, <&clks IMX6SL_CLK_STEP>,
+ <&clks IMX6SL_CLK_PLL1_SW>, <&clks
IMX6SL_CLK_PLL1_SYS>;
+ clock-names = "arm", "pll2_pfd2_396m", "step",
+ "pll1_sw", "pll1_sys";
+ arm-supply = <®_arm>;
+ pu-supply = <®_pu>;
+ soc-supply = <®_soc>;
};
};
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 1/3]: Support cpu frequency scaling and power management for iMX6SL
2013-12-17 1:40 [PATCH 1/3]: Support cpu frequency scaling and power management for iMX6SL John Tobias
@ 2013-12-17 2:37 ` John Tobias
[not found] ` <52B09856.5050609@tqsc.de>
2013-12-17 14:04 ` Shawn Guo
1 sibling, 1 reply; 6+ messages in thread
From: John Tobias @ 2013-12-17 2:37 UTC (permalink / raw)
To: linux-arm-kernel
Need some correction:
From: John Tobias <john.tobias.ph@gmail.com>
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 28558f1..6035e7e 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -38,6 +38,21 @@
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
+ operating-points = <
+ /* kHz uV */
+ 1000000 1275000
+ 996000 1250000
+ 792000 1150000
+ 396000 950000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = <&clks IMX6SL_CLK_ARM>, <&clks
IMX6SL_CLK_PLL2_PFD2>, <&clks IMX6SL_CLK_STEP>,
+ <&clks IMX6SL_CLK_PLL1_SW>, <&clks
IMX6SL_CLK_PLL1_SYS>;
+ clock-names = "arm", "pll2_pfd2_396m", "step",
+ "pll1_sw", "pll1_sys";
+ arm-supply = <®_arm>;
+ pu-supply = <®_pu>;
+ soc-supply = <®_soc>;
};
};
On Mon, Dec 16, 2013 at 5:40 PM, John Tobias <john.tobias.ph@gmail.com> wrote:
> iMX6SL device tree doesn't have a configuration settings to enable the
> frequency scaling and power management.
>
> From: John Tobias <john.tobias.ph@gmail.com>
>
>
> diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
> index 28558f1..0ad2f6a 100644
> --- a/arch/arm/boot/dts/imx6sl.dtsi
> +++ b/arch/arm/boot/dts/imx6sl.dtsi
> @@ -38,6 +38,19 @@
> device_type = "cpu";
> reg = <0x0>;
> next-level-cache = <&L2>;
> + operating-points = <
> + /* kHz uV */
> + 1000000 1275000
> + 792000 1150000
> + >;
> + clock-latency = <61036>; /* two CLK32 periods */
> + clocks = <&clks IMX6SL_CLK_ARM>, <&clks
> IMX6SL_CLK_PLL2_PFD2>, <&clks IMX6SL_CLK_STEP>,
> + <&clks IMX6SL_CLK_PLL1_SW>, <&clks
> IMX6SL_CLK_PLL1_SYS>;
> + clock-names = "arm", "pll2_pfd2_396m", "step",
> + "pll1_sw", "pll1_sys";
> + arm-supply = <®_arm>;
> + pu-supply = <®_pu>;
> + soc-supply = <®_soc>;
> };
> };
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 1/3]: Support cpu frequency scaling and power management for iMX6SL
2013-12-17 1:40 [PATCH 1/3]: Support cpu frequency scaling and power management for iMX6SL John Tobias
2013-12-17 2:37 ` John Tobias
@ 2013-12-17 14:04 ` Shawn Guo
1 sibling, 0 replies; 6+ messages in thread
From: Shawn Guo @ 2013-12-17 14:04 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Dec 16, 2013 at 05:40:15PM -0800, John Tobias wrote:
> iMX6SL device tree doesn't have a configuration settings to enable the
> frequency scaling and power management.
>
> From: John Tobias <john.tobias.ph@gmail.com>
Please use 'git format-patch' and 'git send-email'. Also, it's never
been a good idea to use the exactly same patch subject for 3 different
changes.
Shawn
>
>
> diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
> index 28558f1..0ad2f6a 100644
> --- a/arch/arm/boot/dts/imx6sl.dtsi
> +++ b/arch/arm/boot/dts/imx6sl.dtsi
> @@ -38,6 +38,19 @@
> device_type = "cpu";
> reg = <0x0>;
> next-level-cache = <&L2>;
> + operating-points = <
> + /* kHz uV */
> + 1000000 1275000
> + 792000 1150000
> + >;
> + clock-latency = <61036>; /* two CLK32 periods */
> + clocks = <&clks IMX6SL_CLK_ARM>, <&clks
> IMX6SL_CLK_PLL2_PFD2>, <&clks IMX6SL_CLK_STEP>,
> + <&clks IMX6SL_CLK_PLL1_SW>, <&clks
> IMX6SL_CLK_PLL1_SYS>;
> + clock-names = "arm", "pll2_pfd2_396m", "step",
> + "pll1_sw", "pll1_sys";
> + arm-supply = <®_arm>;
> + pu-supply = <®_pu>;
> + soc-supply = <®_soc>;
> };
> };
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/3]: Support cpu frequency scaling and power management for iMX6SL
[not found] ` <52B09856.5050609@tqsc.de>
@ 2013-12-17 18:31 ` John Tobias
2013-12-18 2:38 ` Shawn Guo
1 sibling, 0 replies; 6+ messages in thread
From: John Tobias @ 2013-12-17 18:31 UTC (permalink / raw)
To: linux-arm-kernel
Guys,
Thanks for your input. I will re-submitting my patches later.
Regards,
john
On Tue, Dec 17, 2013 at 10:30 AM, Markus Niebel <list-09@tqsc.de> wrote:
> Am 17.12.2013 03:37, wrote John Tobias:
>> Need some correction:
>>
>> From: John Tobias <john.tobias.ph@gmail.com>
>>
>>
>> diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
>> index 28558f1..6035e7e 100644
>> --- a/arch/arm/boot/dts/imx6sl.dtsi
>> +++ b/arch/arm/boot/dts/imx6sl.dtsi
>> @@ -38,6 +38,21 @@
>> device_type = "cpu";
>> reg = <0x0>;
>> next-level-cache = <&L2>;
>> + operating-points = <
>> + /* kHz uV */
>> + 1000000 1275000
>> + 996000 1250000
>> + 792000 1150000
>> + 396000 950000
>> + >;
>> + clock-latency = <61036>; /* two CLK32 periods */
>> + clocks = <&clks IMX6SL_CLK_ARM>, <&clks
>> IMX6SL_CLK_PLL2_PFD2>, <&clks IMX6SL_CLK_STEP>,
>> + <&clks IMX6SL_CLK_PLL1_SW>, <&clks
>> IMX6SL_CLK_PLL1_SYS>;
>> + clock-names = "arm", "pll2_pfd2_396m", "step",
>> + "pll1_sw", "pll1_sys";
>> + arm-supply = <®_arm>;
>> + pu-supply = <®_pu>;
>> + soc-supply = <®_soc>;
>> };
>> };
>>
>>
>> On Mon, Dec 16, 2013 at 5:40 PM, John Tobias <john.tobias.ph@gmail.com> wrote:
>>> iMX6SL device tree doesn't have a configuration settings to enable the
>>> frequency scaling and power management.
>>>
>>> From: John Tobias <john.tobias.ph@gmail.com>
>>>
>>>
>>> diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
>>> index 28558f1..0ad2f6a 100644
>>> --- a/arch/arm/boot/dts/imx6sl.dtsi
>>> +++ b/arch/arm/boot/dts/imx6sl.dtsi
>>> @@ -38,6 +38,19 @@
>>> device_type = "cpu";
>>> reg = <0x0>;
>>> next-level-cache = <&L2>;
>>> + operating-points = <
>>> + /* kHz uV */
>>> + 1000000 1275000
>>> + 792000 1150000
>
> according to the CPU documentation the following operation points are suggested (at least AFAIK):
> 996000 1250000 /* for consumer grade only */
> 792000 1150000
> 396000 1050000
> note: AFAIK there is no way to detect at runtime if we running on industrial / automotive variant
> so there is a risk to run at too high frequency ...
>>> + >;
>>> + clock-latency = <61036>; /* two CLK32 periods */
>>> + clocks = <&clks IMX6SL_CLK_ARM>, <&clks
>>> IMX6SL_CLK_PLL2_PFD2>, <&clks IMX6SL_CLK_STEP>,
>>> + <&clks IMX6SL_CLK_PLL1_SW>, <&clks
>>> IMX6SL_CLK_PLL1_SYS>;
>>> + clock-names = "arm", "pll2_pfd2_396m", "step",
>>> + "pll1_sw", "pll1_sys";
>>> + arm-supply = <®_arm>;
>>> + pu-supply = <®_pu>;
>>> + soc-supply = <®_soc>;
>>> };
>>> };
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/3]: Support cpu frequency scaling and power management for iMX6SL
[not found] ` <52B09856.5050609@tqsc.de>
2013-12-17 18:31 ` John Tobias
@ 2013-12-18 2:38 ` Shawn Guo
2013-12-18 3:03 ` John Tobias
1 sibling, 1 reply; 6+ messages in thread
From: Shawn Guo @ 2013-12-18 2:38 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Dec 17, 2013 at 07:30:46PM +0100, Markus Niebel wrote:
> >> @@ -38,6 +38,19 @@
> >> device_type = "cpu";
> >> reg = <0x0>;
> >> next-level-cache = <&L2>;
> >> + operating-points = <
> >> + /* kHz uV */
> >> + 1000000 1275000
> >> + 792000 1150000
>
> according to the CPU documentation the following operation points are suggested (at least AFAIK):
> 996000 1250000 /* for consumer grade only */
> 792000 1150000
> 396000 1050000
> note: AFAIK there is no way to detect at runtime if we running on industrial / automotive variant
> so there is a risk to run at too high frequency ...
I can only find IMX6SLCEC - i.MX 6SoloLite Applications Processors for
Consumer Products on freescale website.
http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6SLCEC.pdf?fpsp=1
In that document, I can see the following in Table 9. Operating Ranges.
LDO output set at 1.250V minimum for operation up to 996MHz
LDO output set at 1.150V minimum for operation up to 792MHz
LDO output set at 0.95V minimum for operation up to 396MHz
However, if you access Freescale 3.10 kernel tree, you will see there
are 25mV addition to each operating-point.
operating-points = <
/* kHz uV */
996000 1275000
792000 1175000
396000 975000
>;
>From the commit log, it said this 25mV is added to compensate the output
tolerance from external regulators.
I suggest we follow Freescale kernel to set the operating-points.
Shawn
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/3]: Support cpu frequency scaling and power management for iMX6SL
2013-12-18 2:38 ` Shawn Guo
@ 2013-12-18 3:03 ` John Tobias
0 siblings, 0 replies; 6+ messages in thread
From: John Tobias @ 2013-12-18 3:03 UTC (permalink / raw)
To: linux-arm-kernel
I think that's the right way to do it. Follow the Freescale kernel to
set the operating-points.
On Tue, Dec 17, 2013 at 6:38 PM, Shawn Guo <shawn.guo@linaro.org> wrote:
> On Tue, Dec 17, 2013 at 07:30:46PM +0100, Markus Niebel wrote:
>> >> @@ -38,6 +38,19 @@
>> >> device_type = "cpu";
>> >> reg = <0x0>;
>> >> next-level-cache = <&L2>;
>> >> + operating-points = <
>> >> + /* kHz uV */
>> >> + 1000000 1275000
>> >> + 792000 1150000
>>
>> according to the CPU documentation the following operation points are suggested (at least AFAIK):
>> 996000 1250000 /* for consumer grade only */
>> 792000 1150000
>> 396000 1050000
>> note: AFAIK there is no way to detect at runtime if we running on industrial / automotive variant
>> so there is a risk to run at too high frequency ...
>
> I can only find IMX6SLCEC - i.MX 6SoloLite Applications Processors for
> Consumer Products on freescale website.
>
> http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6SLCEC.pdf?fpsp=1
>
> In that document, I can see the following in Table 9. Operating Ranges.
>
> LDO output set at 1.250V minimum for operation up to 996MHz
> LDO output set at 1.150V minimum for operation up to 792MHz
> LDO output set at 0.95V minimum for operation up to 396MHz
>
> However, if you access Freescale 3.10 kernel tree, you will see there
> are 25mV addition to each operating-point.
>
> operating-points = <
> /* kHz uV */
> 996000 1275000
> 792000 1175000
> 396000 975000
> >;
>
> From the commit log, it said this 25mV is added to compensate the output
> tolerance from external regulators.
>
> I suggest we follow Freescale kernel to set the operating-points.
>
> Shawn
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2013-12-18 3:03 UTC | newest]
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2013-12-17 18:31 ` John Tobias
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