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Tue, 11 Mar 2025 15:36:49 -0700 (PDT) MIME-Version: 1.0 References: <20250304-msm-gpu-fault-fixes-next-v4-0-be14be37f4c3@gmail.com> <20250304-msm-gpu-fault-fixes-next-v4-1-be14be37f4c3@gmail.com> <20250311180553.GB5216@willie-the-truck> In-Reply-To: <20250311180553.GB5216@willie-the-truck> From: Connor Abbott Date: Tue, 11 Mar 2025 18:36:38 -0400 X-Gm-Features: AQ5f1Jpps08fowB20qui8teO0kCK3_0sMgX__rQse3av3tUA4enIqUvNjCSXypk Message-ID: Subject: Re: [PATCH v4 1/5] iommu/arm-smmu: Save additional information on context fault To: Will Deacon Cc: Rob Clark , Robin Murphy , Joerg Roedel , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, freedreno@lists.freedesktop.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250311_153650_818972_3562BAA3 X-CRM114-Status: GOOD ( 25.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Mar 11, 2025 at 2:06=E2=80=AFPM Will Deacon wrote= : > > On Tue, Mar 04, 2025 at 11:56:47AM -0500, Connor Abbott wrote: > > This will be used by drm/msm for GPU page faults, replacing the manual > > register reading it does. > > > > Signed-off-by: Connor Abbott > > --- > > drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 4 ++-- > > drivers/iommu/arm/arm-smmu/arm-smmu.c | 27 +++++++++++++---= -------- > > drivers/iommu/arm/arm-smmu/arm-smmu.h | 5 ++++- > > 3 files changed, 21 insertions(+), 15 deletions(-) > > > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers= /iommu/arm/arm-smmu/arm-smmu-qcom-debug.c > > index 548783f3f8e89fd978367afa65c473002f66e2e7..ae4fdbbce6ba80440f53955= 7a39866a932360d4e 100644 > > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c > > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c > > @@ -400,7 +400,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *= dev) > > > > if (list_empty(&tbu_list)) { > > ret =3D report_iommu_fault(&smmu_domain->domain, NULL, cf= i.iova, > > - cfi.fsynr & ARM_SMMU_CB_FSYNR0_W= NR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); > > + cfi.fsynr0 & ARM_SMMU_CB_FSYNR0_= WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); > > > > if (ret =3D=3D -ENOSYS) > > arm_smmu_print_context_fault_info(smmu, idx, &cfi= ); > > @@ -412,7 +412,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *= dev) > > phys_soft =3D ops->iova_to_phys(ops, cfi.iova); > > > > tmp =3D report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova, > > - cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOM= MU_FAULT_WRITE : IOMMU_FAULT_READ); > > + cfi.fsynr0 & ARM_SMMU_CB_FSYNR0_WNR ? IO= MMU_FAULT_WRITE : IOMMU_FAULT_READ); > > if (!tmp || tmp =3D=3D -EBUSY) { > > ret =3D IRQ_HANDLED; > > resume =3D ARM_SMMU_RESUME_TERMINATE; > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/= arm-smmu/arm-smmu.c > > index ade4684c14c9b2724a71e2457288dbfaf7562c83..a9213e0f1579d1e3be0bfba= 75eea1d5de23117de 100644 > > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c > > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c > > @@ -409,9 +409,12 @@ void arm_smmu_read_context_fault_info(struct arm_s= mmu_device *smmu, int idx, > > struct arm_smmu_context_fault_info = *cfi) > > { > > cfi->iova =3D arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR); > > + cfi->ttbr0 =3D arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_TTBR0); > > cfi->fsr =3D arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); > > - cfi->fsynr =3D arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0); > > + cfi->fsynr0 =3D arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0); > > + cfi->fsynr1 =3D arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR1); > > We already have an implementation hook (->get_fault_info()) which the > qcom SMMU driver can override with qcom_adreno_smmu_get_fault_info(). > That thing dumps these registers already so if we're moving that into > the core SMMU driver, let's get rid of the hook and move everybody over > rather than having it done in both places. As you probably saw, the next commit moves over qcom_adreno_smmu_get_fault_info() to use this. The current back door used by drm/msm to access these functions is specific to adreno_smmu and there isn't an equivalent interface to allow it to call a generic SMMU function so it isn't possible to move it entirely to the core. At least not without a bigger refactoring that isn't justified for this series that is just trying to fix things. > > > cfi->cbfrsynra =3D arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA= (idx)); > > + cfi->contextidr =3D arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_CONTE= XTIDR); > > I think the CONTEXTIDR register is stage-1 only, so we shouldn't dump > it for stage-2 domains. > > Will Does it matter if we read the register though, as long as users are aware of this and don't use its value for anything? Connor