some question about writel implement in arm platform

some question about writel implement in arm platform

[yoma sophian]

hi all:
the implementation of writel in ARM is writel_relaxed() with barrier
before (DSB + outer cache sync).

if the memory is device memory, shall we still need outer cache sync?
if the memory is normal normal, under what circumstance we will write
it with writel.
As far as I know, the writel is used for register writing.

appreciate your kind help in advance,

some question about writel implement in arm platform

[Arnd Bergmann]

On Thursday 16 April 2015 13:28:41 yoma sophian wrote:
> hi all:
> the implementation of writel in ARM is writel_relaxed() with barrier
> before (DSB + outer cache sync).
> 
> if the memory is device memory, shall we still need outer cache sync?

Yes.

> if the memory is normal normal, under what circumstance we will write
> it with writel.

For normal memory, you never use writel.

> As far as I know, the writel is used for register writing.

Correct.

	Arnd

some question about writel implement in arm platform

[yoma sophian]

hi arnd:

2015-04-16 14:19 GMT+08:00 Arnd Bergmann <arnd@arndb.de>:
> On Thursday 16 April 2015 13:28:41 yoma sophian wrote:
>> hi all:
>> the implementation of writel in ARM is writel_relaxed() with barrier
>> before (DSB + outer cache sync).
>>
>> if the memory is device memory, shall we still need outer cache sync?
>
> Yes.
Take my platform for example, I use Cortex A9 with PL310 L2 cache controller.
if the memory is device memory, that mean it is un-cacheable why we
still need to out sync off the PL310 buffer in writel operation?
>
>> if the memory is normal normal, under what circumstance we will write
>> it with writel.
>
> For normal memory, you never use writel.
>
>> As far as I know, the writel is used for register writing.
>
> Correct.
if so, why we need to do PL310 cache sync for those memory that are
not cacheable?

appreciate your kind help,

some question about writel implement in arm platform

[Arnd Bergmann]

On Thursday 16 April 2015 16:06:16 yoma sophian wrote:
> 
> 2015-04-16 14:19 GMT+08:00 Arnd Bergmann <arnd@arndb.de>:
> > On Thursday 16 April 2015 13:28:41 yoma sophian wrote:
> >> hi all:
> >> the implementation of writel in ARM is writel_relaxed() with barrier
> >> before (DSB + outer cache sync).
> >>
> >> if the memory is device memory, shall we still need outer cache sync?
> >
> > Yes.
> Take my platform for example, I use Cortex A9 with PL310 L2 cache controller.
> if the memory is device memory, that mean it is un-cacheable why we
> still need to out sync off the PL310 buffer in writel operation?

The l2 sync is to ensure that prior memory writes are visible to a DMA
master that gets triggered by the writel.

If your device is not a DMA master, or the operation is unrelated to
DMA, you can use writel_relaxed().

	Arnd

some question about writel implement in arm platform

[yoma sophian]

hi arnd:

2015-04-16 17:47 GMT+08:00 Arnd Bergmann <arnd@arndb.de>:
> On Thursday 16 April 2015 16:06:16 yoma sophian wrote:
>>
>> 2015-04-16 14:19 GMT+08:00 Arnd Bergmann <arnd@arndb.de>:
>> > On Thursday 16 April 2015 13:28:41 yoma sophian wrote:
>> >> hi all:
>> >> the implementation of writel in ARM is writel_relaxed() with barrier
>> >> before (DSB + outer cache sync).
>> >>
>> >> if the memory is device memory, shall we still need outer cache sync?
>> >
>> > Yes.
>> Take my platform for example, I use Cortex A9 with PL310 L2 cache controller.
>> if the memory is device memory, that mean it is un-cacheable why we
>> still need to out sync off the PL310 buffer in writel operation?
>
> The l2 sync is to ensure that prior memory writes are visible to a DMA
> master that gets triggered by the writel.
>
> If your device is not a DMA master, or the operation is unrelated to
> DMA, you can use writel_relaxed().

Thanks for your kind explanation.