Re: [PATCH v2] soc: amlogic: clk-measure: Optimize measurement accuracy

[Martin Blumenstingl <martin.blumenstingl@googlemail.com>]

On Tue, Jul 22, 2025 at 8:09 AM Chuan Liu via B4 Relay
<devnull+chuan.liu.amlogic.com@kernel.org> wrote:
>
> From: Chuan Liu <chuan.liu@amlogic.com>
>
> The cycle count register has a 20-bit effective width, but the driver
> only utilizes 16 bits. This reduces the sampling window when measuring
> high-frequency clocks, resulting in (slightly) degraded measurement
> accuracy.
>
> The input clock signal path from gate (Controlled by MSR_RUN) to internal
> sampling circuit in clk-measure has a propagation delay requirement: 24
> clock cycles must elapse after mux selection before sampling.
>
> The measurement circuit employs single-edge sampling for clock frequency
> detection, resulting in a ±1 cycle count error within the measurement window.
>
> +1 cycle: 3 rising edges captured in 2-cycle measurement window.
>     __    __    __
>  __↑  |__↑  |__↑  |__
>   ^             ^
>
> -1 cycle: 2 rising edges captured in 3-cycle measurement window.
>     __    __    __
>  __↑  |__↑  |__↑  |__↑
>     ^               ^
>
> Change-Id: If367c013fe2a8d0c8f5f06888bb8f30a1e46b927
> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
and with the Change-Id (sorry, I missed that part) dropped as Neil
suggested also:
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>


Best regards,
Martin