Re: [PATCH 2/7] clk: mediatek: reset: Rename reset function - Chen-Yu Tsai

From: Chen-Yu Tsai <wenst@chromium.org>
To: Rex-BC Chen <rex-bc.chen@mediatek.com>
Cc: mturquette@baylibre.com, sboyd@kernel.org,
	matthias.bgg@gmail.com,  p.zabel@pengutronix.de,
	angelogioacchino.delregno@collabora.com,
	 chun-jie.chen@mediatek.com, yong.liang@mediatek.com,
	 runyang.chen@mediatek.com, linux-kernel@vger.kernel.org,
	 allen-kh.cheng@mediatek.com, linux-clk@vger.kernel.org,
	 linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org,
	 Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH 2/7] clk: mediatek: reset: Rename reset function
Date: Tue, 19 Apr 2022 13:57:35 +0800	[thread overview]
Message-ID: <CAGXv+5F027EsJCG4zQarcoqCR8S4tew1n1DjeqU7_+HOzmZs2Q@mail.gmail.com> (raw)
In-Reply-To: <20220418132154.7401-3-rex-bc.chen@mediatek.com>

On Mon, Apr 18, 2022 at 9:22 PM Rex-BC Chen <rex-bc.chen@mediatek.com> wrote:
>
> There are two version for clock reset register control of MediaTek SoCs.
> Since MT8183, the version 2 is adopted.
>
> To make the driver more readable,
> - Rename them to v2 for MT8183 and v1 for previous SoCs.
> - Adjust the fuinction order in reset.c.

I'm not sure that the renaming actually helps, since it is not given that
people outside of MediaTek would know which chip use which version. The
original name of "_set_clr" at least relays how the hardware works, which
coupled with the register naming in the datasheets make it quite obvious
if the hardware is using the "set/clr" variant.

On a different note, the v1 hardware, where a hardware bit represents the
state, is quite common, and there is a common reset driver that handles it.
Perhaps that could be reused instead of code duplicated?
See drivers/reset/reset-simple.c.

Thanks
ChenYu

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