From: Chen-Yu Tsai <wenst@chromium.org>
To: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Cc: "AngeloGioacchino Del Regno"
<angelogioacchino.delregno@collabora.com>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Dong Aisheng" <aisheng.dong@nxp.com>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
"Yassine Oudjana" <y.oudjana@protonmail.com>,
"Laura Nao" <laura.nao@collabora.com>,
"Nícolas F. R. A. Prado" <nfraprado@collabora.com>,
"Chia-I Wu" <olvaffe@gmail.com>,
kernel@collabora.com, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
"Stephen Boyd" <sboyd@codeaurora.org>
Subject: Re: [PATCH v2 3/5] clk: mediatek: Pass device to clk_hw_register for PLLs
Date: Thu, 9 Oct 2025 16:32:45 +0800 [thread overview]
Message-ID: <CAGXv+5G8XMRGasd2=H_obsLJ-97M-cNPDo3BJCrwhx2+GHhYcA@mail.gmail.com> (raw)
In-Reply-To: <20251008-mtk-pll-rpm-v2-3-170ed0698560@collabora.com>
On Thu, Oct 9, 2025 at 12:06 AM Nicolas Frattaroli
<nicolas.frattaroli@collabora.com> wrote:
>
> Passing the struct device pointer to clk_hw_register allows for runtime
> power management to work for the registered clock controllers. However,
> the mediatek PLL clocks do not do this.
>
> Change this by adding a struct device pointer argument to
> mtk_clk_register_pll, and fix up the only other user of it. Also add a
> new member to the struct mtk_clk_pll for the struct device pointer,
> which is set by mtk_clk_register_pll and is used by
> mtk_clk_register_pll_ops.
>
> If mtk_clk_register_pll is called with a NULL struct device pointer,
> then everything still works as expected; the clock core will simply
> treat them as previously, i.e. without runtime power management.
>
> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
next prev parent reply other threads:[~2025-10-09 8:33 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-08 16:05 [PATCH v2 0/5] MediaTek PLL Refactors and Fixes Nicolas Frattaroli
2025-10-08 16:05 ` [PATCH v2 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc Nicolas Frattaroli
2025-10-09 7:07 ` Chen-Yu Tsai
2025-10-09 8:01 ` AngeloGioacchino Del Regno
2025-10-08 16:05 ` [PATCH v2 2/5] clk: mediatek: Refactor pll registration to pass device Nicolas Frattaroli
2025-10-09 7:09 ` Chen-Yu Tsai
2025-10-09 7:19 ` Chen-Yu Tsai
2025-10-09 8:09 ` AngeloGioacchino Del Regno
2025-10-09 8:18 ` Chen-Yu Tsai
2025-10-09 8:52 ` AngeloGioacchino Del Regno
2025-10-10 20:11 ` Nicolas Frattaroli
2025-10-08 16:05 ` [PATCH v2 3/5] clk: mediatek: Pass device to clk_hw_register for PLLs Nicolas Frattaroli
2025-10-09 8:11 ` AngeloGioacchino Del Regno
2025-10-09 8:32 ` Chen-Yu Tsai [this message]
2025-10-08 16:05 ` [PATCH v2 4/5] clk: mediatek: Refactor pllfh registration to pass device Nicolas Frattaroli
2025-10-09 7:33 ` Chen-Yu Tsai
2025-10-10 20:06 ` Nicolas Frattaroli
2025-10-09 8:12 ` AngeloGioacchino Del Regno
2025-10-08 16:05 ` [PATCH v2 5/5] clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks Nicolas Frattaroli
2025-10-09 8:22 ` AngeloGioacchino Del Regno
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