* [PATCH 0/6] powervr: MT8173 GPU support
@ 2024-05-30 8:34 Chen-Yu Tsai
2024-05-30 8:35 ` [PATCH 1/6] dt-bindings: clock: mediatek: Add mt8173 mfgtop Chen-Yu Tsai
` (6 more replies)
0 siblings, 7 replies; 38+ messages in thread
From: Chen-Yu Tsai @ 2024-05-30 8:34 UTC (permalink / raw)
To: Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno
Cc: Chen-Yu Tsai, David Airlie, Daniel Vetter, dri-devel, linux-clk,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel
Hi everyone,
This series enables the PowerVR GPU found in the MT8173 SoC, found in
some Chromebooks.
This version is different from the initial powervr driver submission [1]
in that it splits out the GPU glue layer support out of the powervr
driver and into a separate clock and power domain driver. The glue code
is otherwise the same, and also the same as found in the ChromeOS
kernels, with some extra comments and macro names added where possible.
Patch 1 adds a binding for the glue layer, called mfgtop. The glue layer
contains clock and power controls for the GPU.
Patch 2 adds a driver for the glue layer.
Patch 3 adds an entry for the MT8173 GPU and 6XT series to the PowerVR
binding.
Patch 4 adds an entry for the PowerVR 6XT series GPU to the driver.
Patch 5 corrects the clock for the GPU (called MFG) power domain.
Patch 6 adds device nodes for the GPU and glue layer to the MT8173 dtsi
file.
Patch 2 and 6 depend on patch 1 to build. I suppose some common
immutable tree would be needed from the MediaTek maintainers.
The kernel driver successfully probes the hardware and loads the
"rogue_4.40.2.51_v1.fw" firmware provided by Imagination Technologies [2].
Userspace was tested with Mesa 24.0.8 from Debian Trixie rebuilt with
the powervr vulkan driver enabled. `vulkaninfo` gives some information
about the GPU (attached at the end), but running the `triangle` example
from the Sascha Willems demos [3] with -DUSE_D2D_WSI=ON as recommended [4]
failed with:
Can't find a display and a display mode!
Same program worked correctly on a BeaglePlay and displayed a color
gradient triangle. Not sure what went wrong here.
Anyway, please have a look and test.
Thanks
ChenYu
[1] https://lore.kernel.org/dri-devel/20220815165156.118212-2-sarah.walker@imgtec.com/
[2] https://gitlab.freedesktop.org/imagination/linux-firmware/-/tree/powervr
[3] https://github.com/SaschaWillems/Vulkan
[4] https://lore.kernel.org/dri-devel/f2b2671e-5acc-4dec-9c2e-3c9cd2e1f19e@imgtec.com/
Chen-Yu Tsai (6):
dt-bindings: clock: mediatek: Add mt8173 mfgtop
clk: mediatek: Add mt8173-mfgtop driver
dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU
drm/imagination: Add compatible string entry for Series6XT
arm64: dts: mediatek: mt8173: Fix MFG_ASYNC power domain clock
arm64: dts: mediatek: mt8173: Add GPU device nodes
.../clock/mediatek,mt8173-mfgtop.yaml | 71 ++++++
.../bindings/gpu/img,powervr-rogue.yaml | 24 +-
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 26 +-
drivers/clk/mediatek/Kconfig | 9 +
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8173-mfgtop.c | 240 ++++++++++++++++++
drivers/gpu/drm/imagination/pvr_drv.c | 1 +
include/dt-bindings/clock/mt8173-clk.h | 7 +
8 files changed, 374 insertions(+), 5 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml
create mode 100644 drivers/clk/mediatek/clk-mt8173-mfgtop.c
base-commit: 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
Vulkan info output:
WARNING: [Loader Message] Code 0 : terminator_CreateInstance: Received return code -3 from call to vkCreateInstance in ICD /usr/lib/aarch64-linux-gnu/libvulkan_virtio.so. Skipping this driver.
'DISPLAY' environment variable not set... skipping surface info
ERROR: [../src/panfrost/vulkan/panvk_device.c:386] Code 0 : WARNING: panvk is not a conformant vulkan implementation, pass PAN_I_WANT_A_BROKEN_VULKAN_DRIVER=1 if you know what you're doing. (VK_ERROR_INCOMPATIBLE_DRIVER)
MESA: error: No hard coded idfwdf program. Returning empty program.
MESA: error: No hard coded passthrough rta vertex shader. Returning empty shader.
MESA: error: No hard coded passthrough vertex shader. Returning empty shader.
MESA: warning: ../src/imagination/vulkan/pvr_job_context.c:71: FINISHME: Missing reset support for brn51764
MESA: warning: ../src/imagination/vulkan/pvr_job_context.c:74: FINISHME: Missing reset support for brn58839
MESA: warning: ../src/imagination/vulkan/pvr_border.c:104: FINISHME: Devices without tpu_border_colour_enhanced require entries for compressed formats to be stored in the table pre-compressed.
==========
VULKANINFO
==========
Vulkan Instance Version: 1.3.280
Instance Extensions: count = 23
===============================
VK_EXT_acquire_drm_display : extension revision 1
VK_EXT_acquire_xlib_display : extension revision 1
VK_EXT_debug_report : extension revision 10
VK_EXT_debug_utils : extension revision 2
VK_EXT_direct_mode_display : extension revision 1
VK_EXT_display_surface_counter : extension revision 1
VK_EXT_surface_maintenance1 : extension revision 1
VK_EXT_swapchain_colorspace : extension revision 4
VK_KHR_device_group_creation : extension revision 1
VK_KHR_display : extension revision 23
VK_KHR_external_fence_capabilities : extension revision 1
VK_KHR_external_memory_capabilities : extension revision 1
VK_KHR_external_semaphore_capabilities : extension revision 1
VK_KHR_get_display_properties2 : extension revision 1
VK_KHR_get_physical_device_properties2 : extension revision 2
VK_KHR_get_surface_capabilities2 : extension revision 1
VK_KHR_portability_enumeration : extension revision 1
VK_KHR_surface : extension revision 25
VK_KHR_surface_protected_capabilities : extension revision 1
VK_KHR_wayland_surface : extension revision 6
VK_KHR_xcb_surface : extension revision 6
VK_KHR_xlib_surface : extension revision 6
VK_LUNARG_direct_driver_loading : extension revision 1
Layers: count = 2
=================
VK_LAYER_MESA_device_select (Linux device selection layer) Vulkan version 1.3.211, layer version 1:
Layer Extensions: count = 0
Devices: count = 2
GPU id = 0 (Imagination PowerVR Rogue GX6250)
Layer-Device Extensions: count = 0
GPU id = 1 (llvmpipe (LLVM 17.0.6, 128 bits))
Layer-Device Extensions: count = 0
VK_LAYER_MESA_overlay (Mesa Overlay layer) Vulkan version 1.3.211, layer version 1:
Layer Extensions: count = 0
Devices: count = 2
GPU id = 0 (Imagination PowerVR Rogue GX6250)
Layer-Device Extensions: count = 0
GPU id = 1 (llvmpipe (LLVM 17.0.6, 128 bits))
Layer-Device Extensions: count = 0
Device Properties and Extensions:
=================================
GPU0:
VkPhysicalDeviceProperties:
---------------------------
apiVersion = 1.0.274 (4194578)
driverVersion = 24.0.8 (100663304)
vendorID = 0x1010
deviceID = 0x6250
deviceType = PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
deviceName = Imagination PowerVR Rogue GX6250
pipelineCacheUUID = 6ddf30eb-d118-41f1-455f-580ae751c27b
VkPhysicalDeviceLimits:
-----------------------
maxImageDimension1D = 8192
maxImageDimension2D = 8192
maxImageDimension3D = 2048
maxImageDimensionCube = 8192
maxImageArrayLayers = 2048
maxTexelBufferElements = 65536
maxUniformBufferRange = 134217728
maxStorageBufferRange = 134217728
maxPushConstantsSize = 256
maxMemoryAllocationCount = 4294967295
maxSamplerAllocationCount = 4294967295
bufferImageGranularity = 0x00000001
sparseAddressSpaceSize = 0x4000000000
maxBoundDescriptorSets = 4
maxPerStageDescriptorSamplers = 32
maxPerStageDescriptorUniformBuffers = 64
maxPerStageDescriptorStorageBuffers = 36
maxPerStageDescriptorSampledImages = 48
maxPerStageDescriptorStorageImages = 8
maxPerStageDescriptorInputAttachments = 8
maxPerStageResources = 224
maxDescriptorSetSamplers = 256
maxDescriptorSetUniformBuffers = 256
maxDescriptorSetUniformBuffersDynamic = 8
maxDescriptorSetStorageBuffers = 256
maxDescriptorSetStorageBuffersDynamic = 8
maxDescriptorSetSampledImages = 256
maxDescriptorSetStorageImages = 256
maxDescriptorSetInputAttachments = 256
maxVertexInputAttributes = 16
maxVertexInputBindings = 16
maxVertexInputAttributeOffset = 65535
maxVertexInputBindingStride = 2147483648
maxVertexOutputComponents = 128
maxTessellationGenerationLevel = 0
maxTessellationPatchSize = 0
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maxTessellationControlPerVertexOutputComponents = 0
maxTessellationControlPerPatchOutputComponents = 0
maxTessellationControlTotalOutputComponents = 0
maxTessellationEvaluationInputComponents = 0
maxTessellationEvaluationOutputComponents = 0
maxGeometryShaderInvocations = 0
maxGeometryInputComponents = 0
maxGeometryOutputComponents = 0
maxGeometryOutputVertices = 0
maxGeometryTotalOutputComponents = 0
maxFragmentInputComponents = 128
maxFragmentOutputAttachments = 8
maxFragmentDualSrcAttachments = 0
maxFragmentCombinedOutputResources = 52
maxComputeSharedMemorySize = 16384
maxComputeWorkGroupCount: count = 3
65536
65536
65536
maxComputeWorkGroupInvocations = 512
maxComputeWorkGroupSize: count = 3
512
512
64
subPixelPrecisionBits = 8
subTexelPrecisionBits = 8
mipmapPrecisionBits = 8
maxDrawIndexedIndexValue = 4294967295
maxDrawIndirectCount = 2147483648
maxSamplerLodBias = 16
maxSamplerAnisotropy = 1
maxViewports = 1
maxViewportDimensions: count = 2
8192
8192
viewportBoundsRange: count = 2
-16384
16384
viewportSubPixelBits = 0
minMemoryMapAlignment = 64
minTexelBufferOffsetAlignment = 0x00000010
minUniformBufferOffsetAlignment = 0x00000004
minStorageBufferOffsetAlignment = 0x00000004
minTexelOffset = -8
maxTexelOffset = 7
minTexelGatherOffset = -8
maxTexelGatherOffset = 7
minInterpolationOffset = -0.5
maxInterpolationOffset = 0.5
subPixelInterpolationOffsetBits = 4
maxFramebufferWidth = 8192
maxFramebufferHeight = 8192
maxFramebufferLayers = 2048
framebufferColorSampleCounts: count = 4
SAMPLE_COUNT_1_BIT
SAMPLE_COUNT_2_BIT
SAMPLE_COUNT_4_BIT
SAMPLE_COUNT_8_BIT
framebufferDepthSampleCounts: count = 4
SAMPLE_COUNT_1_BIT
SAMPLE_COUNT_2_BIT
SAMPLE_COUNT_4_BIT
SAMPLE_COUNT_8_BIT
framebufferStencilSampleCounts: count = 4
SAMPLE_COUNT_1_BIT
SAMPLE_COUNT_2_BIT
SAMPLE_COUNT_4_BIT
SAMPLE_COUNT_8_BIT
framebufferNoAttachmentsSampleCounts: count = 4
SAMPLE_COUNT_1_BIT
SAMPLE_COUNT_2_BIT
SAMPLE_COUNT_4_BIT
SAMPLE_COUNT_8_BIT
maxColorAttachments = 8
sampledImageColorSampleCounts: count = 4
SAMPLE_COUNT_1_BIT
SAMPLE_COUNT_2_BIT
SAMPLE_COUNT_4_BIT
SAMPLE_COUNT_8_BIT
sampledImageIntegerSampleCounts: count = 4
SAMPLE_COUNT_1_BIT
SAMPLE_COUNT_2_BIT
SAMPLE_COUNT_4_BIT
SAMPLE_COUNT_8_BIT
sampledImageDepthSampleCounts: count = 4
SAMPLE_COUNT_1_BIT
SAMPLE_COUNT_2_BIT
SAMPLE_COUNT_4_BIT
SAMPLE_COUNT_8_BIT
sampledImageStencilSampleCounts: count = 4
SAMPLE_COUNT_1_BIT
SAMPLE_COUNT_2_BIT
SAMPLE_COUNT_4_BIT
SAMPLE_COUNT_8_BIT
storageImageSampleCounts: count = 4
SAMPLE_COUNT_1_BIT
SAMPLE_COUNT_2_BIT
SAMPLE_COUNT_4_BIT
SAMPLE_COUNT_8_BIT
maxSampleMaskWords = 1
timestampComputeAndGraphics = false
timestampPeriod = 0
maxClipDistances = 8
maxCullDistances = 8
maxCombinedClipAndCullDistances = 8
discreteQueuePriorities = 2
pointSizeRange: count = 2
1
511
lineWidthRange: count = 2
0.0625
16
pointSizeGranularity = 0.0625
lineWidthGranularity = 0.0625
strictLines = false
standardSampleLocations = true
optimalBufferCopyOffsetAlignment = 0x00000004
optimalBufferCopyRowPitchAlignment = 0x00000004
nonCoherentAtomSize = 0x00000001
VkPhysicalDeviceSparseProperties:
---------------------------------
residencyStandard2DBlockShape = false
residencyStandard2DMultisampleBlockShape = false
residencyStandard3DBlockShape = false
residencyAlignedMipSize = false
residencyNonResidentStrict = false
VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT:
--------------------------------------------------
storageTexelBufferOffsetAlignmentBytes = 0x00000010
storageTexelBufferOffsetSingleTexelAlignment = true
uniformTexelBufferOffsetAlignmentBytes = 0x00000010
uniformTexelBufferOffsetSingleTexelAlignment = false
VkPhysicalDeviceTimelineSemaphorePropertiesKHR:
-----------------------------------------------
maxTimelineSemaphoreValueDifference = 18446744073709551615
Device Extensions: count = 20
VK_EXT_external_memory_dma_buf : extension revision 1
VK_EXT_host_query_reset : extension revision 1
VK_EXT_private_data : extension revision 1
VK_EXT_scalar_block_layout : extension revision 1
VK_EXT_texel_buffer_alignment : extension revision 1
VK_EXT_tooling_info : extension revision 1
VK_KHR_bind_memory2 : extension revision 1
VK_KHR_copy_commands2 : extension revision 1
VK_KHR_external_fence : extension revision 1
VK_KHR_external_fence_fd : extension revision 1
VK_KHR_external_memory : extension revision 1
VK_KHR_external_memory_fd : extension revision 1
VK_KHR_external_semaphore : extension revision 1
VK_KHR_external_semaphore_fd : extension revision 1
VK_KHR_format_feature_flags2 : extension revision 2
VK_KHR_get_memory_requirements2 : extension revision 1
VK_KHR_image_format_list : extension revision 1
VK_KHR_swapchain : extension revision 70
VK_KHR_timeline_semaphore : extension revision 2
VK_KHR_uniform_buffer_standard_layout : extension revision 1
VkQueueFamilyProperties:
========================
queueProperties[0]:
-------------------
minImageTransferGranularity = (1,1,1)
queueCount = 2
queueFlags = QUEUE_GRAPHICS_BIT | QUEUE_COMPUTE_BIT | QUEUE_TRANSFER_BIT
timestampValidBits = 0
present support = false
VkPhysicalDeviceMemoryProperties:
=================================
memoryHeaps: count = 1
memoryHeaps[0]:
size = 1752969216 (0x687c3000) (1.63 GiB)
flags: count = 1
MEMORY_HEAP_DEVICE_LOCAL_BIT
memoryTypes: count = 1
memoryTypes[0]:
heapIndex = 0
propertyFlags = 0x0007: count = 3
MEMORY_PROPERTY_DEVICE_LOCAL_BIT
MEMORY_PROPERTY_HOST_VISIBLE_BIT
MEMORY_PROPERTY_HOST_COHERENT_BIT
usable for:
IMAGE_TILING_OPTIMAL:
color images
FORMAT_D16_UNORM
FORMAT_D32_SFLOAT
FORMAT_S8_UINT
FORMAT_D24_UNORM_S8_UINT
(non-sparse)
IMAGE_TILING_LINEAR:
color images
(non-sparse)
VkPhysicalDeviceFeatures:
=========================
robustBufferAccess = true
fullDrawIndexUint32 = true
imageCubeArray = true
independentBlend = false
geometryShader = false
tessellationShader = false
sampleRateShading = true
dualSrcBlend = false
logicOp = false
multiDrawIndirect = true
drawIndirectFirstInstance = true
depthClamp = true
depthBiasClamp = true
fillModeNonSolid = false
depthBounds = false
wideLines = true
largePoints = true
alphaToOne = false
multiViewport = false
samplerAnisotropy = false
textureCompressionETC2 = true
textureCompressionASTC_LDR = false
textureCompressionBC = false
occlusionQueryPrecise = false
pipelineStatisticsQuery = false
vertexPipelineStoresAndAtomics = true
fragmentStoresAndAtomics = true
shaderTessellationAndGeometryPointSize = false
shaderImageGatherExtended = false
shaderStorageImageExtendedFormats = true
shaderStorageImageMultisample = false
shaderStorageImageReadWithoutFormat = true
shaderStorageImageWriteWithoutFormat = false
shaderUniformBufferArrayDynamicIndexing = true
shaderSampledImageArrayDynamicIndexing = true
shaderStorageBufferArrayDynamicIndexing = true
shaderStorageImageArrayDynamicIndexing = true
shaderClipDistance = false
shaderCullDistance = false
shaderFloat64 = false
shaderInt64 = true
shaderInt16 = true
shaderResourceResidency = false
shaderResourceMinLod = false
sparseBinding = false
sparseResidencyBuffer = false
sparseResidencyImage2D = false
sparseResidencyImage3D = false
sparseResidency2Samples = false
sparseResidency4Samples = false
sparseResidency8Samples = false
sparseResidency16Samples = false
sparseResidencyAliased = false
variableMultisampleRate = false
inheritedQueries = false
VkPhysicalDeviceHostQueryResetFeaturesEXT:
------------------------------------------
hostQueryReset = true
VkPhysicalDevicePrivateDataFeaturesEXT:
---------------------------------------
privateData = true
VkPhysicalDeviceScalarBlockLayoutFeaturesEXT:
---------------------------------------------
scalarBlockLayout = true
VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT:
------------------------------------------------
texelBufferAlignment = true
VkPhysicalDeviceTimelineSemaphoreFeaturesKHR:
---------------------------------------------
timelineSemaphore = true
VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR:
-------------------------------------------------------
uniformBufferStandardLayout = true
GPU1:
VkPhysicalDeviceProperties:
---------------------------
apiVersion = 1.3.274 (4206866)
driverVersion = 0.0.1 (1)
vendorID = 0x10005
deviceID = 0x0000
deviceType = PHYSICAL_DEVICE_TYPE_CPU
deviceName = llvmpipe (LLVM 17.0.6, 128 bits)
pipelineCacheUUID = 32342e30-2e38-2d31-2b70-316161616161
VkPhysicalDeviceLimits:
-----------------------
maxImageDimension1D = 16384
maxImageDimension2D = 16384
maxImageDimension3D = 4096
maxImageDimensionCube = 32768
maxImageArrayLayers = 2048
maxTexelBufferElements = 134217728
maxUniformBufferRange = 65536
maxStorageBufferRange = 134217728
maxPushConstantsSize = 256
maxMemoryAllocationCount = 4294967295
maxSamplerAllocationCount = 32768
bufferImageGranularity = 0x00000040
sparseAddressSpaceSize = 0x00000000
maxBoundDescriptorSets = 8
maxPerStageDescriptorSamplers = 1000000
maxPerStageDescriptorUniformBuffers = 1000000
maxPerStageDescriptorStorageBuffers = 1000000
maxPerStageDescriptorSampledImages = 1000000
maxPerStageDescriptorStorageImages = 1000000
maxPerStageDescriptorInputAttachments = 1000000
maxPerStageResources = 1000000
maxDescriptorSetSamplers = 1000000
maxDescriptorSetUniformBuffers = 1000000
maxDescriptorSetUniformBuffersDynamic = 1000000
maxDescriptorSetStorageBuffers = 1000000
maxDescriptorSetStorageBuffersDynamic = 1000000
maxDescriptorSetSampledImages = 1000000
maxDescriptorSetStorageImages = 1000000
maxDescriptorSetInputAttachments = 1000000
maxVertexInputAttributes = 32
maxVertexInputBindings = 32
maxVertexInputAttributeOffset = 2047
maxVertexInputBindingStride = 2048
maxVertexOutputComponents = 128
maxTessellationGenerationLevel = 64
maxTessellationPatchSize = 32
maxTessellationControlPerVertexInputComponents = 128
maxTessellationControlPerVertexOutputComponents = 128
maxTessellationControlPerPatchOutputComponents = 128
maxTessellationControlTotalOutputComponents = 4096
maxTessellationEvaluationInputComponents = 128
maxTessellationEvaluationOutputComponents = 128
maxGeometryShaderInvocations = 32
maxGeometryInputComponents = 64
maxGeometryOutputComponents = 128
maxGeometryOutputVertices = 1024
maxGeometryTotalOutputComponents = 1024
maxFragmentInputComponents = 128
maxFragmentOutputAttachments = 8
maxFragmentDualSrcAttachments = 2
maxFragmentCombinedOutputResources = 104
maxComputeSharedMemorySize = 32768
maxComputeWorkGroupCount: count = 3
65535
65535
65535
maxComputeWorkGroupInvocations = 1024
maxComputeWorkGroupSize: count = 3
1024
1024
1024
subPixelPrecisionBits = 8
subTexelPrecisionBits = 8
mipmapPrecisionBits = 4
maxDrawIndexedIndexValue = 4294967295
maxDrawIndirectCount = 4294967295
maxSamplerLodBias = 16
maxSamplerAnisotropy = 16
maxViewports = 16
maxViewportDimensions: count = 2
16384
16384
viewportBoundsRange: count = 2
-32768
32768
viewportSubPixelBits = 0
minMemoryMapAlignment = 64
minTexelBufferOffsetAlignment = 0x00000010
minUniformBufferOffsetAlignment = 0x00000010
minStorageBufferOffsetAlignment = 0x00000010
minTexelOffset = -32
maxTexelOffset = 31
minTexelGatherOffset = -32
maxTexelGatherOffset = 31
minInterpolationOffset = -2
maxInterpolationOffset = 2
subPixelInterpolationOffsetBits = 8
maxFramebufferWidth = 16384
maxFramebufferHeight = 16384
maxFramebufferLayers = 2048
framebufferColorSampleCounts: count = 2
SAMPLE_COUNT_1_BIT
SAMPLE_COUNT_4_BIT
framebufferDepthSampleCounts: count = 2
SAMPLE_COUNT_1_BIT
SAMPLE_COUNT_4_BIT
framebufferStencilSampleCounts: count = 2
SAMPLE_COUNT_1_BIT
SAMPLE_COUNT_4_BIT
framebufferNoAttachmentsSampleCounts: count = 2
SAMPLE_COUNT_1_BIT
SAMPLE_COUNT_4_BIT
maxColorAttachments = 8
sampledImageColorSampleCounts: count = 2
SAMPLE_COUNT_1_BIT
SAMPLE_COUNT_4_BIT
sampledImageIntegerSampleCounts: count = 2
SAMPLE_COUNT_1_BIT
SAMPLE_COUNT_4_BIT
sampledImageDepthSampleCounts: count = 2
SAMPLE_COUNT_1_BIT
SAMPLE_COUNT_4_BIT
sampledImageStencilSampleCounts: count = 2
SAMPLE_COUNT_1_BIT
SAMPLE_COUNT_4_BIT
storageImageSampleCounts: count = 2
SAMPLE_COUNT_1_BIT
SAMPLE_COUNT_4_BIT
maxSampleMaskWords = 1
timestampComputeAndGraphics = true
timestampPeriod = 1
maxClipDistances = 8
maxCullDistances = 8
maxCombinedClipAndCullDistances = 8
discreteQueuePriorities = 2
pointSizeRange: count = 2
0
255
lineWidthRange: count = 2
1
255
pointSizeGranularity = 0.125
lineWidthGranularity = 0.0078125
strictLines = true
standardSampleLocations = true
optimalBufferCopyOffsetAlignment = 0x00000080
optimalBufferCopyRowPitchAlignment = 0x00000080
nonCoherentAtomSize = 0x00000040
VkPhysicalDeviceSparseProperties:
---------------------------------
residencyStandard2DBlockShape = false
residencyStandard2DMultisampleBlockShape = false
residencyStandard3DBlockShape = false
residencyAlignedMipSize = false
residencyNonResidentStrict = false
VkPhysicalDeviceCustomBorderColorPropertiesEXT:
-----------------------------------------------
maxCustomBorderColorSamplers = 32768
VkPhysicalDeviceDescriptorBufferDensityMapPropertiesEXT:
--------------------------------------------------------
combinedImageSamplerDensityMapDescriptorSize = 0
VkPhysicalDeviceDescriptorBufferPropertiesEXT:
----------------------------------------------
combinedImageSamplerDescriptorSingleArray = true
bufferlessPushDescriptors = true
allowSamplerImageViewPostSubmitCreation = false
descriptorBufferOffsetAlignment = 0x00000004
maxDescriptorBufferBindings = 8
maxResourceDescriptorBufferBindings = 8
maxSamplerDescriptorBufferBindings = 8
maxEmbeddedImmutableSamplerBindings = 8
maxEmbeddedImmutableSamplers = 2032
bufferCaptureReplayDescriptorDataSize = 0
imageCaptureReplayDescriptorDataSize = 0
imageViewCaptureReplayDescriptorDataSize = 0
samplerCaptureReplayDescriptorDataSize = 0
accelerationStructureCaptureReplayDescriptorDataSize = 0
samplerDescriptorSize = 256
combinedImageSamplerDescriptorSize = 256
sampledImageDescriptorSize = 256
storageImageDescriptorSize = 256
uniformTexelBufferDescriptorSize = 256
robustUniformTexelBufferDescriptorSize = 256
storageTexelBufferDescriptorSize = 256
robustStorageTexelBufferDescriptorSize = 256
uniformBufferDescriptorSize = 256
robustUniformBufferDescriptorSize = 256
storageBufferDescriptorSize = 256
robustStorageBufferDescriptorSize = 256
inputAttachmentDescriptorSize = 256
accelerationStructureDescriptorSize = 0
maxSamplerDescriptorBufferRange = 0x08000000
maxResourceDescriptorBufferRange = 0x10000000
samplerDescriptorBufferAddressSpaceSize = 0x08000000
resourceDescriptorBufferAddressSpaceSize = 0x08000000
descriptorBufferAddressSpaceSize = 0x08000000
VkPhysicalDeviceExtendedDynamicState3PropertiesEXT:
---------------------------------------------------
dynamicPrimitiveTopologyUnrestricted = true
VkPhysicalDeviceExternalMemoryHostPropertiesEXT:
------------------------------------------------
minImportedHostPointerAlignment = 0x00001000
VkPhysicalDeviceGraphicsPipelineLibraryPropertiesEXT:
-----------------------------------------------------
graphicsPipelineLibraryFastLinking = true
graphicsPipelineLibraryIndependentInterpolationDecoration = true
VkPhysicalDeviceLineRasterizationPropertiesKHR:
-----------------------------------------------
lineSubPixelPrecisionBits = 8
VkPhysicalDeviceMaintenance5PropertiesKHR:
------------------------------------------
earlyFragmentMultisampleCoverageAfterSampleCounting = true
earlyFragmentSampleMaskTestBeforeSampleCounting = false
depthStencilSwizzleOneSupport = false
polygonModePointSize = true
nonStrictSinglePixelWideLinesUseParallelogram = false
nonStrictWideLinesUseParallelogram = false
VkPhysicalDeviceMaintenance6PropertiesKHR:
------------------------------------------
blockTexelViewCompatibleMultipleLayers = true
maxCombinedImageSamplerDescriptorCount = 3
fragmentShadingRateClampCombinerInputs = false
VkPhysicalDeviceMeshShaderPropertiesEXT:
----------------------------------------
maxTaskWorkGroupTotalCount = 4194304
maxTaskWorkGroupCount: count = 3
65536
65536
65536
maxTaskWorkGroupInvocations = 1024
maxTaskWorkGroupSize: count = 3
1024
1024
1024
maxTaskPayloadSize = 16384
maxTaskSharedMemorySize = 32768
maxTaskPayloadAndSharedMemorySize = 32768
maxMeshWorkGroupTotalCount = 4194304
maxMeshWorkGroupCount: count = 3
65536
65536
65536
maxMeshWorkGroupInvocations = 1024
maxMeshWorkGroupSize: count = 3
1024
1024
1024
maxMeshSharedMemorySize = 28672
maxMeshPayloadAndSharedMemorySize = 45056
maxMeshOutputMemorySize = 32768
maxMeshPayloadAndOutputMemorySize = 49152
maxMeshOutputComponents = 128
maxMeshOutputVertices = 256
maxMeshOutputPrimitives = 256
maxMeshOutputLayers = 8
maxMeshMultiviewViewCount = 0
meshOutputPerVertexGranularity = 1
meshOutputPerPrimitiveGranularity = 1
maxPreferredTaskWorkGroupInvocations = 64
maxPreferredMeshWorkGroupInvocations = 128
prefersLocalInvocationVertexOutput = true
prefersLocalInvocationPrimitiveOutput = true
prefersCompactVertexOutput = true
prefersCompactPrimitiveOutput = false
VkPhysicalDeviceMultiDrawPropertiesEXT:
---------------------------------------
maxMultiDrawCount = 2048
VkPhysicalDeviceNestedCommandBufferPropertiesEXT:
-------------------------------------------------
maxCommandBufferNestingLevel = 4294967295
VkPhysicalDeviceProvokingVertexPropertiesEXT:
---------------------------------------------
provokingVertexModePerPipeline = true
transformFeedbackPreservesTriangleFanProvokingVertex = true
VkPhysicalDevicePushDescriptorPropertiesKHR:
--------------------------------------------
maxPushDescriptors = 32
VkPhysicalDeviceRobustness2PropertiesEXT:
-----------------------------------------
robustStorageBufferAccessSizeAlignment = 0x00000001
robustUniformBufferAccessSizeAlignment = 0x00000001
VkPhysicalDeviceShaderObjectPropertiesEXT:
------------------------------------------
shaderBinaryUUID = 32342e30-2e38-2d31-2b70-316161616161
shaderBinaryVersion = 1
VkPhysicalDeviceTransformFeedbackPropertiesEXT:
-----------------------------------------------
maxTransformFeedbackStreams = 4
maxTransformFeedbackBuffers = 4
maxTransformFeedbackBufferSize = 0xffffffff
maxTransformFeedbackStreamDataSize = 512
maxTransformFeedbackBufferDataSize = 512
maxTransformFeedbackBufferDataStride = 512
transformFeedbackQueries = true
transformFeedbackStreamsLinesTriangles = false
transformFeedbackRasterizationStreamSelect = false
transformFeedbackDraw = true
VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT:
----------------------------------------------------
maxVertexAttribDivisor = 4294967295
VkPhysicalDeviceVulkan11Properties:
-----------------------------------
deviceUUID = 6d657361-3234-2e30-2e38-2d312b703100
driverUUID = 6c6c766d-7069-7065-5555-494400000000
deviceNodeMask = 0
deviceLUIDValid = false
subgroupSize = 4
subgroupSupportedStages: count = 4
SHADER_STAGE_FRAGMENT_BIT
SHADER_STAGE_COMPUTE_BIT
SHADER_STAGE_TASK_BIT_EXT
SHADER_STAGE_MESH_BIT_EXT
subgroupSupportedOperations: count = 7
SUBGROUP_FEATURE_BASIC_BIT
SUBGROUP_FEATURE_VOTE_BIT
SUBGROUP_FEATURE_ARITHMETIC_BIT
SUBGROUP_FEATURE_BALLOT_BIT
SUBGROUP_FEATURE_SHUFFLE_BIT
SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
SUBGROUP_FEATURE_QUAD_BIT
subgroupQuadOperationsInAllStages = false
pointClippingBehavior = POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
maxMultiviewViewCount = 6
maxMultiviewInstanceIndex = 2147483647
protectedNoFault = false
maxPerSetDescriptors = 1000000
maxMemoryAllocationSize = 0x80000000
VkPhysicalDeviceVulkan12Properties:
-----------------------------------
driverID = DRIVER_ID_MESA_LLVMPIPE
driverName = llvmpipe
driverInfo = Mesa 24.0.8-1+p1 (LLVM 17.0.6)
conformanceVersion:
major = 1
minor = 3
subminor = 1
patch = 1
denormBehaviorIndependence = SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL
roundingModeIndependence = SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL
shaderSignedZeroInfNanPreserveFloat16 = true
shaderSignedZeroInfNanPreserveFloat32 = true
shaderSignedZeroInfNanPreserveFloat64 = true
shaderDenormPreserveFloat16 = false
shaderDenormPreserveFloat32 = false
shaderDenormPreserveFloat64 = false
shaderDenormFlushToZeroFloat16 = false
shaderDenormFlushToZeroFloat32 = false
shaderDenormFlushToZeroFloat64 = false
shaderRoundingModeRTEFloat16 = true
shaderRoundingModeRTEFloat32 = true
shaderRoundingModeRTEFloat64 = true
shaderRoundingModeRTZFloat16 = false
shaderRoundingModeRTZFloat32 = false
shaderRoundingModeRTZFloat64 = false
maxUpdateAfterBindDescriptorsInAllPools = 4294967295
shaderUniformBufferArrayNonUniformIndexingNative = true
shaderSampledImageArrayNonUniformIndexingNative = true
shaderStorageBufferArrayNonUniformIndexingNative = true
shaderStorageImageArrayNonUniformIndexingNative = true
shaderInputAttachmentArrayNonUniformIndexingNative = true
robustBufferAccessUpdateAfterBind = true
quadDivergentImplicitLod = true
maxPerStageDescriptorUpdateAfterBindSamplers = 1000000
maxPerStageDescriptorUpdateAfterBindUniformBuffers = 1000000
maxPerStageDescriptorUpdateAfterBindStorageBuffers = 1000000
maxPerStageDescriptorUpdateAfterBindSampledImages = 1000000
maxPerStageDescriptorUpdateAfterBindStorageImages = 1000000
maxPerStageDescriptorUpdateAfterBindInputAttachments = 1000000
maxPerStageUpdateAfterBindResources = 1000000
maxDescriptorSetUpdateAfterBindSamplers = 1000000
maxDescriptorSetUpdateAfterBindUniformBuffers = 1000000
maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = 1000000
maxDescriptorSetUpdateAfterBindStorageBuffers = 1000000
maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = 1000000
maxDescriptorSetUpdateAfterBindSampledImages = 1000000
maxDescriptorSetUpdateAfterBindStorageImages = 1000000
maxDescriptorSetUpdateAfterBindInputAttachments = 1000000
supportedDepthResolveModes: count = 2
RESOLVE_MODE_SAMPLE_ZERO_BIT
RESOLVE_MODE_AVERAGE_BIT
supportedStencilResolveModes: count = 1
RESOLVE_MODE_SAMPLE_ZERO_BIT
independentResolveNone = false
independentResolve = false
filterMinmaxSingleComponentFormats = true
filterMinmaxImageComponentMapping = true
maxTimelineSemaphoreValueDifference = 18446744073709551615
framebufferIntegerColorSampleCounts: count = 1
SAMPLE_COUNT_1_BIT
VkPhysicalDeviceVulkan13Properties:
-----------------------------------
minSubgroupSize = 4
maxSubgroupSize = 4
maxComputeWorkgroupSubgroups = 32
requiredSubgroupSizeStages: count = 2
SHADER_STAGE_FRAGMENT_BIT
SHADER_STAGE_COMPUTE_BIT
maxInlineUniformBlockSize = 4096
maxPerStageDescriptorInlineUniformBlocks = 8
maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = 8
maxDescriptorSetInlineUniformBlocks = 8
maxDescriptorSetUpdateAfterBindInlineUniformBlocks = 8
maxInlineUniformTotalSize = 262144
integerDotProduct8BitUnsignedAccelerated = false
integerDotProduct8BitSignedAccelerated = false
integerDotProduct8BitMixedSignednessAccelerated = false
integerDotProduct4x8BitPackedUnsignedAccelerated = false
integerDotProduct4x8BitPackedSignedAccelerated = false
integerDotProduct4x8BitPackedMixedSignednessAccelerated = false
integerDotProduct16BitUnsignedAccelerated = false
integerDotProduct16BitSignedAccelerated = false
integerDotProduct16BitMixedSignednessAccelerated = false
integerDotProduct32BitUnsignedAccelerated = false
integerDotProduct32BitSignedAccelerated = false
integerDotProduct32BitMixedSignednessAccelerated = false
integerDotProduct64BitUnsignedAccelerated = false
integerDotProduct64BitSignedAccelerated = false
integerDotProduct64BitMixedSignednessAccelerated = false
integerDotProductAccumulatingSaturating8BitUnsignedAccelerated = false
integerDotProductAccumulatingSaturating8BitSignedAccelerated = false
integerDotProductAccumulatingSaturating8BitMixedSignednessAccelerated = false
integerDotProductAccumulatingSaturating4x8BitPackedUnsignedAccelerated = false
integerDotProductAccumulatingSaturating4x8BitPackedSignedAccelerated = false
integerDotProductAccumulatingSaturating4x8BitPackedMixedSignednessAccelerated = false
integerDotProductAccumulatingSaturating16BitUnsignedAccelerated = false
integerDotProductAccumulatingSaturating16BitSignedAccelerated = false
integerDotProductAccumulatingSaturating16BitMixedSignednessAccelerated = false
integerDotProductAccumulatingSaturating32BitUnsignedAccelerated = false
integerDotProductAccumulatingSaturating32BitSignedAccelerated = false
integerDotProductAccumulatingSaturating32BitMixedSignednessAccelerated = false
integerDotProductAccumulatingSaturating64BitUnsignedAccelerated = false
integerDotProductAccumulatingSaturating64BitSignedAccelerated = false
integerDotProductAccumulatingSaturating64BitMixedSignednessAccelerated = false
storageTexelBufferOffsetAlignmentBytes = 0x00000010
storageTexelBufferOffsetSingleTexelAlignment = true
uniformTexelBufferOffsetAlignmentBytes = 0x00000010
uniformTexelBufferOffsetSingleTexelAlignment = true
maxBufferSize = 0xffffffff
VkPhysicalDeviceHostImageCopyPropertiesEXT:
-------------------------------------------
copySrcLayoutCount = 23
pCopySrcLayouts: count = 23
IMAGE_LAYOUT_GENERAL
IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
IMAGE_LAYOUT_PREINITIALIZED
IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL
IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL
IMAGE_LAYOUT_DEPTH_READ_ONLY_OPTIMAL
IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL
IMAGE_LAYOUT_STENCIL_READ_ONLY_OPTIMAL
IMAGE_LAYOUT_READ_ONLY_OPTIMAL
IMAGE_LAYOUT_ATTACHMENT_OPTIMAL
IMAGE_LAYOUT_PRESENT_SRC_KHR
IMAGE_LAYOUT_VIDEO_DECODE_DST_KHR
IMAGE_LAYOUT_VIDEO_DECODE_SRC_KHR
IMAGE_LAYOUT_VIDEO_DECODE_DPB_KHR
IMAGE_LAYOUT_SHARED_PRESENT_KHR
IMAGE_LAYOUT_FRAGMENT_DENSITY_MAP_OPTIMAL_EXT
IMAGE_LAYOUT_FRAGMENT_SHADING_RATE_ATTACHMENT_OPTIMAL_KHR
copyDstLayoutCount = 23
pCopyDstLayouts: count = 23
IMAGE_LAYOUT_GENERAL
IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
IMAGE_LAYOUT_PREINITIALIZED
IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL
IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL
IMAGE_LAYOUT_DEPTH_READ_ONLY_OPTIMAL
IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL
IMAGE_LAYOUT_STENCIL_READ_ONLY_OPTIMAL
IMAGE_LAYOUT_READ_ONLY_OPTIMAL
IMAGE_LAYOUT_ATTACHMENT_OPTIMAL
IMAGE_LAYOUT_PRESENT_SRC_KHR
IMAGE_LAYOUT_VIDEO_DECODE_DST_KHR
IMAGE_LAYOUT_VIDEO_DECODE_SRC_KHR
IMAGE_LAYOUT_VIDEO_DECODE_DPB_KHR
IMAGE_LAYOUT_SHARED_PRESENT_KHR
IMAGE_LAYOUT_FRAGMENT_DENSITY_MAP_OPTIMAL_EXT
IMAGE_LAYOUT_FRAGMENT_SHADING_RATE_ATTACHMENT_OPTIMAL_KHR
optimalTilingLayoutUUID = 32342e30-2e38-2d31-2b70-316161616161
identicalMemoryTypeRequirements = false
Device Extensions: count = 124
VK_AMDX_shader_enqueue : extension revision 1
VK_ARM_rasterization_order_attachment_access : extension revision 1
VK_EXT_4444_formats : extension revision 1
VK_EXT_attachment_feedback_loop_dynamic_state : extension revision 1
VK_EXT_attachment_feedback_loop_layout : extension revision 2
VK_EXT_border_color_swizzle : extension revision 1
VK_EXT_calibrated_timestamps : extension revision 2
VK_EXT_color_write_enable : extension revision 1
VK_EXT_conditional_rendering : extension revision 2
VK_EXT_custom_border_color : extension revision 12
VK_EXT_depth_clip_control : extension revision 1
VK_EXT_depth_clip_enable : extension revision 1
VK_EXT_depth_range_unrestricted : extension revision 1
VK_EXT_descriptor_buffer : extension revision 1
VK_EXT_descriptor_indexing : extension revision 2
VK_EXT_dynamic_rendering_unused_attachments : extension revision 1
VK_EXT_extended_dynamic_state : extension revision 1
VK_EXT_extended_dynamic_state2 : extension revision 1
VK_EXT_extended_dynamic_state3 : extension revision 2
VK_EXT_external_memory_host : extension revision 1
VK_EXT_graphics_pipeline_library : extension revision 1
VK_EXT_host_image_copy : extension revision 1
VK_EXT_host_query_reset : extension revision 1
VK_EXT_image_2d_view_of_3d : extension revision 1
VK_EXT_image_robustness : extension revision 1
VK_EXT_image_sliced_view_of_3d : extension revision 1
VK_EXT_index_type_uint8 : extension revision 1
VK_EXT_inline_uniform_block : extension revision 1
VK_EXT_line_rasterization : extension revision 1
VK_EXT_load_store_op_none : extension revision 1
VK_EXT_memory_budget : extension revision 1
VK_EXT_memory_priority : extension revision 1
VK_EXT_mesh_shader : extension revision 1
VK_EXT_multi_draw : extension revision 1
VK_EXT_multisampled_render_to_single_sampled : extension revision 1
VK_EXT_mutable_descriptor_type : extension revision 1
VK_EXT_nested_command_buffer : extension revision 1
VK_EXT_non_seamless_cube_map : extension revision 1
VK_EXT_pageable_device_local_memory : extension revision 1
VK_EXT_pipeline_creation_cache_control : extension revision 3
VK_EXT_pipeline_creation_feedback : extension revision 1
VK_EXT_post_depth_coverage : extension revision 1
VK_EXT_primitive_topology_list_restart : extension revision 1
VK_EXT_primitives_generated_query : extension revision 1
VK_EXT_private_data : extension revision 1
VK_EXT_provoking_vertex : extension revision 1
VK_EXT_rasterization_order_attachment_access : extension revision 1
VK_EXT_robustness2 : extension revision 1
VK_EXT_sampler_filter_minmax : extension revision 2
VK_EXT_scalar_block_layout : extension revision 1
VK_EXT_separate_stencil_usage : extension revision 1
VK_EXT_shader_atomic_float : extension revision 1
VK_EXT_shader_atomic_float2 : extension revision 1
VK_EXT_shader_demote_to_helper_invocation : extension revision 1
VK_EXT_shader_object : extension revision 1
VK_EXT_shader_stencil_export : extension revision 1
VK_EXT_shader_subgroup_ballot : extension revision 1
VK_EXT_shader_subgroup_vote : extension revision 1
VK_EXT_shader_viewport_index_layer : extension revision 1
VK_EXT_subgroup_size_control : extension revision 2
VK_EXT_texel_buffer_alignment : extension revision 1
VK_EXT_transform_feedback : extension revision 1
VK_EXT_vertex_attribute_divisor : extension revision 3
VK_EXT_vertex_input_dynamic_state : extension revision 2
VK_EXT_ycbcr_2plane_444_formats : extension revision 1
VK_EXT_ycbcr_image_arrays : extension revision 1
VK_GOOGLE_decorate_string : extension revision 1
VK_GOOGLE_hlsl_functionality1 : extension revision 1
VK_KHR_16bit_storage : extension revision 1
VK_KHR_8bit_storage : extension revision 1
VK_KHR_bind_memory2 : extension revision 1
VK_KHR_buffer_device_address : extension revision 1
VK_KHR_copy_commands2 : extension revision 1
VK_KHR_create_renderpass2 : extension revision 1
VK_KHR_dedicated_allocation : extension revision 3
VK_KHR_depth_stencil_resolve : extension revision 1
VK_KHR_descriptor_update_template : extension revision 1
VK_KHR_device_group : extension revision 4
VK_KHR_draw_indirect_count : extension revision 1
VK_KHR_driver_properties : extension revision 1
VK_KHR_dynamic_rendering : extension revision 1
VK_KHR_external_fence : extension revision 1
VK_KHR_external_memory : extension revision 1
VK_KHR_external_memory_fd : extension revision 1
VK_KHR_external_semaphore : extension revision 1
VK_KHR_format_feature_flags2 : extension revision 2
VK_KHR_get_memory_requirements2 : extension revision 1
VK_KHR_image_format_list : extension revision 1
VK_KHR_imageless_framebuffer : extension revision 1
VK_KHR_incremental_present : extension revision 2
VK_KHR_maintenance1 : extension revision 2
VK_KHR_maintenance2 : extension revision 1
VK_KHR_maintenance3 : extension revision 1
VK_KHR_maintenance4 : extension revision 2
VK_KHR_maintenance5 : extension revision 1
VK_KHR_maintenance6 : extension revision 1
VK_KHR_map_memory2 : extension revision 1
VK_KHR_multiview : extension revision 1
VK_KHR_pipeline_library : extension revision 1
VK_KHR_push_descriptor : extension revision 2
VK_KHR_relaxed_block_layout : extension revision 1
VK_KHR_sampler_mirror_clamp_to_edge : extension revision 3
VK_KHR_sampler_ycbcr_conversion : extension revision 14
VK_KHR_separate_depth_stencil_layouts : extension revision 1
VK_KHR_shader_atomic_int64 : extension revision 1
VK_KHR_shader_clock : extension revision 1
VK_KHR_shader_draw_parameters : extension revision 1
VK_KHR_shader_float16_int8 : extension revision 1
VK_KHR_shader_float_controls : extension revision 4
VK_KHR_shader_integer_dot_product : extension revision 1
VK_KHR_shader_non_semantic_info : extension revision 1
VK_KHR_shader_subgroup_extended_types : extension revision 1
VK_KHR_shader_terminate_invocation : extension revision 1
VK_KHR_spirv_1_4 : extension revision 1
VK_KHR_storage_buffer_storage_class : extension revision 1
VK_KHR_swapchain : extension revision 70
VK_KHR_swapchain_mutable_format : extension revision 1
VK_KHR_synchronization2 : extension revision 1
VK_KHR_timeline_semaphore : extension revision 2
VK_KHR_uniform_buffer_standard_layout : extension revision 1
VK_KHR_variable_pointers : extension revision 1
VK_KHR_vulkan_memory_model : extension revision 3
VK_KHR_zero_initialize_workgroup_memory : extension revision 1
VK_NV_device_generated_commands : extension revision 3
VkQueueFamilyProperties:
========================
queueProperties[0]:
-------------------
minImageTransferGranularity = (1,1,1)
queueCount = 1
queueFlags = QUEUE_GRAPHICS_BIT | QUEUE_COMPUTE_BIT | QUEUE_TRANSFER_BIT
timestampValidBits = 64
present support = false
VkPhysicalDeviceMemoryProperties:
=================================
memoryHeaps: count = 1
memoryHeaps[0]:
size = 3505938432 (0xd0f86000) (3.27 GiB)
budget = 3505938432 (0xd0f86000) (3.27 GiB)
usage = 522092544 (0x1f1e8000) (497.91 MiB)
flags: count = 1
MEMORY_HEAP_DEVICE_LOCAL_BIT
memoryTypes: count = 1
memoryTypes[0]:
heapIndex = 0
propertyFlags = 0x000f: count = 4
MEMORY_PROPERTY_DEVICE_LOCAL_BIT
MEMORY_PROPERTY_HOST_VISIBLE_BIT
MEMORY_PROPERTY_HOST_COHERENT_BIT
MEMORY_PROPERTY_HOST_CACHED_BIT
usable for:
IMAGE_TILING_OPTIMAL:
color images
FORMAT_D16_UNORM
FORMAT_X8_D24_UNORM_PACK32
FORMAT_D32_SFLOAT
FORMAT_S8_UINT
FORMAT_D24_UNORM_S8_UINT
FORMAT_D32_SFLOAT_S8_UINT
(non-sparse)
IMAGE_TILING_LINEAR:
color images
(non-sparse)
VkPhysicalDeviceFeatures:
=========================
robustBufferAccess = true
fullDrawIndexUint32 = true
imageCubeArray = true
independentBlend = true
geometryShader = true
tessellationShader = true
sampleRateShading = true
dualSrcBlend = true
logicOp = true
multiDrawIndirect = true
drawIndirectFirstInstance = true
depthClamp = true
depthBiasClamp = true
fillModeNonSolid = true
depthBounds = false
wideLines = true
largePoints = true
alphaToOne = true
multiViewport = true
samplerAnisotropy = true
textureCompressionETC2 = false
textureCompressionASTC_LDR = false
textureCompressionBC = true
occlusionQueryPrecise = true
pipelineStatisticsQuery = true
vertexPipelineStoresAndAtomics = true
fragmentStoresAndAtomics = true
shaderTessellationAndGeometryPointSize = true
shaderImageGatherExtended = true
shaderStorageImageExtendedFormats = true
shaderStorageImageMultisample = true
shaderStorageImageReadWithoutFormat = true
shaderStorageImageWriteWithoutFormat = true
shaderUniformBufferArrayDynamicIndexing = true
shaderSampledImageArrayDynamicIndexing = true
shaderStorageBufferArrayDynamicIndexing = true
shaderStorageImageArrayDynamicIndexing = true
shaderClipDistance = true
shaderCullDistance = true
shaderFloat64 = true
shaderInt64 = true
shaderInt16 = true
shaderResourceResidency = false
shaderResourceMinLod = false
sparseBinding = false
sparseResidencyBuffer = false
sparseResidencyImage2D = false
sparseResidencyImage3D = false
sparseResidency2Samples = false
sparseResidency4Samples = false
sparseResidency8Samples = false
sparseResidency16Samples = false
sparseResidencyAliased = false
variableMultisampleRate = false
inheritedQueries = false
VkPhysicalDevice4444FormatsFeaturesEXT:
---------------------------------------
formatA4R4G4B4 = true
formatA4B4G4R4 = true
VkPhysicalDeviceAttachmentFeedbackLoopDynamicStateFeaturesEXT:
--------------------------------------------------------------
attachmentFeedbackLoopDynamicState = true
VkPhysicalDeviceAttachmentFeedbackLoopLayoutFeaturesEXT:
--------------------------------------------------------
attachmentFeedbackLoopLayout = true
VkPhysicalDeviceBorderColorSwizzleFeaturesEXT:
----------------------------------------------
borderColorSwizzle = true
borderColorSwizzleFromImage = true
VkPhysicalDeviceColorWriteEnableFeaturesEXT:
--------------------------------------------
colorWriteEnable = true
VkPhysicalDeviceConditionalRenderingFeaturesEXT:
------------------------------------------------
conditionalRendering = true
inheritedConditionalRendering = false
VkPhysicalDeviceCustomBorderColorFeaturesEXT:
---------------------------------------------
customBorderColors = true
customBorderColorWithoutFormat = true
VkPhysicalDeviceDepthClipControlFeaturesEXT:
--------------------------------------------
depthClipControl = true
VkPhysicalDeviceDepthClipEnableFeaturesEXT:
-------------------------------------------
depthClipEnable = true
VkPhysicalDeviceDescriptorBufferFeaturesEXT:
--------------------------------------------
descriptorBuffer = true
descriptorBufferCaptureReplay = false
descriptorBufferImageLayoutIgnored = true
descriptorBufferPushDescriptors = true
VkPhysicalDeviceDynamicRenderingUnusedAttachmentsFeaturesEXT:
-------------------------------------------------------------
dynamicRenderingUnusedAttachments = true
VkPhysicalDeviceExtendedDynamicState2FeaturesEXT:
-------------------------------------------------
extendedDynamicState2 = true
extendedDynamicState2LogicOp = true
extendedDynamicState2PatchControlPoints = true
VkPhysicalDeviceExtendedDynamicState3FeaturesEXT:
-------------------------------------------------
extendedDynamicState3TessellationDomainOrigin = true
extendedDynamicState3DepthClampEnable = true
extendedDynamicState3PolygonMode = true
extendedDynamicState3RasterizationSamples = true
extendedDynamicState3SampleMask = true
extendedDynamicState3AlphaToCoverageEnable = true
extendedDynamicState3AlphaToOneEnable = true
extendedDynamicState3LogicOpEnable = true
extendedDynamicState3ColorBlendEnable = true
extendedDynamicState3ColorBlendEquation = true
extendedDynamicState3ColorWriteMask = true
extendedDynamicState3RasterizationStream = false
extendedDynamicState3ConservativeRasterizationMode = false
extendedDynamicState3ExtraPrimitiveOverestimationSize = false
extendedDynamicState3DepthClipEnable = true
extendedDynamicState3SampleLocationsEnable = false
extendedDynamicState3ColorBlendAdvanced = false
extendedDynamicState3ProvokingVertexMode = true
extendedDynamicState3LineRasterizationMode = true
extendedDynamicState3LineStippleEnable = true
extendedDynamicState3DepthClipNegativeOneToOne = true
extendedDynamicState3ViewportWScalingEnable = false
extendedDynamicState3ViewportSwizzle = false
extendedDynamicState3CoverageToColorEnable = false
extendedDynamicState3CoverageToColorLocation = false
extendedDynamicState3CoverageModulationMode = false
extendedDynamicState3CoverageModulationTableEnable = false
extendedDynamicState3CoverageModulationTable = false
extendedDynamicState3CoverageReductionMode = false
extendedDynamicState3RepresentativeFragmentTestEnable = false
extendedDynamicState3ShadingRateImageEnable = false
VkPhysicalDeviceExtendedDynamicStateFeaturesEXT:
------------------------------------------------
extendedDynamicState = true
VkPhysicalDeviceGraphicsPipelineLibraryFeaturesEXT:
---------------------------------------------------
graphicsPipelineLibrary = true
VkPhysicalDeviceHostImageCopyFeaturesEXT:
-----------------------------------------
hostImageCopy = true
VkPhysicalDeviceImage2DViewOf3DFeaturesEXT:
-------------------------------------------
image2DViewOf3D = true
sampler2DViewOf3D = true
VkPhysicalDeviceImageSlicedViewOf3DFeaturesEXT:
-----------------------------------------------
imageSlicedViewOf3D = true
VkPhysicalDeviceIndexTypeUint8FeaturesKHR:
------------------------------------------
indexTypeUint8 = true
VkPhysicalDeviceLineRasterizationFeaturesKHR:
---------------------------------------------
rectangularLines = true
bresenhamLines = true
smoothLines = true
stippledRectangularLines = true
stippledBresenhamLines = true
stippledSmoothLines = true
VkPhysicalDeviceMaintenance5FeaturesKHR:
----------------------------------------
maintenance5 = true
VkPhysicalDeviceMaintenance6FeaturesKHR:
----------------------------------------
maintenance6 = true
VkPhysicalDeviceMemoryPriorityFeaturesEXT:
------------------------------------------
memoryPriority = true
VkPhysicalDeviceMeshShaderFeaturesEXT:
--------------------------------------
taskShader = true
meshShader = true
multiviewMeshShader = false
primitiveFragmentShadingRateMeshShader = false
meshShaderQueries = true
VkPhysicalDeviceMultiDrawFeaturesEXT:
-------------------------------------
multiDraw = true
VkPhysicalDeviceMultisampledRenderToSingleSampledFeaturesEXT:
-------------------------------------------------------------
multisampledRenderToSingleSampled = true
VkPhysicalDeviceMutableDescriptorTypeFeaturesEXT:
-------------------------------------------------
mutableDescriptorType = true
VkPhysicalDeviceNestedCommandBufferFeaturesEXT:
-----------------------------------------------
nestedCommandBuffer = true
nestedCommandBufferRendering = true
nestedCommandBufferSimultaneousUse = true
VkPhysicalDeviceNonSeamlessCubeMapFeaturesEXT:
----------------------------------------------
nonSeamlessCubeMap = true
VkPhysicalDevicePageableDeviceLocalMemoryFeaturesEXT:
-----------------------------------------------------
pageableDeviceLocalMemory = true
VkPhysicalDevicePrimitiveTopologyListRestartFeaturesEXT:
--------------------------------------------------------
primitiveTopologyListRestart = true
primitiveTopologyPatchListRestart = true
VkPhysicalDevicePrimitivesGeneratedQueryFeaturesEXT:
----------------------------------------------------
primitivesGeneratedQuery = true
primitivesGeneratedQueryWithRasterizerDiscard = true
primitivesGeneratedQueryWithNonZeroStreams = true
VkPhysicalDeviceProvokingVertexFeaturesEXT:
-------------------------------------------
provokingVertexLast = true
transformFeedbackPreservesProvokingVertex = true
VkPhysicalDeviceRasterizationOrderAttachmentAccessFeaturesEXT:
--------------------------------------------------------------
rasterizationOrderColorAttachmentAccess = true
rasterizationOrderDepthAttachmentAccess = true
rasterizationOrderStencilAttachmentAccess = true
VkPhysicalDeviceRobustness2FeaturesEXT:
---------------------------------------
robustBufferAccess2 = true
robustImageAccess2 = true
nullDescriptor = true
VkPhysicalDeviceShaderAtomicFloat2FeaturesEXT:
----------------------------------------------
shaderBufferFloat16Atomics = false
shaderBufferFloat16AtomicAdd = false
shaderBufferFloat16AtomicMinMax = false
shaderBufferFloat32AtomicMinMax = true
shaderBufferFloat64AtomicMinMax = false
shaderSharedFloat16Atomics = false
shaderSharedFloat16AtomicAdd = false
shaderSharedFloat16AtomicMinMax = false
shaderSharedFloat32AtomicMinMax = true
shaderSharedFloat64AtomicMinMax = false
shaderImageFloat32AtomicMinMax = true
sparseImageFloat32AtomicMinMax = false
VkPhysicalDeviceShaderAtomicFloatFeaturesEXT:
---------------------------------------------
shaderBufferFloat32Atomics = true
shaderBufferFloat32AtomicAdd = true
shaderBufferFloat64Atomics = false
shaderBufferFloat64AtomicAdd = false
shaderSharedFloat32Atomics = true
shaderSharedFloat32AtomicAdd = true
shaderSharedFloat64Atomics = false
shaderSharedFloat64AtomicAdd = false
shaderImageFloat32Atomics = true
shaderImageFloat32AtomicAdd = true
sparseImageFloat32Atomics = false
sparseImageFloat32AtomicAdd = false
VkPhysicalDeviceShaderClockFeaturesKHR:
---------------------------------------
shaderSubgroupClock = true
shaderDeviceClock = true
VkPhysicalDeviceShaderObjectFeaturesEXT:
----------------------------------------
shaderObject = true
VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT:
------------------------------------------------
texelBufferAlignment = true
VkPhysicalDeviceTransformFeedbackFeaturesEXT:
---------------------------------------------
transformFeedback = true
geometryStreams = true
VkPhysicalDeviceVertexAttributeDivisorFeaturesKHR:
--------------------------------------------------
vertexAttributeInstanceRateDivisor = true
vertexAttributeInstanceRateZeroDivisor = true
VkPhysicalDeviceVertexInputDynamicStateFeaturesEXT:
---------------------------------------------------
vertexInputDynamicState = true
VkPhysicalDeviceVulkan11Features:
---------------------------------
storageBuffer16BitAccess = true
uniformAndStorageBuffer16BitAccess = true
storagePushConstant16 = true
storageInputOutput16 = false
multiview = true
multiviewGeometryShader = true
multiviewTessellationShader = true
variablePointersStorageBuffer = true
variablePointers = true
protectedMemory = false
samplerYcbcrConversion = true
shaderDrawParameters = true
VkPhysicalDeviceVulkan12Features:
---------------------------------
samplerMirrorClampToEdge = true
drawIndirectCount = true
storageBuffer8BitAccess = true
uniformAndStorageBuffer8BitAccess = true
storagePushConstant8 = true
shaderBufferInt64Atomics = true
shaderSharedInt64Atomics = true
shaderFloat16 = true
shaderInt8 = true
descriptorIndexing = true
shaderInputAttachmentArrayDynamicIndexing = true
shaderUniformTexelBufferArrayDynamicIndexing = true
shaderStorageTexelBufferArrayDynamicIndexing = true
shaderUniformBufferArrayNonUniformIndexing = true
shaderSampledImageArrayNonUniformIndexing = true
shaderStorageBufferArrayNonUniformIndexing = true
shaderStorageImageArrayNonUniformIndexing = true
shaderInputAttachmentArrayNonUniformIndexing = true
shaderUniformTexelBufferArrayNonUniformIndexing = true
shaderStorageTexelBufferArrayNonUniformIndexing = true
descriptorBindingUniformBufferUpdateAfterBind = true
descriptorBindingSampledImageUpdateAfterBind = true
descriptorBindingStorageImageUpdateAfterBind = true
descriptorBindingStorageBufferUpdateAfterBind = true
descriptorBindingUniformTexelBufferUpdateAfterBind = true
descriptorBindingStorageTexelBufferUpdateAfterBind = true
descriptorBindingUpdateUnusedWhilePending = true
descriptorBindingPartiallyBound = true
descriptorBindingVariableDescriptorCount = true
runtimeDescriptorArray = true
samplerFilterMinmax = true
scalarBlockLayout = true
imagelessFramebuffer = true
uniformBufferStandardLayout = true
shaderSubgroupExtendedTypes = true
separateDepthStencilLayouts = true
hostQueryReset = true
timelineSemaphore = true
bufferDeviceAddress = true
bufferDeviceAddressCaptureReplay = false
bufferDeviceAddressMultiDevice = false
vulkanMemoryModel = true
vulkanMemoryModelDeviceScope = true
vulkanMemoryModelAvailabilityVisibilityChains = true
shaderOutputViewportIndex = true
shaderOutputLayer = true
subgroupBroadcastDynamicId = true
VkPhysicalDeviceVulkan13Features:
---------------------------------
robustImageAccess = true
inlineUniformBlock = true
descriptorBindingInlineUniformBlockUpdateAfterBind = true
pipelineCreationCacheControl = true
privateData = true
shaderDemoteToHelperInvocation = true
shaderTerminateInvocation = true
subgroupSizeControl = true
computeFullSubgroups = true
synchronization2 = true
textureCompressionASTC_HDR = false
shaderZeroInitializeWorkgroupMemory = true
dynamicRendering = true
shaderIntegerDotProduct = true
maintenance4 = true
VkPhysicalDeviceYcbcr2Plane444FormatsFeaturesEXT:
-------------------------------------------------
ycbcr2plane444Formats = true
VkPhysicalDeviceYcbcrImageArraysFeaturesEXT:
--------------------------------------------
ycbcrImageArrays = true
--
2.45.1.288.g0e0cd299f1-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 1/6] dt-bindings: clock: mediatek: Add mt8173 mfgtop
2024-05-30 8:34 [PATCH 0/6] powervr: MT8173 GPU support Chen-Yu Tsai
@ 2024-05-30 8:35 ` Chen-Yu Tsai
2024-05-30 15:43 ` Conor Dooley
2024-05-30 8:35 ` [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver Chen-Yu Tsai
` (5 subsequent siblings)
6 siblings, 1 reply; 38+ messages in thread
From: Chen-Yu Tsai @ 2024-05-30 8:35 UTC (permalink / raw)
To: Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno
Cc: Chen-Yu Tsai, David Airlie, Daniel Vetter, dri-devel, linux-clk,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel
The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP
in the datasheet, that contains clock gates, some power sequence signal
delays, and other unknown registers that get toggled when the GPU is
powered on.
The clock gates are exposed as clocks provided by a clock controller,
while the power sequencing bits are exposed as one singular power domain.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
.../clock/mediatek,mt8173-mfgtop.yaml | 71 +++++++++++++++++++
include/dt-bindings/clock/mt8173-clk.h | 7 ++
2 files changed, 78 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml
new file mode 100644
index 000000000000..03c3c1f8cf75
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/clock/mediatek,mt8173-mfgtop.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT8173 MFG TOP controller
+
+maintainers:
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+description:
+ The MFG TOP glue layer controls various signals going to the MFG (GPU)
+ block on the MT8173.
+
+properties:
+ compatible:
+ const: mediatek,mt8173-mfgtop
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 4
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: sys
+ - const: mem
+ - const: core
+ - const: clk26m
+
+ power-domains:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+ - '#clock-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+
+ mfgtop: clock-controller@13fff000 {
+ compatible = "mediatek,mt8173-mfgtop";
+ reg = <0x13fff000 0x1000>;
+ clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>,
+ <&topckgen CLK_TOP_MEM_MFG_IN_SEL>,
+ <&topckgen CLK_TOP_MFG_SEL>,
+ <&clk26m>;
+ clock-names = "sys", "mem", "core", "clk26m";
+ power-domains = <&spm MT8173_POWER_DOMAIN_MFG>;
+ #clock-cells = <1>;
+ #power-domain-cells = <0>;
+ };
diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h
index 3d00c98b9654..89e982f771db 100644
--- a/include/dt-bindings/clock/mt8173-clk.h
+++ b/include/dt-bindings/clock/mt8173-clk.h
@@ -243,6 +243,13 @@
#define CLK_IMG_FD 7
#define CLK_IMG_NR_CLK 8
+/* MFG_SYS */
+
+#define CLK_MFG_AXI 0
+#define CLK_MFG_MEM 1
+#define CLK_MFG_G3D 2
+#define CLK_MFG_26M 3
+
/* MM_SYS */
#define CLK_MM_SMI_COMMON 1
--
2.45.1.288.g0e0cd299f1-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver
2024-05-30 8:34 [PATCH 0/6] powervr: MT8173 GPU support Chen-Yu Tsai
2024-05-30 8:35 ` [PATCH 1/6] dt-bindings: clock: mediatek: Add mt8173 mfgtop Chen-Yu Tsai
@ 2024-05-30 8:35 ` Chen-Yu Tsai
2024-05-30 9:59 ` AngeloGioacchino Del Regno
` (3 more replies)
2024-05-30 8:35 ` [PATCH 3/6] dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU Chen-Yu Tsai
` (4 subsequent siblings)
6 siblings, 4 replies; 38+ messages in thread
From: Chen-Yu Tsai @ 2024-05-30 8:35 UTC (permalink / raw)
To: Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno
Cc: Chen-Yu Tsai, David Airlie, Daniel Vetter, dri-devel, linux-clk,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel
The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP
in the datasheet, that contains clock gates, some power sequence signal
delays, and other unknown registers that get toggled when the GPU is
powered on.
The clock gates are exposed as clocks provided by a clock controller,
while the power sequencing bits are exposed as one singular power domain.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
drivers/clk/mediatek/Kconfig | 9 +
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8173-mfgtop.c | 240 +++++++++++++++++++++++
3 files changed, 250 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8173-mfgtop.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 70a005e7e1b1..9e279c739f1c 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -500,6 +500,15 @@ config COMMON_CLK_MT8173_IMGSYS
help
This driver supports MediaTek MT8173 imgsys clocks.
+config COMMON_CLK_MT8173_MFGTOP
+ tristate "Clock and power driver for MediaTek MT8173 mfgtop"
+ depends on COMMON_CLK_MT8173
+ default COMMON_CLK_MT8173
+ select PM_GENERIC_DOMAINS
+ select PM_GENERIC_DOMAINS_OF
+ help
+ This driver supports MediaTek MT8173 mfgtop clocks and power domain.
+
config COMMON_CLK_MT8173_MMSYS
tristate "Clock driver for MediaTek MT8173 mmsys"
depends on COMMON_CLK_MT8173
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index eeccfa039896..fdd3a76e12a1 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_COMMON_CLK_MT8167_VDECSYS) += clk-mt8167-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173-apmixedsys.o clk-mt8173-infracfg.o \
clk-mt8173-pericfg.o clk-mt8173-topckgen.o
obj-$(CONFIG_COMMON_CLK_MT8173_IMGSYS) += clk-mt8173-img.o
+obj-$(CONFIG_COMMON_CLK_MT8173_MFGTOP) += clk-mt8173-mfgtop.o
obj-$(CONFIG_COMMON_CLK_MT8173_MMSYS) += clk-mt8173-mm.o
obj-$(CONFIG_COMMON_CLK_MT8173_VDECSYS) += clk-mt8173-vdecsys.o
obj-$(CONFIG_COMMON_CLK_MT8173_VENCSYS) += clk-mt8173-vencsys.o
diff --git a/drivers/clk/mediatek/clk-mt8173-mfgtop.c b/drivers/clk/mediatek/clk-mt8173-mfgtop.c
new file mode 100644
index 000000000000..85fa7a7453ed
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8173-mfgtop.c
@@ -0,0 +1,240 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024 Google LLC
+ * Author: Chen-Yu Tsai <wenst@chromium.org>
+ *
+ * Based on driver in downstream ChromeOS v5.15 kernel.
+ *
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Chiawen Lee <chiawen.lee@mediatek.com>
+ */
+
+#include <dt-bindings/clock/mt8173-clk.h>
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs mfg_cg_regs = {
+ .sta_ofs = 0x0000,
+ .clr_ofs = 0x0008,
+ .set_ofs = 0x0004,
+};
+
+#define GATE_MFG(_id, _name, _parent, _shift, _flags) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr, _flags)
+
+/* TODO: The block actually has dividers for the core and mem clocks. */
+static const struct mtk_gate mfg_clks[] = {
+ GATE_MFG(CLK_MFG_AXI, "mfg_axi", "axi_mfg_in_sel", 0, CLK_SET_RATE_PARENT),
+ GATE_MFG(CLK_MFG_MEM, "mfg_mem", "mem_mfg_in_sel", 1, CLK_SET_RATE_PARENT),
+ GATE_MFG(CLK_MFG_G3D, "mfg_g3d", "mfg_sel", 2, CLK_SET_RATE_PARENT),
+ GATE_MFG(CLK_MFG_26M, "mfg_26m", "clk26m", 3, 0),
+};
+
+static const struct mtk_clk_desc mfg_desc = {
+ .clks = mfg_clks,
+ .num_clks = ARRAY_SIZE(mfg_clks),
+};
+
+struct mt8173_mfgtop_data {
+ struct clk_hw_onecell_data *clk_data;
+ struct regmap *regmap;
+ struct generic_pm_domain genpd;
+ struct of_phandle_args parent_pd, child_pd;
+ struct clk *clk_26m;
+};
+
+static const struct of_device_id of_match_clk_mt8173_mfgtop[] = {
+ { .compatible = "mediatek,mt8173-mfgtop", .data = &mfg_desc },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_mfgtop);
+
+/* Delay count in clock cycles */
+#define MFG_ACTIVE_POWER_CON0 0x24
+ #define RST_B_DELAY_CNT GENMASK(7, 0) /* pwr_rst_b de-assert delay during power-up */
+ #define CLK_EN_DELAY_CNT GENMASK(15, 8) /* CLK_DIS deassert delay during power-up */
+ #define CLK_DIS_DELAY_CNT GENMASK(23, 16) /* CLK_DIS assert delay during power-down */
+
+#define MFG_ACTIVE_POWER_CON1 0x28
+ #define PWR_ON_S_DELAY_CNT GENMASK(7, 0) /* pwr_on_s assert delay during power-up */
+ #define ISO_DELAY_CNT GENMASK(15, 8) /* ISO assert delay during power-down */
+ #define ISOOFF_DELAY_CNT GENMASK(23, 16) /* ISO de-assert delay during power-up */
+ #define RST__DELAY_CNT GENMASK(31, 24) /* pwr_rsb_b assert delay during power-down */
+
+static int clk_mt8173_mfgtop_power_on(struct generic_pm_domain *domain)
+{
+ struct mt8173_mfgtop_data *data = container_of(domain, struct mt8173_mfgtop_data, genpd);
+
+ /* drives internal power management */
+ clk_prepare_enable(data->clk_26m);
+
+ /* Power on/off delays for various signals */
+ regmap_write(data->regmap, MFG_ACTIVE_POWER_CON0,
+ FIELD_PREP(RST_B_DELAY_CNT, 77) |
+ FIELD_PREP(CLK_EN_DELAY_CNT, 61) |
+ FIELD_PREP(CLK_DIS_DELAY_CNT, 60));
+ regmap_write(data->regmap, MFG_ACTIVE_POWER_CON1,
+ FIELD_PREP(PWR_ON_S_DELAY_CNT, 11) |
+ FIELD_PREP(ISO_DELAY_CNT, 68) |
+ FIELD_PREP(ISOOFF_DELAY_CNT, 69) |
+ FIELD_PREP(RST__DELAY_CNT, 77));
+
+ /* Magic numbers related to core switch sequence and delays */
+ regmap_write(data->regmap, 0xe0, 0x7a710184);
+ regmap_write(data->regmap, 0xe4, 0x835f6856);
+ regmap_write(data->regmap, 0xe8, 0x002b0234);
+ regmap_write(data->regmap, 0xec, 0x80000000);
+ regmap_write(data->regmap, 0xa0, 0x08000000);
+
+ return 0;
+}
+
+static int clk_mt8173_mfgtop_power_off(struct generic_pm_domain *domain)
+{
+ struct mt8173_mfgtop_data *data = container_of(domain, struct mt8173_mfgtop_data, genpd);
+
+ /* Magic numbers related to core switch sequence and delays */
+ regmap_write(data->regmap, 0xec, 0);
+
+ /* drives internal power management */
+ clk_disable_unprepare(data->clk_26m);
+
+ return 0;
+}
+
+static int clk_mt8173_mfgtop_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
+ struct mt8173_mfgtop_data *data;
+ int ret;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, data);
+
+ data->clk_data = mtk_devm_alloc_clk_data(dev, ARRAY_SIZE(mfg_clks));
+ if (!data->clk_data)
+ return -ENOMEM;
+
+ /* MTK clock gates also uses regmap */
+ data->regmap = device_node_to_regmap(node);
+ if (IS_ERR(data->regmap))
+ return dev_err_probe(dev, PTR_ERR(data->regmap), "Failed to get regmap\n");
+
+ data->child_pd.np = node;
+ data->child_pd.args_count = 0;
+ ret = of_parse_phandle_with_args(node, "power-domains", "#power-domain-cells", 0,
+ &data->parent_pd);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to parse power domain\n");
+
+ devm_pm_runtime_enable(dev);
+ /*
+ * Do a pm_runtime_resume_and_get() to workaround a possible
+ * deadlock between clk_register() and the genpd framework.
+ */
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret) {
+ dev_err_probe(dev, ret, "Failed to runtime resume device\n");
+ goto put_of_node;
+ }
+
+ ret = mtk_clk_register_gates(dev, node, mfg_clks, ARRAY_SIZE(mfg_clks),
+ data->clk_data);
+ if (ret) {
+ dev_err_probe(dev, ret, "Failed to register clock gates\n");
+ goto put_pm_runtime;
+ }
+
+ data->clk_26m = clk_hw_get_clk(data->clk_data->hws[CLK_MFG_26M], "26m");
+ if (IS_ERR(data->clk_26m)) {
+ dev_err_probe(dev, PTR_ERR(data->clk_26m), "Failed to get 26 MHz clock\n");
+ goto unregister_clks;
+ }
+
+ ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data->clk_data);
+ if (ret) {
+ dev_err_probe(dev, ret, "Failed to add clk OF provider\n");
+ goto put_26m_clk;
+ }
+
+ data->genpd.name = "mfg_apm";
+ data->genpd.power_on = clk_mt8173_mfgtop_power_on;
+ data->genpd.power_off = clk_mt8173_mfgtop_power_off;
+ ret = pm_genpd_init(&data->genpd, NULL, true);
+ if (ret) {
+ dev_err_probe(dev, ret, "Failed to add power domain\n");
+ goto del_clk_provider;
+ }
+
+ ret = of_genpd_add_provider_simple(node, &data->genpd);
+ if (ret) {
+ dev_err_probe(dev, ret, "Failed to add power domain OF provider\n");
+ goto remove_pd;
+ }
+
+ ret = of_genpd_add_subdomain(&data->parent_pd, &data->child_pd);
+ if (ret) {
+ dev_err_probe(dev, ret, "Failed to link PM domains\n");
+ goto del_pd_provider;
+ }
+
+ pm_runtime_put(dev);
+ return 0;
+
+del_pd_provider:
+ of_genpd_del_provider(node);
+remove_pd:
+ pm_genpd_remove(&data->genpd);
+del_clk_provider:
+ of_clk_del_provider(node);
+put_26m_clk:
+ clk_put(data->clk_26m);
+unregister_clks:
+ mtk_clk_unregister_gates(mfg_clks, ARRAY_SIZE(mfg_clks), data->clk_data);
+put_pm_runtime:
+ pm_runtime_put(dev);
+put_of_node:
+ of_node_put(data->parent_pd.np);
+ return ret;
+}
+
+static void clk_mt8173_mfgtop_remove(struct platform_device *pdev)
+{
+ struct mt8173_mfgtop_data *data = platform_get_drvdata(pdev);
+ struct device_node *node = pdev->dev.of_node;
+
+ of_genpd_remove_subdomain(&data->parent_pd, &data->child_pd);
+ of_genpd_del_provider(node);
+ pm_genpd_remove(&data->genpd);
+ of_clk_del_provider(node);
+ clk_put(data->clk_26m);
+ mtk_clk_unregister_gates(mfg_clks, ARRAY_SIZE(mfg_clks), data->clk_data);
+}
+
+static struct platform_driver clk_mt8173_mfgtop_drv = {
+ .probe = clk_mt8173_mfgtop_probe,
+ .remove_new = clk_mt8173_mfgtop_remove,
+ .driver = {
+ .name = "clk-mt8173-mfgtop",
+ .of_match_table = of_match_clk_mt8173_mfgtop,
+ },
+};
+module_platform_driver(clk_mt8173_mfgtop_drv);
+
+MODULE_DESCRIPTION("MediaTek MT8173 mfgtop clock driver");
+MODULE_LICENSE("GPL");
--
2.45.1.288.g0e0cd299f1-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 3/6] dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU
2024-05-30 8:34 [PATCH 0/6] powervr: MT8173 GPU support Chen-Yu Tsai
2024-05-30 8:35 ` [PATCH 1/6] dt-bindings: clock: mediatek: Add mt8173 mfgtop Chen-Yu Tsai
2024-05-30 8:35 ` [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver Chen-Yu Tsai
@ 2024-05-30 8:35 ` Chen-Yu Tsai
2024-05-30 10:03 ` AngeloGioacchino Del Regno
` (2 more replies)
2024-05-30 8:35 ` [PATCH 4/6] drm/imagination: Add compatible string entry for Series6XT Chen-Yu Tsai
` (3 subsequent siblings)
6 siblings, 3 replies; 38+ messages in thread
From: Chen-Yu Tsai @ 2024-05-30 8:35 UTC (permalink / raw)
To: Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno
Cc: Chen-Yu Tsai, David Airlie, Daniel Vetter, dri-devel, linux-clk,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel
The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is one
of the Series6XT GPUs, another sub-family of the Rogue family.
This was part of the very first few versions of the PowerVR submission,
but was later dropped. The compatible string has been updated to follow
the new naming scheme adopted for the AXE series.
In a previous iteration of the PowerVR binding submission [1], the
number of clocks required for the 6XT family was mentioned to be
always 3. This is also reflected here.
[1] https://lore.kernel.org/dri-devel/6eeccb26e09aad67fb30ffcd523c793a43c79c2a.camel@imgtec.com/
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
.../bindings/gpu/img,powervr-rogue.yaml | 24 +++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
index 256e252f8087..48aa205b66b4 100644
--- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
+++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
@@ -12,10 +12,17 @@ maintainers:
properties:
compatible:
- items:
- - enum:
- - ti,am62-gpu
- - const: img,img-axe # IMG AXE GPU model/revision is fully discoverable
+ oneOf:
+ - items:
+ - enum:
+ - mediatek,mt8173-gpu
+ # PowerVR 6XT GPU model/revision is fully discoverable
+ - const: img,powervr-6xt
+ - items:
+ - enum:
+ - ti,am62-gpu
+ # IMG AXE GPU model/revision is fully discoverable
+ - const: img,img-axe
reg:
maxItems: 1
@@ -56,6 +63,15 @@ allOf:
properties:
clocks:
maxItems: 1
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: img,powervr-6xt
+ then:
+ properties:
+ clocks:
+ minItems: 3
examples:
- |
--
2.45.1.288.g0e0cd299f1-goog
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^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 4/6] drm/imagination: Add compatible string entry for Series6XT
2024-05-30 8:34 [PATCH 0/6] powervr: MT8173 GPU support Chen-Yu Tsai
` (2 preceding siblings ...)
2024-05-30 8:35 ` [PATCH 3/6] dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU Chen-Yu Tsai
@ 2024-05-30 8:35 ` Chen-Yu Tsai
2024-05-30 10:03 ` AngeloGioacchino Del Regno
2024-05-31 11:18 ` Frank Binns
2024-05-30 8:35 ` [PATCH 5/6] arm64: dts: mediatek: mt8173: Fix MFG_ASYNC power domain clock Chen-Yu Tsai
` (2 subsequent siblings)
6 siblings, 2 replies; 38+ messages in thread
From: Chen-Yu Tsai @ 2024-05-30 8:35 UTC (permalink / raw)
To: Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno
Cc: Chen-Yu Tsai, David Airlie, Daniel Vetter, dri-devel, linux-clk,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel
The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is part
of the Series6XT, another variation of the Rogue family of GPUs.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
drivers/gpu/drm/imagination/pvr_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/imagination/pvr_drv.c b/drivers/gpu/drm/imagination/pvr_drv.c
index 5c3b2d58d766..3d1a933c8303 100644
--- a/drivers/gpu/drm/imagination/pvr_drv.c
+++ b/drivers/gpu/drm/imagination/pvr_drv.c
@@ -1475,6 +1475,7 @@ pvr_remove(struct platform_device *plat_dev)
static const struct of_device_id dt_match[] = {
{ .compatible = "img,img-axe", .data = NULL },
+ { .compatible = "img,powervr-6xt", .data = NULL },
{}
};
MODULE_DEVICE_TABLE(of, dt_match);
--
2.45.1.288.g0e0cd299f1-goog
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^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 5/6] arm64: dts: mediatek: mt8173: Fix MFG_ASYNC power domain clock
2024-05-30 8:34 [PATCH 0/6] powervr: MT8173 GPU support Chen-Yu Tsai
` (3 preceding siblings ...)
2024-05-30 8:35 ` [PATCH 4/6] drm/imagination: Add compatible string entry for Series6XT Chen-Yu Tsai
@ 2024-05-30 8:35 ` Chen-Yu Tsai
2024-05-30 10:03 ` AngeloGioacchino Del Regno
2024-05-30 8:35 ` [PATCH 6/6] arm64: dts: mediatek: mt8173: Add GPU device nodes Chen-Yu Tsai
2024-05-31 4:00 ` [PATCH 0/6] powervr: MT8173 GPU support Chen-Yu Tsai
6 siblings, 1 reply; 38+ messages in thread
From: Chen-Yu Tsai @ 2024-05-30 8:35 UTC (permalink / raw)
To: Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno
Cc: Chen-Yu Tsai, David Airlie, Daniel Vetter, dri-devel, linux-clk,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel
The MFG_ASYNC domain, which is likely associated to the whole MFG block,
currently specifies clk26m as its domain clock. This is bogus, since the
clock is an external crystal with no controls. Also, the MFG block has
a independent CLK_TOP_AXI_MFG_IN_SEL clock, which according to the block
diagram, gates access to the hardware registers. Having this one as the
domain clock makes much more sense. This also fixes access to the MFGTOP
registers.
Change the MFG_ASYNC domain clock to CLK_TOP_AXI_MFG_IN_SEL.
Fixes: 8b6562644df9 ("arm64: dts: mediatek: Add mt8173 power domain controller")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 3458be7f7f61..136b28f80cc2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -497,7 +497,7 @@ power-domain@MT8173_POWER_DOMAIN_USB {
};
mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
- clocks = <&clk26m>;
+ clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>;
clock-names = "mfg";
#address-cells = <1>;
#size-cells = <0>;
--
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^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 6/6] arm64: dts: mediatek: mt8173: Add GPU device nodes
2024-05-30 8:34 [PATCH 0/6] powervr: MT8173 GPU support Chen-Yu Tsai
` (4 preceding siblings ...)
2024-05-30 8:35 ` [PATCH 5/6] arm64: dts: mediatek: mt8173: Fix MFG_ASYNC power domain clock Chen-Yu Tsai
@ 2024-05-30 8:35 ` Chen-Yu Tsai
2024-05-30 10:04 ` AngeloGioacchino Del Regno
2024-05-31 4:00 ` [PATCH 0/6] powervr: MT8173 GPU support Chen-Yu Tsai
6 siblings, 1 reply; 38+ messages in thread
From: Chen-Yu Tsai @ 2024-05-30 8:35 UTC (permalink / raw)
To: Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno
Cc: Chen-Yu Tsai, David Airlie, Daniel Vetter, dri-devel, linux-clk,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel
The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is part
of the Series6XT, another variation of the Rogue family of GPUs.
On top of the GPU is a glue layer that handles some clock and power
signals.
Add device nodes for both.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 136b28f80cc2..3d7b9cc20a16 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -993,6 +993,30 @@ u2port1: usb-phy@11291000 {
};
};
+ gpu: gpu@13000000 {
+ compatible = "mediatek,mt8173-gpu", "img,powervr-6xt";
+ reg = <0 0x13000000 0 0x10000>;
+ interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mfgtop CLK_MFG_G3D>,
+ <&mfgtop CLK_MFG_MEM>,
+ <&mfgtop CLK_MFG_AXI>;
+ clock-names = "core", "mem", "sys";
+ power-domains = <&mfgtop>;
+ };
+
+ mfgtop: clock-controller@13fff000 {
+ compatible = "mediatek,mt8173-mfgtop";
+ reg = <0 0x13fff000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>,
+ <&topckgen CLK_TOP_MEM_MFG_IN_SEL>,
+ <&topckgen CLK_TOP_MFG_SEL>,
+ <&clk26m>;
+ clock-names = "sys", "mem", "core", "clk26m";
+ power-domains = <&spm MT8173_POWER_DOMAIN_MFG>;
+ #clock-cells = <1>;
+ #power-domain-cells = <0>;
+ };
+
mmsys: syscon@14000000 {
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
--
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^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver
2024-05-30 8:35 ` [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver Chen-Yu Tsai
@ 2024-05-30 9:59 ` AngeloGioacchino Del Regno
2024-05-30 10:16 ` Chen-Yu Tsai
2024-05-30 16:15 ` kernel test robot
` (2 subsequent siblings)
3 siblings, 1 reply; 38+ messages in thread
From: AngeloGioacchino Del Regno @ 2024-05-30 9:59 UTC (permalink / raw)
To: Chen-Yu Tsai, Frank Binns, Matt Coster, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: David Airlie, Daniel Vetter, dri-devel, linux-clk, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel
Il 30/05/24 10:35, Chen-Yu Tsai ha scritto:
> The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP
> in the datasheet, that contains clock gates, some power sequence signal
> delays, and other unknown registers that get toggled when the GPU is
> powered on.
>
> The clock gates are exposed as clocks provided by a clock controller,
> while the power sequencing bits are exposed as one singular power domain.
>
> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> ---
> drivers/clk/mediatek/Kconfig | 9 +
> drivers/clk/mediatek/Makefile | 1 +
> drivers/clk/mediatek/clk-mt8173-mfgtop.c | 240 +++++++++++++++++++++++
> 3 files changed, 250 insertions(+)
> create mode 100644 drivers/clk/mediatek/clk-mt8173-mfgtop.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 70a005e7e1b1..9e279c739f1c 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -500,6 +500,15 @@ config COMMON_CLK_MT8173_IMGSYS
> help
> This driver supports MediaTek MT8173 imgsys clocks.
>
> +config COMMON_CLK_MT8173_MFGTOP
> + tristate "Clock and power driver for MediaTek MT8173 mfgtop"
> + depends on COMMON_CLK_MT8173
> + default COMMON_CLK_MT8173
> + select PM_GENERIC_DOMAINS
> + select PM_GENERIC_DOMAINS_OF
> + help
> + This driver supports MediaTek MT8173 mfgtop clocks and power domain.
> +
> config COMMON_CLK_MT8173_MMSYS
> tristate "Clock driver for MediaTek MT8173 mmsys"
> depends on COMMON_CLK_MT8173
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index eeccfa039896..fdd3a76e12a1 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -77,6 +77,7 @@ obj-$(CONFIG_COMMON_CLK_MT8167_VDECSYS) += clk-mt8167-vdec.o
> obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173-apmixedsys.o clk-mt8173-infracfg.o \
> clk-mt8173-pericfg.o clk-mt8173-topckgen.o
> obj-$(CONFIG_COMMON_CLK_MT8173_IMGSYS) += clk-mt8173-img.o
> +obj-$(CONFIG_COMMON_CLK_MT8173_MFGTOP) += clk-mt8173-mfgtop.o
> obj-$(CONFIG_COMMON_CLK_MT8173_MMSYS) += clk-mt8173-mm.o
> obj-$(CONFIG_COMMON_CLK_MT8173_VDECSYS) += clk-mt8173-vdecsys.o
> obj-$(CONFIG_COMMON_CLK_MT8173_VENCSYS) += clk-mt8173-vencsys.o
> diff --git a/drivers/clk/mediatek/clk-mt8173-mfgtop.c b/drivers/clk/mediatek/clk-mt8173-mfgtop.c
> new file mode 100644
> index 000000000000..85fa7a7453ed
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8173-mfgtop.c
> @@ -0,0 +1,240 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2024 Google LLC
> + * Author: Chen-Yu Tsai <wenst@chromium.org>
> + *
> + * Based on driver in downstream ChromeOS v5.15 kernel.
> + *
> + * Copyright (c) 2014 MediaTek Inc.
> + * Author: Chiawen Lee <chiawen.lee@mediatek.com>
> + */
> +
> +#include <dt-bindings/clock/mt8173-clk.h>
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs mfg_cg_regs = {
> + .sta_ofs = 0x0000,
> + .clr_ofs = 0x0008,
> + .set_ofs = 0x0004,
> +};
> +
> +#define GATE_MFG(_id, _name, _parent, _shift, _flags) \
> + GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr, _flags)
Extra tabulation: please fix
> +
> +/* TODO: The block actually has dividers for the core and mem clocks. */
> +static const struct mtk_gate mfg_clks[] = {
> + GATE_MFG(CLK_MFG_AXI, "mfg_axi", "axi_mfg_in_sel", 0, CLK_SET_RATE_PARENT),
> + GATE_MFG(CLK_MFG_MEM, "mfg_mem", "mem_mfg_in_sel", 1, CLK_SET_RATE_PARENT),
> + GATE_MFG(CLK_MFG_G3D, "mfg_g3d", "mfg_sel", 2, CLK_SET_RATE_PARENT),
> + GATE_MFG(CLK_MFG_26M, "mfg_26m", "clk26m", 3, 0),
> +};
> +
> +static const struct mtk_clk_desc mfg_desc = {
> + .clks = mfg_clks,
> + .num_clks = ARRAY_SIZE(mfg_clks),
> +};
> +
> +struct mt8173_mfgtop_data {
> + struct clk_hw_onecell_data *clk_data;
> + struct regmap *regmap;
> + struct generic_pm_domain genpd;
> + struct of_phandle_args parent_pd, child_pd;
> + struct clk *clk_26m;
> +};
> +
> +static const struct of_device_id of_match_clk_mt8173_mfgtop[] = {
> + { .compatible = "mediatek,mt8173-mfgtop", .data = &mfg_desc },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_mfgtop);
Please move of_match_clk_mt8173_mfgtop before clk_mt8173_mfgtop_drv for consistency
with all the other clock drivers.
> +
> +/* Delay count in clock cycles */
> +#define MFG_ACTIVE_POWER_CON0 0x24
> + #define RST_B_DELAY_CNT GENMASK(7, 0) /* pwr_rst_b de-assert delay during power-up */
> + #define CLK_EN_DELAY_CNT GENMASK(15, 8) /* CLK_DIS deassert delay during power-up */
> + #define CLK_DIS_DELAY_CNT GENMASK(23, 16) /* CLK_DIS assert delay during power-down */
The reason why I had EVT_FORCE_ABORT and ACTIVE_PWRCTL_EN in my driver is to
document that we're keeping the event force abort disabled and, more importantly,
we are keeping the "active power control" feature disabled.
Please, add those two - or at least the ACTIVE_PWRCTL_EN - to keep that documented,
or this information will be lost for sure.
If in the future the ACTIVE_PWRCTL feature will become usable, it's going to be
just a 30 seconds change, as the info is already there.
> +
> +#define MFG_ACTIVE_POWER_CON1 0x28
> + #define PWR_ON_S_DELAY_CNT GENMASK(7, 0) /* pwr_on_s assert delay during power-up */
> + #define ISO_DELAY_CNT GENMASK(15, 8) /* ISO assert delay during power-down */
> + #define ISOOFF_DELAY_CNT GENMASK(23, 16) /* ISO de-assert delay during power-up */
> + #define RST__DELAY_CNT GENMASK(31, 24) /* pwr_rsb_b assert delay during power-down */
> +
> +static int clk_mt8173_mfgtop_power_on(struct generic_pm_domain *domain)
> +{
> + struct mt8173_mfgtop_data *data = container_of(domain, struct mt8173_mfgtop_data, genpd);
> +
> + /* drives internal power management */
> + clk_prepare_enable(data->clk_26m);
> +
> + /* Power on/off delays for various signals */
> + regmap_write(data->regmap, MFG_ACTIVE_POWER_CON0,
> + FIELD_PREP(RST_B_DELAY_CNT, 77) |
> + FIELD_PREP(CLK_EN_DELAY_CNT, 61) |
> + FIELD_PREP(CLK_DIS_DELAY_CNT, 60));
I get that this is kinda odd to read, but still...
FIELD_PREP(CLK_DIS_DELAY_CNT, 60) |
FIELD_PREP(ACTIVE_PWRCTL_EN, 0));
...please :-)
> + regmap_write(data->regmap, MFG_ACTIVE_POWER_CON1,
> + FIELD_PREP(PWR_ON_S_DELAY_CNT, 11) |
> + FIELD_PREP(ISO_DELAY_CNT, 68) |
> + FIELD_PREP(ISOOFF_DELAY_CNT, 69) |
> + FIELD_PREP(RST__DELAY_CNT, 77));
> +
> + /* Magic numbers related to core switch sequence and delays */
> + regmap_write(data->regmap, 0xe0, 0x7a710184);
> + regmap_write(data->regmap, 0xe4, 0x835f6856);
> + regmap_write(data->regmap, 0xe8, 0x002b0234);
> + regmap_write(data->regmap, 0xec, 0x80000000);
> + regmap_write(data->regmap, 0xa0, 0x08000000);
Is there any way to retrieve information about what those registers are?
> +
> + return 0;
> +}
> +
> +static int clk_mt8173_mfgtop_power_off(struct generic_pm_domain *domain)
> +{
> + struct mt8173_mfgtop_data *data = container_of(domain, struct mt8173_mfgtop_data, genpd);
> +
> + /* Magic numbers related to core switch sequence and delays */
> + regmap_write(data->regmap, 0xec, 0);
> +
> + /* drives internal power management */
> + clk_disable_unprepare(data->clk_26m);
> +
> + return 0;
> +}
> +
> +static int clk_mt8173_mfgtop_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *node = dev->of_node;
> + struct mt8173_mfgtop_data *data;
> + int ret;
> +
> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, data);
> +
> + data->clk_data = mtk_devm_alloc_clk_data(dev, ARRAY_SIZE(mfg_clks));
> + if (!data->clk_data)
> + return -ENOMEM;
> +
> + /* MTK clock gates also uses regmap */
> + data->regmap = device_node_to_regmap(node);
> + if (IS_ERR(data->regmap))
> + return dev_err_probe(dev, PTR_ERR(data->regmap), "Failed to get regmap\n");
> +
> + data->child_pd.np = node;
> + data->child_pd.args_count = 0;
> + ret = of_parse_phandle_with_args(node, "power-domains", "#power-domain-cells", 0,
> + &data->parent_pd);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to parse power domain\n");
> +
> + devm_pm_runtime_enable(dev);
> + /*
> + * Do a pm_runtime_resume_and_get() to workaround a possible
> + * deadlock between clk_register() and the genpd framework.
> + */
> + ret = pm_runtime_resume_and_get(dev);
> + if (ret) {
> + dev_err_probe(dev, ret, "Failed to runtime resume device\n");
> + goto put_of_node;
> + }
> +
> + ret = mtk_clk_register_gates(dev, node, mfg_clks, ARRAY_SIZE(mfg_clks),
> + data->clk_data);
> + if (ret) {
> + dev_err_probe(dev, ret, "Failed to register clock gates\n");
> + goto put_pm_runtime;
> + }
> +
> + data->clk_26m = clk_hw_get_clk(data->clk_data->hws[CLK_MFG_26M], "26m");
> + if (IS_ERR(data->clk_26m)) {
> + dev_err_probe(dev, PTR_ERR(data->clk_26m), "Failed to get 26 MHz clock\n");
> + goto unregister_clks;
> + }
> +
> + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data->clk_data);
> + if (ret) {
> + dev_err_probe(dev, ret, "Failed to add clk OF provider\n");
> + goto put_26m_clk;
> + }
> +
> + data->genpd.name = "mfg_apm";
"mfg-apm" or "mfg-pwr" please!
Everything else looks good.
Thanks for taking care of that, I started this work way too much time ago and
realistically I wouldn't have been able to finish it due to time constraints.
It's great to see that *finally* we can get some GPU upstream on this old SoC.
As its CPUs are really slow, LLVMPipe is quite unusable from a UX perspective
hence its only big issue was the lack of 3D HW acceleration.
This makes machines embedding this SoC usable, and that's simply awesome.
Cheers!
Angelo
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 3/6] dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU
2024-05-30 8:35 ` [PATCH 3/6] dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU Chen-Yu Tsai
@ 2024-05-30 10:03 ` AngeloGioacchino Del Regno
2024-05-30 15:38 ` Conor Dooley
2024-05-31 13:37 ` Frank Binns
2 siblings, 0 replies; 38+ messages in thread
From: AngeloGioacchino Del Regno @ 2024-05-30 10:03 UTC (permalink / raw)
To: Chen-Yu Tsai, Frank Binns, Matt Coster, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: David Airlie, Daniel Vetter, dri-devel, linux-clk, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel
Il 30/05/24 10:35, Chen-Yu Tsai ha scritto:
> The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is one
> of the Series6XT GPUs, another sub-family of the Rogue family.
>
> This was part of the very first few versions of the PowerVR submission,
> but was later dropped. The compatible string has been updated to follow
> the new naming scheme adopted for the AXE series.
>
> In a previous iteration of the PowerVR binding submission [1], the
> number of clocks required for the 6XT family was mentioned to be
> always 3. This is also reflected here.
>
> [1] https://lore.kernel.org/dri-devel/6eeccb26e09aad67fb30ffcd523c793a43c79c2a.camel@imgtec.com/
>
> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 4/6] drm/imagination: Add compatible string entry for Series6XT
2024-05-30 8:35 ` [PATCH 4/6] drm/imagination: Add compatible string entry for Series6XT Chen-Yu Tsai
@ 2024-05-30 10:03 ` AngeloGioacchino Del Regno
2024-05-31 11:18 ` Frank Binns
1 sibling, 0 replies; 38+ messages in thread
From: AngeloGioacchino Del Regno @ 2024-05-30 10:03 UTC (permalink / raw)
To: Chen-Yu Tsai, Frank Binns, Matt Coster, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: David Airlie, Daniel Vetter, dri-devel, linux-clk, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel
Il 30/05/24 10:35, Chen-Yu Tsai ha scritto:
> The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is part
> of the Series6XT, another variation of the Rogue family of GPUs.
>
> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 5/6] arm64: dts: mediatek: mt8173: Fix MFG_ASYNC power domain clock
2024-05-30 8:35 ` [PATCH 5/6] arm64: dts: mediatek: mt8173: Fix MFG_ASYNC power domain clock Chen-Yu Tsai
@ 2024-05-30 10:03 ` AngeloGioacchino Del Regno
2024-06-05 8:25 ` Chen-Yu Tsai
0 siblings, 1 reply; 38+ messages in thread
From: AngeloGioacchino Del Regno @ 2024-05-30 10:03 UTC (permalink / raw)
To: Chen-Yu Tsai, Frank Binns, Matt Coster, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: David Airlie, Daniel Vetter, dri-devel, linux-clk, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel
Il 30/05/24 10:35, Chen-Yu Tsai ha scritto:
> The MFG_ASYNC domain, which is likely associated to the whole MFG block,
> currently specifies clk26m as its domain clock. This is bogus, since the
> clock is an external crystal with no controls. Also, the MFG block has
> a independent CLK_TOP_AXI_MFG_IN_SEL clock, which according to the block
> diagram, gates access to the hardware registers. Having this one as the
> domain clock makes much more sense. This also fixes access to the MFGTOP
> registers.
>
> Change the MFG_ASYNC domain clock to CLK_TOP_AXI_MFG_IN_SEL.
>
> Fixes: 8b6562644df9 ("arm64: dts: mediatek: Add mt8173 power domain controller")
> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Just one question... what happens if there's no GPU support at all and this
power domain gets powered off?
I expect the answer to be "nothing", so I'm preventively giving you my
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
....but if I'm wrong and the answer isn't exactly "nothing", then I still agree
with this commit, but only after removing the Fixes tag.
Cheers,
Angelo
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 3458be7f7f61..136b28f80cc2 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -497,7 +497,7 @@ power-domain@MT8173_POWER_DOMAIN_USB {
> };
> mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
> reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
> - clocks = <&clk26m>;
> + clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>;
> clock-names = "mfg";
> #address-cells = <1>;
> #size-cells = <0>;
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 6/6] arm64: dts: mediatek: mt8173: Add GPU device nodes
2024-05-30 8:35 ` [PATCH 6/6] arm64: dts: mediatek: mt8173: Add GPU device nodes Chen-Yu Tsai
@ 2024-05-30 10:04 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 38+ messages in thread
From: AngeloGioacchino Del Regno @ 2024-05-30 10:04 UTC (permalink / raw)
To: Chen-Yu Tsai, Frank Binns, Matt Coster, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger
Cc: David Airlie, Daniel Vetter, dri-devel, linux-clk, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel
Il 30/05/24 10:35, Chen-Yu Tsai ha scritto:
> The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is part
> of the Series6XT, another variation of the Rogue family of GPUs.
>
> On top of the GPU is a glue layer that handles some clock and power
> signals.
>
> Add device nodes for both.
>
> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver
2024-05-30 9:59 ` AngeloGioacchino Del Regno
@ 2024-05-30 10:16 ` Chen-Yu Tsai
2024-05-30 12:48 ` AngeloGioacchino Del Regno
` (2 more replies)
0 siblings, 3 replies; 38+ messages in thread
From: Chen-Yu Tsai @ 2024-05-30 10:16 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, David Airlie, Daniel Vetter,
dri-devel, linux-clk, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel
On Thu, May 30, 2024 at 5:59 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Il 30/05/24 10:35, Chen-Yu Tsai ha scritto:
> > The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP
> > in the datasheet, that contains clock gates, some power sequence signal
> > delays, and other unknown registers that get toggled when the GPU is
> > powered on.
> >
> > The clock gates are exposed as clocks provided by a clock controller,
> > while the power sequencing bits are exposed as one singular power domain.
> >
> > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> > ---
> > drivers/clk/mediatek/Kconfig | 9 +
> > drivers/clk/mediatek/Makefile | 1 +
> > drivers/clk/mediatek/clk-mt8173-mfgtop.c | 240 +++++++++++++++++++++++
> > 3 files changed, 250 insertions(+)
> > create mode 100644 drivers/clk/mediatek/clk-mt8173-mfgtop.c
> >
> > diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> > index 70a005e7e1b1..9e279c739f1c 100644
> > --- a/drivers/clk/mediatek/Kconfig
> > +++ b/drivers/clk/mediatek/Kconfig
> > @@ -500,6 +500,15 @@ config COMMON_CLK_MT8173_IMGSYS
> > help
> > This driver supports MediaTek MT8173 imgsys clocks.
> >
> > +config COMMON_CLK_MT8173_MFGTOP
> > + tristate "Clock and power driver for MediaTek MT8173 mfgtop"
> > + depends on COMMON_CLK_MT8173
> > + default COMMON_CLK_MT8173
> > + select PM_GENERIC_DOMAINS
> > + select PM_GENERIC_DOMAINS_OF
> > + help
> > + This driver supports MediaTek MT8173 mfgtop clocks and power domain.
> > +
> > config COMMON_CLK_MT8173_MMSYS
> > tristate "Clock driver for MediaTek MT8173 mmsys"
> > depends on COMMON_CLK_MT8173
> > diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> > index eeccfa039896..fdd3a76e12a1 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -77,6 +77,7 @@ obj-$(CONFIG_COMMON_CLK_MT8167_VDECSYS) += clk-mt8167-vdec.o
> > obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173-apmixedsys.o clk-mt8173-infracfg.o \
> > clk-mt8173-pericfg.o clk-mt8173-topckgen.o
> > obj-$(CONFIG_COMMON_CLK_MT8173_IMGSYS) += clk-mt8173-img.o
> > +obj-$(CONFIG_COMMON_CLK_MT8173_MFGTOP) += clk-mt8173-mfgtop.o
> > obj-$(CONFIG_COMMON_CLK_MT8173_MMSYS) += clk-mt8173-mm.o
> > obj-$(CONFIG_COMMON_CLK_MT8173_VDECSYS) += clk-mt8173-vdecsys.o
> > obj-$(CONFIG_COMMON_CLK_MT8173_VENCSYS) += clk-mt8173-vencsys.o
> > diff --git a/drivers/clk/mediatek/clk-mt8173-mfgtop.c b/drivers/clk/mediatek/clk-mt8173-mfgtop.c
> > new file mode 100644
> > index 000000000000..85fa7a7453ed
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8173-mfgtop.c
> > @@ -0,0 +1,240 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2024 Google LLC
> > + * Author: Chen-Yu Tsai <wenst@chromium.org>
> > + *
> > + * Based on driver in downstream ChromeOS v5.15 kernel.
> > + *
> > + * Copyright (c) 2014 MediaTek Inc.
> > + * Author: Chiawen Lee <chiawen.lee@mediatek.com>
> > + */
> > +
> > +#include <dt-bindings/clock/mt8173-clk.h>
> > +
> > +#include <linux/bitfield.h>
> > +#include <linux/clk.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_domain.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/regmap.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs mfg_cg_regs = {
> > + .sta_ofs = 0x0000,
> > + .clr_ofs = 0x0008,
> > + .set_ofs = 0x0004,
> > +};
> > +
> > +#define GATE_MFG(_id, _name, _parent, _shift, _flags) \
> > + GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr, _flags)
>
> Extra tabulation: please fix
One tab instead of two? OK.
> > +
> > +/* TODO: The block actually has dividers for the core and mem clocks. */
> > +static const struct mtk_gate mfg_clks[] = {
> > + GATE_MFG(CLK_MFG_AXI, "mfg_axi", "axi_mfg_in_sel", 0, CLK_SET_RATE_PARENT),
> > + GATE_MFG(CLK_MFG_MEM, "mfg_mem", "mem_mfg_in_sel", 1, CLK_SET_RATE_PARENT),
> > + GATE_MFG(CLK_MFG_G3D, "mfg_g3d", "mfg_sel", 2, CLK_SET_RATE_PARENT),
> > + GATE_MFG(CLK_MFG_26M, "mfg_26m", "clk26m", 3, 0),
> > +};
> > +
> > +static const struct mtk_clk_desc mfg_desc = {
> > + .clks = mfg_clks,
> > + .num_clks = ARRAY_SIZE(mfg_clks),
> > +};
> > +
> > +struct mt8173_mfgtop_data {
> > + struct clk_hw_onecell_data *clk_data;
> > + struct regmap *regmap;
> > + struct generic_pm_domain genpd;
> > + struct of_phandle_args parent_pd, child_pd;
> > + struct clk *clk_26m;
> > +};
> > +
> > +static const struct of_device_id of_match_clk_mt8173_mfgtop[] = {
> > + { .compatible = "mediatek,mt8173-mfgtop", .data = &mfg_desc },
> > + { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_mfgtop);
>
> Please move of_match_clk_mt8173_mfgtop before clk_mt8173_mfgtop_drv for consistency
> with all the other clock drivers.
Ack.
> > +
> > +/* Delay count in clock cycles */
> > +#define MFG_ACTIVE_POWER_CON0 0x24
> > + #define RST_B_DELAY_CNT GENMASK(7, 0) /* pwr_rst_b de-assert delay during power-up */
> > + #define CLK_EN_DELAY_CNT GENMASK(15, 8) /* CLK_DIS deassert delay during power-up */
> > + #define CLK_DIS_DELAY_CNT GENMASK(23, 16) /* CLK_DIS assert delay during power-down */
>
> The reason why I had EVT_FORCE_ABORT and ACTIVE_PWRCTL_EN in my driver is to
> document that we're keeping the event force abort disabled and, more importantly,
> we are keeping the "active power control" feature disabled.
>
> Please, add those two - or at least the ACTIVE_PWRCTL_EN - to keep that documented,
> or this information will be lost for sure.
> If in the future the ACTIVE_PWRCTL feature will become usable, it's going to be
> just a 30 seconds change, as the info is already there.
OK.
> > +
> > +#define MFG_ACTIVE_POWER_CON1 0x28
> > + #define PWR_ON_S_DELAY_CNT GENMASK(7, 0) /* pwr_on_s assert delay during power-up */
> > + #define ISO_DELAY_CNT GENMASK(15, 8) /* ISO assert delay during power-down */
> > + #define ISOOFF_DELAY_CNT GENMASK(23, 16) /* ISO de-assert delay during power-up */
> > + #define RST__DELAY_CNT GENMASK(31, 24) /* pwr_rsb_b assert delay during power-down */
> > +
> > +static int clk_mt8173_mfgtop_power_on(struct generic_pm_domain *domain)
> > +{
> > + struct mt8173_mfgtop_data *data = container_of(domain, struct mt8173_mfgtop_data, genpd);
> > +
> > + /* drives internal power management */
> > + clk_prepare_enable(data->clk_26m);
> > +
> > + /* Power on/off delays for various signals */
> > + regmap_write(data->regmap, MFG_ACTIVE_POWER_CON0,
> > + FIELD_PREP(RST_B_DELAY_CNT, 77) |
> > + FIELD_PREP(CLK_EN_DELAY_CNT, 61) |
> > + FIELD_PREP(CLK_DIS_DELAY_CNT, 60));
>
> I get that this is kinda odd to read, but still...
>
> FIELD_PREP(CLK_DIS_DELAY_CNT, 60) |
> FIELD_PREP(ACTIVE_PWRCTL_EN, 0));
>
> ...please :-)
Sure.
> > + regmap_write(data->regmap, MFG_ACTIVE_POWER_CON1,
> > + FIELD_PREP(PWR_ON_S_DELAY_CNT, 11) |
> > + FIELD_PREP(ISO_DELAY_CNT, 68) |
> > + FIELD_PREP(ISOOFF_DELAY_CNT, 69) |
> > + FIELD_PREP(RST__DELAY_CNT, 77));
> > +
> > + /* Magic numbers related to core switch sequence and delays */
> > + regmap_write(data->regmap, 0xe0, 0x7a710184);
> > + regmap_write(data->regmap, 0xe4, 0x835f6856);
> > + regmap_write(data->regmap, 0xe8, 0x002b0234);
> > + regmap_write(data->regmap, 0xec, 0x80000000);
> > + regmap_write(data->regmap, 0xa0, 0x08000000);
>
> Is there any way to retrieve information about what those registers are?
I asked. They said the project was too long ago, and they could only
figure out that it had something to do with core switch sequencing and
delays between each core, which is what I put in the comment there.
> > +
> > + return 0;
> > +}
> > +
> > +static int clk_mt8173_mfgtop_power_off(struct generic_pm_domain *domain)
> > +{
> > + struct mt8173_mfgtop_data *data = container_of(domain, struct mt8173_mfgtop_data, genpd);
> > +
> > + /* Magic numbers related to core switch sequence and delays */
> > + regmap_write(data->regmap, 0xec, 0);
> > +
> > + /* drives internal power management */
> > + clk_disable_unprepare(data->clk_26m);
> > +
> > + return 0;
> > +}
> > +
> > +static int clk_mt8173_mfgtop_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct device_node *node = dev->of_node;
> > + struct mt8173_mfgtop_data *data;
> > + int ret;
> > +
> > + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> > + if (!data)
> > + return -ENOMEM;
> > +
> > + platform_set_drvdata(pdev, data);
> > +
> > + data->clk_data = mtk_devm_alloc_clk_data(dev, ARRAY_SIZE(mfg_clks));
> > + if (!data->clk_data)
> > + return -ENOMEM;
> > +
> > + /* MTK clock gates also uses regmap */
> > + data->regmap = device_node_to_regmap(node);
> > + if (IS_ERR(data->regmap))
> > + return dev_err_probe(dev, PTR_ERR(data->regmap), "Failed to get regmap\n");
> > +
> > + data->child_pd.np = node;
> > + data->child_pd.args_count = 0;
> > + ret = of_parse_phandle_with_args(node, "power-domains", "#power-domain-cells", 0,
> > + &data->parent_pd);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to parse power domain\n");
> > +
> > + devm_pm_runtime_enable(dev);
> > + /*
> > + * Do a pm_runtime_resume_and_get() to workaround a possible
> > + * deadlock between clk_register() and the genpd framework.
> > + */
> > + ret = pm_runtime_resume_and_get(dev);
> > + if (ret) {
> > + dev_err_probe(dev, ret, "Failed to runtime resume device\n");
> > + goto put_of_node;
> > + }
> > +
> > + ret = mtk_clk_register_gates(dev, node, mfg_clks, ARRAY_SIZE(mfg_clks),
> > + data->clk_data);
> > + if (ret) {
> > + dev_err_probe(dev, ret, "Failed to register clock gates\n");
> > + goto put_pm_runtime;
> > + }
> > +
> > + data->clk_26m = clk_hw_get_clk(data->clk_data->hws[CLK_MFG_26M], "26m");
> > + if (IS_ERR(data->clk_26m)) {
> > + dev_err_probe(dev, PTR_ERR(data->clk_26m), "Failed to get 26 MHz clock\n");
> > + goto unregister_clks;
> > + }
> > +
> > + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data->clk_data);
> > + if (ret) {
> > + dev_err_probe(dev, ret, "Failed to add clk OF provider\n");
> > + goto put_26m_clk;
> > + }
> > +
> > + data->genpd.name = "mfg_apm";
>
> "mfg-apm" or "mfg-pwr" please!
Ack.
> Everything else looks good.
>
> Thanks for taking care of that, I started this work way too much time ago and
> realistically I wouldn't have been able to finish it due to time constraints.
>
> It's great to see that *finally* we can get some GPU upstream on this old SoC.
> As its CPUs are really slow, LLVMPipe is quite unusable from a UX perspective
> hence its only big issue was the lack of 3D HW acceleration.
I think there's still more work on the GPU driver side. I was digging
through the mailing list to find ways to get it running, and evidently
it doesn't fully support zink yet.
> This makes machines embedding this SoC usable, and that's simply awesome.
I'll give the patches a week to simmer while I go work on some
other stuff.
ChenYu
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver
2024-05-30 10:16 ` Chen-Yu Tsai
@ 2024-05-30 12:48 ` AngeloGioacchino Del Regno
2024-05-31 11:17 ` Frank Binns
2024-06-05 8:39 ` Chen-Yu Tsai
2 siblings, 0 replies; 38+ messages in thread
From: AngeloGioacchino Del Regno @ 2024-05-30 12:48 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, David Airlie, Daniel Vetter,
dri-devel, linux-clk, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel
Il 30/05/24 12:16, Chen-Yu Tsai ha scritto:
> On Thu, May 30, 2024 at 5:59 PM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
>>
>> Il 30/05/24 10:35, Chen-Yu Tsai ha scritto:
>>> The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP
>>> in the datasheet, that contains clock gates, some power sequence signal
>>> delays, and other unknown registers that get toggled when the GPU is
>>> powered on.
>>>
>>> The clock gates are exposed as clocks provided by a clock controller,
>>> while the power sequencing bits are exposed as one singular power domain.
>>>
>>> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
>>> ---
>>> drivers/clk/mediatek/Kconfig | 9 +
>>> drivers/clk/mediatek/Makefile | 1 +
>>> drivers/clk/mediatek/clk-mt8173-mfgtop.c | 240 +++++++++++++++++++++++
>>> 3 files changed, 250 insertions(+)
>>> create mode 100644 drivers/clk/mediatek/clk-mt8173-mfgtop.c
>>>
>>> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
>>> index 70a005e7e1b1..9e279c739f1c 100644
>>> --- a/drivers/clk/mediatek/Kconfig
>>> +++ b/drivers/clk/mediatek/Kconfig
>>> @@ -500,6 +500,15 @@ config COMMON_CLK_MT8173_IMGSYS
>>> help
>>> This driver supports MediaTek MT8173 imgsys clocks.
>>>
>>> +config COMMON_CLK_MT8173_MFGTOP
>>> + tristate "Clock and power driver for MediaTek MT8173 mfgtop"
>>> + depends on COMMON_CLK_MT8173
>>> + default COMMON_CLK_MT8173
>>> + select PM_GENERIC_DOMAINS
>>> + select PM_GENERIC_DOMAINS_OF
>>> + help
>>> + This driver supports MediaTek MT8173 mfgtop clocks and power domain.
>>> +
>>> config COMMON_CLK_MT8173_MMSYS
>>> tristate "Clock driver for MediaTek MT8173 mmsys"
>>> depends on COMMON_CLK_MT8173
>>> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
>>> index eeccfa039896..fdd3a76e12a1 100644
>>> --- a/drivers/clk/mediatek/Makefile
>>> +++ b/drivers/clk/mediatek/Makefile
>>> @@ -77,6 +77,7 @@ obj-$(CONFIG_COMMON_CLK_MT8167_VDECSYS) += clk-mt8167-vdec.o
>>> obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173-apmixedsys.o clk-mt8173-infracfg.o \
>>> clk-mt8173-pericfg.o clk-mt8173-topckgen.o
>>> obj-$(CONFIG_COMMON_CLK_MT8173_IMGSYS) += clk-mt8173-img.o
>>> +obj-$(CONFIG_COMMON_CLK_MT8173_MFGTOP) += clk-mt8173-mfgtop.o
>>> obj-$(CONFIG_COMMON_CLK_MT8173_MMSYS) += clk-mt8173-mm.o
>>> obj-$(CONFIG_COMMON_CLK_MT8173_VDECSYS) += clk-mt8173-vdecsys.o
>>> obj-$(CONFIG_COMMON_CLK_MT8173_VENCSYS) += clk-mt8173-vencsys.o
>>> diff --git a/drivers/clk/mediatek/clk-mt8173-mfgtop.c b/drivers/clk/mediatek/clk-mt8173-mfgtop.c
>>> new file mode 100644
>>> index 000000000000..85fa7a7453ed
>>> --- /dev/null
>>> +++ b/drivers/clk/mediatek/clk-mt8173-mfgtop.c
>>> @@ -0,0 +1,240 @@
>>> +// SPDX-License-Identifier: GPL-2.0-only
>>> +/*
>>> + * Copyright (c) 2024 Google LLC
>>> + * Author: Chen-Yu Tsai <wenst@chromium.org>
>>> + *
>>> + * Based on driver in downstream ChromeOS v5.15 kernel.
>>> + *
>>> + * Copyright (c) 2014 MediaTek Inc.
>>> + * Author: Chiawen Lee <chiawen.lee@mediatek.com>
>>> + */
>>> +
>>> +#include <dt-bindings/clock/mt8173-clk.h>
>>> +
>>> +#include <linux/bitfield.h>
>>> +#include <linux/clk.h>
>>> +#include <linux/mfd/syscon.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/pm_domain.h>
>>> +#include <linux/pm_runtime.h>
>>> +#include <linux/regmap.h>
>>> +
>>> +#include "clk-gate.h"
>>> +#include "clk-mtk.h"
>>> +
>>> +static const struct mtk_gate_regs mfg_cg_regs = {
>>> + .sta_ofs = 0x0000,
>>> + .clr_ofs = 0x0008,
>>> + .set_ofs = 0x0004,
>>> +};
>>> +
>>> +#define GATE_MFG(_id, _name, _parent, _shift, _flags) \
>>> + GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr, _flags)
>>
>> Extra tabulation: please fix
>
> One tab instead of two? OK.
>
Yeah.
>>> +
>>> +/* TODO: The block actually has dividers for the core and mem clocks. */
>>> +static const struct mtk_gate mfg_clks[] = {
>>> + GATE_MFG(CLK_MFG_AXI, "mfg_axi", "axi_mfg_in_sel", 0, CLK_SET_RATE_PARENT),
>>> + GATE_MFG(CLK_MFG_MEM, "mfg_mem", "mem_mfg_in_sel", 1, CLK_SET_RATE_PARENT),
>>> + GATE_MFG(CLK_MFG_G3D, "mfg_g3d", "mfg_sel", 2, CLK_SET_RATE_PARENT),
>>> + GATE_MFG(CLK_MFG_26M, "mfg_26m", "clk26m", 3, 0),
>>> +};
>>> +
>>> +static const struct mtk_clk_desc mfg_desc = {
>>> + .clks = mfg_clks,
>>> + .num_clks = ARRAY_SIZE(mfg_clks),
>>> +};
>>> +
>>> +struct mt8173_mfgtop_data {
>>> + struct clk_hw_onecell_data *clk_data;
>>> + struct regmap *regmap;
>>> + struct generic_pm_domain genpd;
>>> + struct of_phandle_args parent_pd, child_pd;
>>> + struct clk *clk_26m;
>>> +};
>>> +
>>> +static const struct of_device_id of_match_clk_mt8173_mfgtop[] = {
>>> + { .compatible = "mediatek,mt8173-mfgtop", .data = &mfg_desc },
>>> + { /* sentinel */ }
>>> +};
>>> +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_mfgtop);
>>
>> Please move of_match_clk_mt8173_mfgtop before clk_mt8173_mfgtop_drv for consistency
>> with all the other clock drivers.
>
> Ack.
>
>>> +
>>> +/* Delay count in clock cycles */
>>> +#define MFG_ACTIVE_POWER_CON0 0x24
>>> + #define RST_B_DELAY_CNT GENMASK(7, 0) /* pwr_rst_b de-assert delay during power-up */
>>> + #define CLK_EN_DELAY_CNT GENMASK(15, 8) /* CLK_DIS deassert delay during power-up */
>>> + #define CLK_DIS_DELAY_CNT GENMASK(23, 16) /* CLK_DIS assert delay during power-down */
>>
>> The reason why I had EVT_FORCE_ABORT and ACTIVE_PWRCTL_EN in my driver is to
>> document that we're keeping the event force abort disabled and, more importantly,
>> we are keeping the "active power control" feature disabled.
>>
>> Please, add those two - or at least the ACTIVE_PWRCTL_EN - to keep that documented,
>> or this information will be lost for sure.
>> If in the future the ACTIVE_PWRCTL feature will become usable, it's going to be
>> just a 30 seconds change, as the info is already there.
>
> OK.
>
>>> +
>>> +#define MFG_ACTIVE_POWER_CON1 0x28
>>> + #define PWR_ON_S_DELAY_CNT GENMASK(7, 0) /* pwr_on_s assert delay during power-up */
>>> + #define ISO_DELAY_CNT GENMASK(15, 8) /* ISO assert delay during power-down */
>>> + #define ISOOFF_DELAY_CNT GENMASK(23, 16) /* ISO de-assert delay during power-up */
>>> + #define RST__DELAY_CNT GENMASK(31, 24) /* pwr_rsb_b assert delay during power-down */
>>> +
>>> +static int clk_mt8173_mfgtop_power_on(struct generic_pm_domain *domain)
>>> +{
>>> + struct mt8173_mfgtop_data *data = container_of(domain, struct mt8173_mfgtop_data, genpd);
>>> +
>>> + /* drives internal power management */
>>> + clk_prepare_enable(data->clk_26m);
>>> +
>>> + /* Power on/off delays for various signals */
>>> + regmap_write(data->regmap, MFG_ACTIVE_POWER_CON0,
>>> + FIELD_PREP(RST_B_DELAY_CNT, 77) |
>>> + FIELD_PREP(CLK_EN_DELAY_CNT, 61) |
>>> + FIELD_PREP(CLK_DIS_DELAY_CNT, 60));
>>
>> I get that this is kinda odd to read, but still...
>>
>> FIELD_PREP(CLK_DIS_DELAY_CNT, 60) |
>> FIELD_PREP(ACTIVE_PWRCTL_EN, 0));
>>
>> ...please :-)
>
> Sure.
>
>>> + regmap_write(data->regmap, MFG_ACTIVE_POWER_CON1,
>>> + FIELD_PREP(PWR_ON_S_DELAY_CNT, 11) |
>>> + FIELD_PREP(ISO_DELAY_CNT, 68) |
>>> + FIELD_PREP(ISOOFF_DELAY_CNT, 69) |
>>> + FIELD_PREP(RST__DELAY_CNT, 77));
>>> +
>>> + /* Magic numbers related to core switch sequence and delays */
>>> + regmap_write(data->regmap, 0xe0, 0x7a710184);
>>> + regmap_write(data->regmap, 0xe4, 0x835f6856);
>>> + regmap_write(data->regmap, 0xe8, 0x002b0234);
>>> + regmap_write(data->regmap, 0xec, 0x80000000);
>>> + regmap_write(data->regmap, 0xa0, 0x08000000);
>>
>> Is there any way to retrieve information about what those registers are?
>
> I asked. They said the project was too long ago, and they could only
> figure out that it had something to do with core switch sequencing and
> delays between each core, which is what I put in the comment there.
>
That's a bit sad to read, but okay, I guess we'll call it a day and keep the
magic numbers around, as that's the only option. :-(
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int clk_mt8173_mfgtop_power_off(struct generic_pm_domain *domain)
>>> +{
>>> + struct mt8173_mfgtop_data *data = container_of(domain, struct mt8173_mfgtop_data, genpd);
>>> +
>>> + /* Magic numbers related to core switch sequence and delays */
>>> + regmap_write(data->regmap, 0xec, 0);
>>> +
>>> + /* drives internal power management */
>>> + clk_disable_unprepare(data->clk_26m);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int clk_mt8173_mfgtop_probe(struct platform_device *pdev)
>>> +{
>>> + struct device *dev = &pdev->dev;
>>> + struct device_node *node = dev->of_node;
>>> + struct mt8173_mfgtop_data *data;
>>> + int ret;
>>> +
>>> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
>>> + if (!data)
>>> + return -ENOMEM;
>>> +
>>> + platform_set_drvdata(pdev, data);
>>> +
>>> + data->clk_data = mtk_devm_alloc_clk_data(dev, ARRAY_SIZE(mfg_clks));
>>> + if (!data->clk_data)
>>> + return -ENOMEM;
>>> +
>>> + /* MTK clock gates also uses regmap */
>>> + data->regmap = device_node_to_regmap(node);
>>> + if (IS_ERR(data->regmap))
>>> + return dev_err_probe(dev, PTR_ERR(data->regmap), "Failed to get regmap\n");
>>> +
>>> + data->child_pd.np = node;
>>> + data->child_pd.args_count = 0;
>>> + ret = of_parse_phandle_with_args(node, "power-domains", "#power-domain-cells", 0,
>>> + &data->parent_pd);
>>> + if (ret)
>>> + return dev_err_probe(dev, ret, "Failed to parse power domain\n");
>>> +
>>> + devm_pm_runtime_enable(dev);
>>> + /*
>>> + * Do a pm_runtime_resume_and_get() to workaround a possible
>>> + * deadlock between clk_register() and the genpd framework.
>>> + */
>>> + ret = pm_runtime_resume_and_get(dev);
>>> + if (ret) {
>>> + dev_err_probe(dev, ret, "Failed to runtime resume device\n");
>>> + goto put_of_node;
>>> + }
>>> +
>>> + ret = mtk_clk_register_gates(dev, node, mfg_clks, ARRAY_SIZE(mfg_clks),
>>> + data->clk_data);
>>> + if (ret) {
>>> + dev_err_probe(dev, ret, "Failed to register clock gates\n");
>>> + goto put_pm_runtime;
>>> + }
>>> +
>>> + data->clk_26m = clk_hw_get_clk(data->clk_data->hws[CLK_MFG_26M], "26m");
>>> + if (IS_ERR(data->clk_26m)) {
>>> + dev_err_probe(dev, PTR_ERR(data->clk_26m), "Failed to get 26 MHz clock\n");
>>> + goto unregister_clks;
>>> + }
>>> +
>>> + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data->clk_data);
>>> + if (ret) {
>>> + dev_err_probe(dev, ret, "Failed to add clk OF provider\n");
>>> + goto put_26m_clk;
>>> + }
>>> +
>>> + data->genpd.name = "mfg_apm";
>>
>> "mfg-apm" or "mfg-pwr" please!
>
> Ack.
>
>> Everything else looks good.
>>
>> Thanks for taking care of that, I started this work way too much time ago and
>> realistically I wouldn't have been able to finish it due to time constraints.
>>
>> It's great to see that *finally* we can get some GPU upstream on this old SoC.
>> As its CPUs are really slow, LLVMPipe is quite unusable from a UX perspective
>> hence its only big issue was the lack of 3D HW acceleration.
>
> I think there's still more work on the GPU driver side. I was digging
> through the mailing list to find ways to get it running, and evidently
> it doesn't fully support zink yet.
>
There's still more work to do, yes, but it's still a great advancement.
>> This makes machines embedding this SoC usable, and that's simply awesome.
>
> I'll give the patches a week to simmer while I go work on some
> other stuff.
>
Sure, no worries.
Cheers!
Angelo
> ChenYu
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 3/6] dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU
2024-05-30 8:35 ` [PATCH 3/6] dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU Chen-Yu Tsai
2024-05-30 10:03 ` AngeloGioacchino Del Regno
@ 2024-05-30 15:38 ` Conor Dooley
2024-05-31 13:37 ` Frank Binns
2 siblings, 0 replies; 38+ messages in thread
From: Conor Dooley @ 2024-05-30 15:38 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
David Airlie, Daniel Vetter, dri-devel, linux-clk, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 828 bytes --]
On Thu, May 30, 2024 at 04:35:02PM +0800, Chen-Yu Tsai wrote:
> The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is one
> of the Series6XT GPUs, another sub-family of the Rogue family.
>
> This was part of the very first few versions of the PowerVR submission,
> but was later dropped. The compatible string has been updated to follow
> the new naming scheme adopted for the AXE series.
>
> In a previous iteration of the PowerVR binding submission [1], the
> number of clocks required for the 6XT family was mentioned to be
> always 3. This is also reflected here.
>
> [1] https://lore.kernel.org/dri-devel/6eeccb26e09aad67fb30ffcd523c793a43c79c2a.camel@imgtec.com/
>
> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 1/6] dt-bindings: clock: mediatek: Add mt8173 mfgtop
2024-05-30 8:35 ` [PATCH 1/6] dt-bindings: clock: mediatek: Add mt8173 mfgtop Chen-Yu Tsai
@ 2024-05-30 15:43 ` Conor Dooley
2024-05-31 7:29 ` Chen-Yu Tsai
0 siblings, 1 reply; 38+ messages in thread
From: Conor Dooley @ 2024-05-30 15:43 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
David Airlie, Daniel Vetter, dri-devel, linux-clk, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 2624 bytes --]
On Thu, May 30, 2024 at 04:35:00PM +0800, Chen-Yu Tsai wrote:
> The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP
> in the datasheet, that contains clock gates, some power sequence signal
> delays, and other unknown registers that get toggled when the GPU is
> powered on.
>
> The clock gates are exposed as clocks provided by a clock controller,
> while the power sequencing bits are exposed as one singular power domain.
>
> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> ---
> .../clock/mediatek,mt8173-mfgtop.yaml | 71 +++++++++++++++++++
> include/dt-bindings/clock/mt8173-clk.h | 7 ++
> 2 files changed, 78 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml
> new file mode 100644
> index 000000000000..03c3c1f8cf75
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml
> @@ -0,0 +1,71 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +
> +$id: http://devicetree.org/schemas/clock/mediatek,mt8173-mfgtop.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek MT8173 MFG TOP controller
> +
> +maintainers:
> + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> +
> +description:
> + The MFG TOP glue layer controls various signals going to the MFG (GPU)
> + block on the MT8173.
> +
> +properties:
> + compatible:
> + const: mediatek,mt8173-mfgtop
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 4
minItems is not needed when minItems == maxItems.
> + maxItems: 4
> +
> + clock-names:
> + items:
> + - const: sys
> + - const: mem
> + - const: core
> + - const: clk26m
> +
> + power-domains:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> + '#power-domain-cells':
> + const: 0
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - power-domains
> + - '#clock-cells'
> + - '#power-domain-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8173-clk.h>
> + #include <dt-bindings/power/mt8173-power.h>
> +
> + mfgtop: clock-controller@13fff000 {
The label here is used, so drop it.
Otherwise,
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver
2024-05-30 8:35 ` [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver Chen-Yu Tsai
2024-05-30 9:59 ` AngeloGioacchino Del Regno
@ 2024-05-30 16:15 ` kernel test robot
2024-05-30 16:26 ` kernel test robot
2024-05-30 18:03 ` kernel test robot
3 siblings, 0 replies; 38+ messages in thread
From: kernel test robot @ 2024-05-30 16:15 UTC (permalink / raw)
To: Chen-Yu Tsai, Frank Binns, Matt Coster, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno
Cc: oe-kbuild-all, Chen-Yu Tsai, David Airlie, Daniel Vetter,
dri-devel, linux-clk, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel
Hi Chen-Yu,
kernel test robot noticed the following build errors:
[auto build test ERROR on 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0]
url: https://github.com/intel-lab-lkp/linux/commits/Chen-Yu-Tsai/dt-bindings-clock-mediatek-Add-mt8173-mfgtop/20240530-163739
base: 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
patch link: https://lore.kernel.org/r/20240530083513.4135052-3-wenst%40chromium.org
patch subject: [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver
config: arc-randconfig-001-20240530 (https://download.01.org/0day-ci/archive/20240531/202405310018.2eeqgDyV-lkp@intel.com/config)
compiler: arc-elf-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240531/202405310018.2eeqgDyV-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202405310018.2eeqgDyV-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/pmdomain/core.c: In function 'genpd_queue_power_off_work':
drivers/pmdomain/core.c:701:20: error: 'pm_wq' undeclared (first use in this function)
701 | queue_work(pm_wq, &genpd->power_off_work);
| ^~~~~
drivers/pmdomain/core.c:701:20: note: each undeclared identifier is reported only once for each function it appears in
drivers/pmdomain/core.c: In function 'genpd_dev_pm_qos_notifier':
drivers/pmdomain/core.c:900:39: error: 'struct dev_pm_info' has no member named 'ignore_children'
900 | if (!dev || dev->power.ignore_children)
| ^
drivers/pmdomain/core.c: In function 'rtpm_status_str':
>> drivers/pmdomain/core.c:3111:23: error: 'struct dev_pm_info' has no member named 'runtime_error'
3111 | if (dev->power.runtime_error)
| ^
>> drivers/pmdomain/core.c:3113:28: error: 'struct dev_pm_info' has no member named 'disable_depth'
3113 | else if (dev->power.disable_depth)
| ^
>> drivers/pmdomain/core.c:3115:28: error: 'struct dev_pm_info' has no member named 'runtime_status'
3115 | else if (dev->power.runtime_status < ARRAY_SIZE(status_lookup))
| ^
drivers/pmdomain/core.c:3116:45: error: 'struct dev_pm_info' has no member named 'runtime_status'
3116 | p = status_lookup[dev->power.runtime_status];
| ^
Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for PM_GENERIC_DOMAINS
Depends on [n]: PM [=n]
Selected by [m]:
- COMMON_CLK_MT8173_MFGTOP [=m] && COMMON_CLK [=y] && (ARCH_MEDIATEK || COMPILE_TEST [=y]) && COMMON_CLK_MT8173 [=m]
vim +3111 drivers/pmdomain/core.c
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3095
8b0510b52478a4e drivers/base/power/domain.c Jon Hunter 2016-08-11 3096 #ifdef CONFIG_DEBUG_FS
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3097 /*
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3098 * TODO: This function is a slightly modified version of rtpm_status_show
d30d819dc831078 drivers/base/power/domain.c Rafael J. Wysocki 2014-11-27 3099 * from sysfs.c, so generalize it.
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3100 */
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3101 static void rtpm_status_str(struct seq_file *s, struct device *dev)
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3102 {
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3103 static const char * const status_lookup[] = {
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3104 [RPM_ACTIVE] = "active",
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3105 [RPM_RESUMING] = "resuming",
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3106 [RPM_SUSPENDED] = "suspended",
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3107 [RPM_SUSPENDING] = "suspending"
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3108 };
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3109 const char *p = "";
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3110
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 @3111 if (dev->power.runtime_error)
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3112 p = "error";
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 @3113 else if (dev->power.disable_depth)
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3114 p = "unsupported";
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 @3115 else if (dev->power.runtime_status < ARRAY_SIZE(status_lookup))
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3116 p = status_lookup[dev->power.runtime_status];
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3117 else
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3118 WARN_ON(1);
2bd5306a8764d94 drivers/base/power/domain.c Maciej Matraszek 2014-09-15 3119
45fbc464b047b3f drivers/base/power/domain.c Dmitry Osipenko 2021-01-21 3120 seq_printf(s, "%-25s ", p);
45fbc464b047b3f drivers/base/power/domain.c Dmitry Osipenko 2021-01-21 3121 }
45fbc464b047b3f drivers/base/power/domain.c Dmitry Osipenko 2021-01-21 3122
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver
2024-05-30 8:35 ` [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver Chen-Yu Tsai
2024-05-30 9:59 ` AngeloGioacchino Del Regno
2024-05-30 16:15 ` kernel test robot
@ 2024-05-30 16:26 ` kernel test robot
2024-05-30 18:03 ` kernel test robot
3 siblings, 0 replies; 38+ messages in thread
From: kernel test robot @ 2024-05-30 16:26 UTC (permalink / raw)
To: Chen-Yu Tsai, Frank Binns, Matt Coster, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno
Cc: oe-kbuild-all, Chen-Yu Tsai, David Airlie, Daniel Vetter,
dri-devel, linux-clk, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel
Hi Chen-Yu,
kernel test robot noticed the following build errors:
[auto build test ERROR on 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0]
url: https://github.com/intel-lab-lkp/linux/commits/Chen-Yu-Tsai/dt-bindings-clock-mediatek-Add-mt8173-mfgtop/20240530-163739
base: 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
patch link: https://lore.kernel.org/r/20240530083513.4135052-3-wenst%40chromium.org
patch subject: [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver
config: arc-randconfig-002-20240530 (https://download.01.org/0day-ci/archive/20240531/202405310025.nOseddVa-lkp@intel.com/config)
compiler: arceb-elf-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240531/202405310025.nOseddVa-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202405310025.nOseddVa-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/pmdomain/core.c: In function 'genpd_queue_power_off_work':
>> drivers/pmdomain/core.c:701:20: error: 'pm_wq' undeclared (first use in this function)
701 | queue_work(pm_wq, &genpd->power_off_work);
| ^~~~~
drivers/pmdomain/core.c:701:20: note: each undeclared identifier is reported only once for each function it appears in
drivers/pmdomain/core.c: In function 'genpd_dev_pm_qos_notifier':
>> drivers/pmdomain/core.c:900:39: error: 'struct dev_pm_info' has no member named 'ignore_children'
900 | if (!dev || dev->power.ignore_children)
| ^
--
drivers/pmdomain/governor.c: In function 'default_suspend_ok':
>> drivers/pmdomain/governor.c:87:24: error: 'struct dev_pm_info' has no member named 'ignore_children'
87 | if (!dev->power.ignore_children)
| ^
Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for PM_GENERIC_DOMAINS
Depends on [n]: PM [=n]
Selected by [y]:
- COMMON_CLK_MT8173_MFGTOP [=y] && COMMON_CLK [=y] && (ARCH_MEDIATEK || COMPILE_TEST [=y]) && COMMON_CLK_MT8173 [=y]
vim +/pm_wq +701 drivers/pmdomain/core.c
c8f0ea45169c57 drivers/base/power/domain.c Geert Uytterhoeven 2014-11-10 691
29e47e2173349e drivers/base/power/domain.c Ulf Hansson 2015-09-02 692 /**
86e12eac1f7f84 drivers/base/power/domain.c Ulf Hansson 2016-12-08 693 * genpd_queue_power_off_work - Queue up the execution of genpd_power_off().
a3d09c73492e57 drivers/base/power/domain.c Moritz Fischer 2016-01-27 694 * @genpd: PM domain to power off.
29e47e2173349e drivers/base/power/domain.c Ulf Hansson 2015-09-02 695 *
86e12eac1f7f84 drivers/base/power/domain.c Ulf Hansson 2016-12-08 696 * Queue up the execution of genpd_power_off() unless it's already been done
29e47e2173349e drivers/base/power/domain.c Ulf Hansson 2015-09-02 697 * before.
29e47e2173349e drivers/base/power/domain.c Ulf Hansson 2015-09-02 698 */
29e47e2173349e drivers/base/power/domain.c Ulf Hansson 2015-09-02 699 static void genpd_queue_power_off_work(struct generic_pm_domain *genpd)
29e47e2173349e drivers/base/power/domain.c Ulf Hansson 2015-09-02 700 {
29e47e2173349e drivers/base/power/domain.c Ulf Hansson 2015-09-02 @701 queue_work(pm_wq, &genpd->power_off_work);
29e47e2173349e drivers/base/power/domain.c Ulf Hansson 2015-09-02 702 }
29e47e2173349e drivers/base/power/domain.c Ulf Hansson 2015-09-02 703
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 704 /**
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 705 * genpd_power_off - Remove power from a given PM domain.
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 706 * @genpd: PM domain to power down.
3c64649d1cf9f3 drivers/base/power/domain.c Ulf Hansson 2017-02-17 707 * @one_dev_on: If invoked from genpd's ->runtime_suspend|resume() callback, the
3c64649d1cf9f3 drivers/base/power/domain.c Ulf Hansson 2017-02-17 708 * RPM status of the releated device is in an intermediate state, not yet turned
3c64649d1cf9f3 drivers/base/power/domain.c Ulf Hansson 2017-02-17 709 * into RPM_SUSPENDED. This means genpd_power_off() must allow one device to not
3c64649d1cf9f3 drivers/base/power/domain.c Ulf Hansson 2017-02-17 710 * be RPM_SUSPENDED, while it tries to power off the PM domain.
763663c9715f5f drivers/base/power/domain.c Yang Yingliang 2021-05-12 711 * @depth: nesting count for lockdep.
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 712 *
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 713 * If all of the @genpd's devices have been suspended and all of its subdomains
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 714 * have been powered down, remove power from @genpd.
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 715 */
2da835452a0875 drivers/base/power/domain.c Ulf Hansson 2017-02-17 716 static int genpd_power_off(struct generic_pm_domain *genpd, bool one_dev_on,
2da835452a0875 drivers/base/power/domain.c Ulf Hansson 2017-02-17 717 unsigned int depth)
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 718 {
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 719 struct pm_domain_data *pdd;
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 720 struct gpd_link *link;
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 721 unsigned int not_suspended = 0;
f63816e43d9044 drivers/base/power/domain.c Ulf Hansson 2020-09-24 722 int ret;
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 723
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 724 /*
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 725 * Do not try to power off the domain in the following situations:
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 726 * (1) The domain is already in the "power off" state.
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 727 * (2) System suspend is in progress.
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 728 */
41e2c8e0060db2 drivers/base/power/domain.c Ulf Hansson 2017-03-20 729 if (!genpd_status_on(genpd) || genpd->prepared_count > 0)
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 730 return 0;
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 731
ffaa42e8a40b7f drivers/base/power/domain.c Ulf Hansson 2017-03-20 732 /*
ffaa42e8a40b7f drivers/base/power/domain.c Ulf Hansson 2017-03-20 733 * Abort power off for the PM domain in the following situations:
ffaa42e8a40b7f drivers/base/power/domain.c Ulf Hansson 2017-03-20 734 * (1) The domain is configured as always on.
ffaa42e8a40b7f drivers/base/power/domain.c Ulf Hansson 2017-03-20 735 * (2) When the domain has a subdomain being powered on.
ffaa42e8a40b7f drivers/base/power/domain.c Ulf Hansson 2017-03-20 736 */
ed61e18a4b4e44 drivers/base/power/domain.c Leonard Crestez 2019-04-30 737 if (genpd_is_always_on(genpd) ||
ed61e18a4b4e44 drivers/base/power/domain.c Leonard Crestez 2019-04-30 738 genpd_is_rpm_always_on(genpd) ||
ed61e18a4b4e44 drivers/base/power/domain.c Leonard Crestez 2019-04-30 739 atomic_read(&genpd->sd_count) > 0)
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 740 return -EBUSY;
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 741
e7d90cfac5510f drivers/base/power/domain.c Ulf Hansson 2022-02-17 742 /*
e7d90cfac5510f drivers/base/power/domain.c Ulf Hansson 2022-02-17 743 * The children must be in their deepest (powered-off) states to allow
e7d90cfac5510f drivers/base/power/domain.c Ulf Hansson 2022-02-17 744 * the parent to be powered off. Note that, there's no need for
e7d90cfac5510f drivers/base/power/domain.c Ulf Hansson 2022-02-17 745 * additional locking, as powering on a child, requires the parent's
e7d90cfac5510f drivers/base/power/domain.c Ulf Hansson 2022-02-17 746 * lock to be acquired first.
e7d90cfac5510f drivers/base/power/domain.c Ulf Hansson 2022-02-17 747 */
e7d90cfac5510f drivers/base/power/domain.c Ulf Hansson 2022-02-17 748 list_for_each_entry(link, &genpd->parent_links, parent_node) {
e7d90cfac5510f drivers/base/power/domain.c Ulf Hansson 2022-02-17 749 struct generic_pm_domain *child = link->child;
e7d90cfac5510f drivers/base/power/domain.c Ulf Hansson 2022-02-17 750 if (child->state_idx < child->state_count - 1)
e7d90cfac5510f drivers/base/power/domain.c Ulf Hansson 2022-02-17 751 return -EBUSY;
e7d90cfac5510f drivers/base/power/domain.c Ulf Hansson 2022-02-17 752 }
e7d90cfac5510f drivers/base/power/domain.c Ulf Hansson 2022-02-17 753
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 754 list_for_each_entry(pdd, &genpd->dev_list, list_node) {
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 755 /*
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 756 * Do not allow PM domain to be powered off, when an IRQ safe
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 757 * device is part of a non-IRQ safe domain.
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 758 */
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 759 if (!pm_runtime_suspended(pdd->dev) ||
7a02444b8fc25a drivers/base/power/domain.c Ulf Hansson 2022-05-11 760 irq_safe_dev_in_sleep_domain(pdd->dev, genpd))
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 761 not_suspended++;
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 762 }
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 763
3c64649d1cf9f3 drivers/base/power/domain.c Ulf Hansson 2017-02-17 764 if (not_suspended > 1 || (not_suspended == 1 && !one_dev_on))
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 765 return -EBUSY;
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 766
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 767 if (genpd->gov && genpd->gov->power_down_ok) {
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 768 if (!genpd->gov->power_down_ok(&genpd->domain))
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 769 return -EAGAIN;
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 770 }
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 771
2c9b7f8772033c drivers/base/power/domain.c Ulf Hansson 2018-10-03 772 /* Default to shallowest state. */
2c9b7f8772033c drivers/base/power/domain.c Ulf Hansson 2018-10-03 773 if (!genpd->gov)
2c9b7f8772033c drivers/base/power/domain.c Ulf Hansson 2018-10-03 774 genpd->state_idx = 0;
2c9b7f8772033c drivers/base/power/domain.c Ulf Hansson 2018-10-03 775
f63816e43d9044 drivers/base/power/domain.c Ulf Hansson 2020-09-24 776 /* Don't power off, if a child domain is waiting to power on. */
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 777 if (atomic_read(&genpd->sd_count) > 0)
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 778 return -EBUSY;
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 779
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 780 ret = _genpd_power_off(genpd, true);
c6a113b52302ad drivers/base/power/domain.c Lina Iyer 2020-10-15 781 if (ret) {
c6a113b52302ad drivers/base/power/domain.c Lina Iyer 2020-10-15 782 genpd->states[genpd->state_idx].rejected++;
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 783 return ret;
c6a113b52302ad drivers/base/power/domain.c Lina Iyer 2020-10-15 784 }
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 785
49f618e1b669ef drivers/base/power/domain.c Ulf Hansson 2020-09-24 786 genpd->status = GENPD_STATE_OFF;
afece3ab9a3640 drivers/base/power/domain.c Thara Gopinath 2017-07-14 787 genpd_update_accounting(genpd);
c6a113b52302ad drivers/base/power/domain.c Lina Iyer 2020-10-15 788 genpd->states[genpd->state_idx].usage++;
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 789
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 790 list_for_each_entry(link, &genpd->child_links, child_node) {
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 791 genpd_sd_counter_dec(link->parent);
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 792 genpd_lock_nested(link->parent, depth + 1);
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 793 genpd_power_off(link->parent, false, depth + 1);
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 794 genpd_unlock(link->parent);
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 795 }
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 796
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 797 return 0;
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 798 }
1f8728b7adc4c2 drivers/base/power/domain.c Ulf Hansson 2017-02-17 799
5248051b9afb66 drivers/base/power/domain.c Rafael J. Wysocki 2011-07-01 800 /**
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 801 * genpd_power_on - Restore power to a given PM domain and its parents.
5248051b9afb66 drivers/base/power/domain.c Rafael J. Wysocki 2011-07-01 802 * @genpd: PM domain to power up.
0106ef5146f9e8 drivers/base/power/domain.c Marek Szyprowski 2016-01-20 803 * @depth: nesting count for lockdep.
5248051b9afb66 drivers/base/power/domain.c Rafael J. Wysocki 2011-07-01 804 *
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 805 * Restore power to @genpd and all of its parents so that it is possible to
5248051b9afb66 drivers/base/power/domain.c Rafael J. Wysocki 2011-07-01 806 * resume a device belonging to it.
5248051b9afb66 drivers/base/power/domain.c Rafael J. Wysocki 2011-07-01 807 */
86e12eac1f7f84 drivers/base/power/domain.c Ulf Hansson 2016-12-08 808 static int genpd_power_on(struct generic_pm_domain *genpd, unsigned int depth)
5248051b9afb66 drivers/base/power/domain.c Rafael J. Wysocki 2011-07-01 809 {
5063ce1571b738 drivers/base/power/domain.c Rafael J. Wysocki 2011-08-08 810 struct gpd_link *link;
5248051b9afb66 drivers/base/power/domain.c Rafael J. Wysocki 2011-07-01 811 int ret = 0;
5248051b9afb66 drivers/base/power/domain.c Rafael J. Wysocki 2011-07-01 812
41e2c8e0060db2 drivers/base/power/domain.c Ulf Hansson 2017-03-20 813 if (genpd_status_on(genpd))
3f241775c30365 drivers/base/power/domain.c Rafael J. Wysocki 2011-08-08 814 return 0;
5248051b9afb66 drivers/base/power/domain.c Rafael J. Wysocki 2011-07-01 815
5063ce1571b738 drivers/base/power/domain.c Rafael J. Wysocki 2011-08-08 816 /*
5063ce1571b738 drivers/base/power/domain.c Rafael J. Wysocki 2011-08-08 817 * The list is guaranteed not to change while the loop below is being
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 818 * executed, unless one of the parents' .power_on() callbacks fiddles
5063ce1571b738 drivers/base/power/domain.c Rafael J. Wysocki 2011-08-08 819 * with it.
5063ce1571b738 drivers/base/power/domain.c Rafael J. Wysocki 2011-08-08 820 */
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 821 list_for_each_entry(link, &genpd->child_links, child_node) {
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 822 struct generic_pm_domain *parent = link->parent;
0106ef5146f9e8 drivers/base/power/domain.c Marek Szyprowski 2016-01-20 823
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 824 genpd_sd_counter_inc(parent);
0106ef5146f9e8 drivers/base/power/domain.c Marek Szyprowski 2016-01-20 825
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 826 genpd_lock_nested(parent, depth + 1);
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 827 ret = genpd_power_on(parent, depth + 1);
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 828 genpd_unlock(parent);
5248051b9afb66 drivers/base/power/domain.c Rafael J. Wysocki 2011-07-01 829
5063ce1571b738 drivers/base/power/domain.c Rafael J. Wysocki 2011-08-08 830 if (ret) {
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 831 genpd_sd_counter_dec(parent);
9e08cf42969709 drivers/base/power/domain.c Rafael J. Wysocki 2011-08-08 832 goto err;
5248051b9afb66 drivers/base/power/domain.c Rafael J. Wysocki 2011-07-01 833 }
5063ce1571b738 drivers/base/power/domain.c Rafael J. Wysocki 2011-08-08 834 }
5248051b9afb66 drivers/base/power/domain.c Rafael J. Wysocki 2011-07-01 835
86e12eac1f7f84 drivers/base/power/domain.c Ulf Hansson 2016-12-08 836 ret = _genpd_power_on(genpd, true);
9e08cf42969709 drivers/base/power/domain.c Rafael J. Wysocki 2011-08-08 837 if (ret)
9e08cf42969709 drivers/base/power/domain.c Rafael J. Wysocki 2011-08-08 838 goto err;
0140d8bd47f798 drivers/base/power/domain.c Rafael J. Wysocki 2011-12-01 839
49f618e1b669ef drivers/base/power/domain.c Ulf Hansson 2020-09-24 840 genpd->status = GENPD_STATE_ON;
afece3ab9a3640 drivers/base/power/domain.c Thara Gopinath 2017-07-14 841 genpd_update_accounting(genpd);
afece3ab9a3640 drivers/base/power/domain.c Thara Gopinath 2017-07-14 842
3f241775c30365 drivers/base/power/domain.c Rafael J. Wysocki 2011-08-08 843 return 0;
9e08cf42969709 drivers/base/power/domain.c Rafael J. Wysocki 2011-08-08 844
9e08cf42969709 drivers/base/power/domain.c Rafael J. Wysocki 2011-08-08 845 err:
29e47e2173349e drivers/base/power/domain.c Ulf Hansson 2015-09-02 846 list_for_each_entry_continue_reverse(link,
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 847 &genpd->child_links,
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 848 child_node) {
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 849 genpd_sd_counter_dec(link->parent);
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 850 genpd_lock_nested(link->parent, depth + 1);
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 851 genpd_power_off(link->parent, false, depth + 1);
8d87ae48ced2df drivers/base/power/domain.c Kees Cook 2020-07-08 852 genpd_unlock(link->parent);
29e47e2173349e drivers/base/power/domain.c Ulf Hansson 2015-09-02 853 }
9e08cf42969709 drivers/base/power/domain.c Rafael J. Wysocki 2011-08-08 854
3f241775c30365 drivers/base/power/domain.c Rafael J. Wysocki 2011-08-08 855 return ret;
3f241775c30365 drivers/base/power/domain.c Rafael J. Wysocki 2011-08-08 856 }
3f241775c30365 drivers/base/power/domain.c Rafael J. Wysocki 2011-08-08 857
ea71c59669f17d drivers/base/power/domain.c Ulf Hansson 2019-10-16 858 static int genpd_dev_pm_start(struct device *dev)
ea71c59669f17d drivers/base/power/domain.c Ulf Hansson 2019-10-16 859 {
ea71c59669f17d drivers/base/power/domain.c Ulf Hansson 2019-10-16 860 struct generic_pm_domain *genpd = dev_to_genpd(dev);
ea71c59669f17d drivers/base/power/domain.c Ulf Hansson 2019-10-16 861
ea71c59669f17d drivers/base/power/domain.c Ulf Hansson 2019-10-16 862 return genpd_start_dev(genpd, dev);
ea71c59669f17d drivers/base/power/domain.c Ulf Hansson 2019-10-16 863 }
ea71c59669f17d drivers/base/power/domain.c Ulf Hansson 2019-10-16 864
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 865 static int genpd_dev_pm_qos_notifier(struct notifier_block *nb,
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 866 unsigned long val, void *ptr)
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 867 {
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 868 struct generic_pm_domain_data *gpd_data;
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 869 struct device *dev;
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 870
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 871 gpd_data = container_of(nb, struct generic_pm_domain_data, nb);
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 872 dev = gpd_data->base.dev;
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 873
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 874 for (;;) {
f38d1a6d002526 drivers/base/power/domain.c Ulf Hansson 2022-05-11 875 struct generic_pm_domain *genpd = ERR_PTR(-ENODATA);
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 876 struct pm_domain_data *pdd;
66d29d802ef3bf drivers/base/power/domain.c Ulf Hansson 2022-05-11 877 struct gpd_timing_data *td;
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 878
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 879 spin_lock_irq(&dev->power.lock);
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 880
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 881 pdd = dev->power.subsys_data ?
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 882 dev->power.subsys_data->domain_data : NULL;
b4883ca449473e drivers/base/power/domain.c Viresh Kumar 2017-05-16 883 if (pdd) {
66d29d802ef3bf drivers/base/power/domain.c Ulf Hansson 2022-05-11 884 td = to_gpd_data(pdd)->td;
f38d1a6d002526 drivers/base/power/domain.c Ulf Hansson 2022-05-11 885 if (td) {
66d29d802ef3bf drivers/base/power/domain.c Ulf Hansson 2022-05-11 886 td->constraint_changed = true;
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 887 genpd = dev_to_genpd(dev);
f38d1a6d002526 drivers/base/power/domain.c Ulf Hansson 2022-05-11 888 }
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 889 }
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 890
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 891 spin_unlock_irq(&dev->power.lock);
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 892
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 893 if (!IS_ERR(genpd)) {
35241d12f750d2 drivers/base/power/domain.c Lina Iyer 2016-10-14 894 genpd_lock(genpd);
f38d1a6d002526 drivers/base/power/domain.c Ulf Hansson 2022-05-11 895 genpd->gd->max_off_time_changed = true;
35241d12f750d2 drivers/base/power/domain.c Lina Iyer 2016-10-14 896 genpd_unlock(genpd);
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 897 }
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 898
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 899 dev = dev->parent;
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 @900 if (!dev || dev->power.ignore_children)
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 901 break;
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 902 }
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 903
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 904 return NOTIFY_DONE;
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 905 }
6ff7bb0d02f829 drivers/base/power/domain.c Rafael J. Wysocki 2012-05-01 906
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver
2024-05-30 8:35 ` [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver Chen-Yu Tsai
` (2 preceding siblings ...)
2024-05-30 16:26 ` kernel test robot
@ 2024-05-30 18:03 ` kernel test robot
3 siblings, 0 replies; 38+ messages in thread
From: kernel test robot @ 2024-05-30 18:03 UTC (permalink / raw)
To: Chen-Yu Tsai, Frank Binns, Matt Coster, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno
Cc: oe-kbuild-all, Chen-Yu Tsai, David Airlie, Daniel Vetter,
dri-devel, linux-clk, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel
Hi Chen-Yu,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0]
url: https://github.com/intel-lab-lkp/linux/commits/Chen-Yu-Tsai/dt-bindings-clock-mediatek-Add-mt8173-mfgtop/20240530-163739
base: 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
patch link: https://lore.kernel.org/r/20240530083513.4135052-3-wenst%40chromium.org
patch subject: [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver
config: x86_64-buildonly-randconfig-002-20240531 (https://download.01.org/0day-ci/archive/20240531/202405310123.KWoPspRr-lkp@intel.com/config)
compiler: gcc-13 (Ubuntu 13.2.0-4ubuntu3) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240531/202405310123.KWoPspRr-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202405310123.KWoPspRr-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/pmdomain/core.c:2965:34: warning: 'idle_state_match' defined but not used [-Wunused-const-variable=]
2965 | static const struct of_device_id idle_state_match[] = {
| ^~~~~~~~~~~~~~~~
Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for PM_GENERIC_DOMAINS_OF
Depends on [n]: PM_GENERIC_DOMAINS [=y] && OF [=n]
Selected by [y]:
- COMMON_CLK_MT8173_MFGTOP [=y] && COMMON_CLK [=y] && (ARCH_MEDIATEK || COMPILE_TEST [=y]) && COMMON_CLK_MT8173 [=y]
vim +/idle_state_match +2965 drivers/pmdomain/core.c
5d6be70add65e3 drivers/base/power/domain.c Ulf Hansson 2018-06-29 2964
30f604283e05d3 drivers/base/power/domain.c Lina Iyer 2016-10-14 @2965 static const struct of_device_id idle_state_match[] = {
598da548ef7892 drivers/base/power/domain.c Lina Iyer 2016-11-03 2966 { .compatible = "domain-idle-state", },
30f604283e05d3 drivers/base/power/domain.c Lina Iyer 2016-10-14 2967 { }
30f604283e05d3 drivers/base/power/domain.c Lina Iyer 2016-10-14 2968 };
30f604283e05d3 drivers/base/power/domain.c Lina Iyer 2016-10-14 2969
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 0/6] powervr: MT8173 GPU support
2024-05-30 8:34 [PATCH 0/6] powervr: MT8173 GPU support Chen-Yu Tsai
` (5 preceding siblings ...)
2024-05-30 8:35 ` [PATCH 6/6] arm64: dts: mediatek: mt8173: Add GPU device nodes Chen-Yu Tsai
@ 2024-05-31 4:00 ` Chen-Yu Tsai
[not found] ` <d4a97a657330d50d14cb93954e8b243489bb51ef.camel@imgtec.com>
6 siblings, 1 reply; 38+ messages in thread
From: Chen-Yu Tsai @ 2024-05-31 4:00 UTC (permalink / raw)
To: Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno
Cc: David Airlie, Daniel Vetter, dri-devel, linux-clk, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel
On Thu, May 30, 2024 at 4:35 PM Chen-Yu Tsai <wenst@chromium.org> wrote:
>
> Hi everyone,
>
> This series enables the PowerVR GPU found in the MT8173 SoC, found in
> some Chromebooks.
>
> This version is different from the initial powervr driver submission [1]
> in that it splits out the GPU glue layer support out of the powervr
> driver and into a separate clock and power domain driver. The glue code
> is otherwise the same, and also the same as found in the ChromeOS
> kernels, with some extra comments and macro names added where possible.
>
> Patch 1 adds a binding for the glue layer, called mfgtop. The glue layer
> contains clock and power controls for the GPU.
>
> Patch 2 adds a driver for the glue layer.
>
> Patch 3 adds an entry for the MT8173 GPU and 6XT series to the PowerVR
> binding.
>
> Patch 4 adds an entry for the PowerVR 6XT series GPU to the driver.
>
> Patch 5 corrects the clock for the GPU (called MFG) power domain.
>
> Patch 6 adds device nodes for the GPU and glue layer to the MT8173 dtsi
> file.
>
> Patch 2 and 6 depend on patch 1 to build. I suppose some common
> immutable tree would be needed from the MediaTek maintainers.
>
> The kernel driver successfully probes the hardware and loads the
> "rogue_4.40.2.51_v1.fw" firmware provided by Imagination Technologies [2].
> Userspace was tested with Mesa 24.0.8 from Debian Trixie rebuilt with
> the powervr vulkan driver enabled. `vulkaninfo` gives some information
> about the GPU (attached at the end), but running the `triangle` example
> from the Sascha Willems demos [3] with -DUSE_D2D_WSI=ON as recommended [4]
> failed with:
>
> Can't find a display and a display mode!
>
> Same program worked correctly on a BeaglePlay and displayed a color
> gradient triangle. Not sure what went wrong here.
Frank mentioned over IRC that giving `triangle` a screen resolution would
make it work, and it did! Thanks Frank!
OTOH I'm getting some extra warnings not seen on the BeaglePlay:
MESA: error: No hard coded passthrough rta vertex shader.
Returning empty shader.
MESA: warning: ../src/imagination/vulkan/pvr_job_context.c:71:
FINISHME: Missing reset support for brn51764
MESA: warning: ../src/imagination/vulkan/pvr_job_context.c:74:
FINISHME: Missing reset support for brn58839
MESA: warning: ../src/imagination/vulkan/pvr_border.c:104:
FINISHME: Devices without tpu_border_colour_enhanced require entries
for compressed formats to be stored in the table pre-compressed.
I also get a constant stream of kernel error messages, all the same:
powervr 13000000.gpu: [drm] Received unknown FWCCB command 2abc0069
And the first few frames seem to flicker. (Though that could also be the
display driver that's at fault.)
For reference, on the BeaglePlay I see:
MESA: error: No hard coded idfwdf program. Returning empty program.
MESA: error: No hard coded passthrough vertex shader. Returning
empty shader.
MESA: warning:
../src/imagination/vulkan/pvr_descriptor_set.c:1073: FINISHME: Entry
tracker for allocations?
Regards
ChenYu
> Anyway, please have a look and test.
>
>
> Thanks
> ChenYu
>
> [1] https://lore.kernel.org/dri-devel/20220815165156.118212-2-sarah.walker@imgtec.com/
> [2] https://gitlab.freedesktop.org/imagination/linux-firmware/-/tree/powervr
> [3] https://github.com/SaschaWillems/Vulkan
> [4] https://lore.kernel.org/dri-devel/f2b2671e-5acc-4dec-9c2e-3c9cd2e1f19e@imgtec.com/
>
> Chen-Yu Tsai (6):
> dt-bindings: clock: mediatek: Add mt8173 mfgtop
> clk: mediatek: Add mt8173-mfgtop driver
> dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU
> drm/imagination: Add compatible string entry for Series6XT
> arm64: dts: mediatek: mt8173: Fix MFG_ASYNC power domain clock
> arm64: dts: mediatek: mt8173: Add GPU device nodes
>
> .../clock/mediatek,mt8173-mfgtop.yaml | 71 ++++++
> .../bindings/gpu/img,powervr-rogue.yaml | 24 +-
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 26 +-
> drivers/clk/mediatek/Kconfig | 9 +
> drivers/clk/mediatek/Makefile | 1 +
> drivers/clk/mediatek/clk-mt8173-mfgtop.c | 240 ++++++++++++++++++
> drivers/gpu/drm/imagination/pvr_drv.c | 1 +
> include/dt-bindings/clock/mt8173-clk.h | 7 +
> 8 files changed, 374 insertions(+), 5 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml
> create mode 100644 drivers/clk/mediatek/clk-mt8173-mfgtop.c
>
>
> base-commit: 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
>
> Vulkan info output:
>
> WARNING: [Loader Message] Code 0 : terminator_CreateInstance: Received return code -3 from call to vkCreateInstance in ICD /usr/lib/aarch64-linux-gnu/libvulkan_virtio.so. Skipping this driver.
> 'DISPLAY' environment variable not set... skipping surface info
> ERROR: [../src/panfrost/vulkan/panvk_device.c:386] Code 0 : WARNING: panvk is not a conformant vulkan implementation, pass PAN_I_WANT_A_BROKEN_VULKAN_DRIVER=1 if you know what you're doing. (VK_ERROR_INCOMPATIBLE_DRIVER)
> MESA: error: No hard coded idfwdf program. Returning empty program.
> MESA: error: No hard coded passthrough rta vertex shader. Returning empty shader.
> MESA: error: No hard coded passthrough vertex shader. Returning empty shader.
> MESA: warning: ../src/imagination/vulkan/pvr_job_context.c:71: FINISHME: Missing reset support for brn51764
> MESA: warning: ../src/imagination/vulkan/pvr_job_context.c:74: FINISHME: Missing reset support for brn58839
> MESA: warning: ../src/imagination/vulkan/pvr_border.c:104: FINISHME: Devices without tpu_border_colour_enhanced require entries for compressed formats to be stored in the table pre-compressed.
> ==========
> VULKANINFO
> ==========
>
> Vulkan Instance Version: 1.3.280
>
>
> Instance Extensions: count = 23
> ===============================
> VK_EXT_acquire_drm_display : extension revision 1
> VK_EXT_acquire_xlib_display : extension revision 1
> VK_EXT_debug_report : extension revision 10
> VK_EXT_debug_utils : extension revision 2
> VK_EXT_direct_mode_display : extension revision 1
> VK_EXT_display_surface_counter : extension revision 1
> VK_EXT_surface_maintenance1 : extension revision 1
> VK_EXT_swapchain_colorspace : extension revision 4
> VK_KHR_device_group_creation : extension revision 1
> VK_KHR_display : extension revision 23
> VK_KHR_external_fence_capabilities : extension revision 1
> VK_KHR_external_memory_capabilities : extension revision 1
> VK_KHR_external_semaphore_capabilities : extension revision 1
> VK_KHR_get_display_properties2 : extension revision 1
> VK_KHR_get_physical_device_properties2 : extension revision 2
> VK_KHR_get_surface_capabilities2 : extension revision 1
> VK_KHR_portability_enumeration : extension revision 1
> VK_KHR_surface : extension revision 25
> VK_KHR_surface_protected_capabilities : extension revision 1
> VK_KHR_wayland_surface : extension revision 6
> VK_KHR_xcb_surface : extension revision 6
> VK_KHR_xlib_surface : extension revision 6
> VK_LUNARG_direct_driver_loading : extension revision 1
>
> Layers: count = 2
> =================
> VK_LAYER_MESA_device_select (Linux device selection layer) Vulkan version 1.3.211, layer version 1:
> Layer Extensions: count = 0
> Devices: count = 2
> GPU id = 0 (Imagination PowerVR Rogue GX6250)
> Layer-Device Extensions: count = 0
>
> GPU id = 1 (llvmpipe (LLVM 17.0.6, 128 bits))
> Layer-Device Extensions: count = 0
>
> VK_LAYER_MESA_overlay (Mesa Overlay layer) Vulkan version 1.3.211, layer version 1:
> Layer Extensions: count = 0
> Devices: count = 2
> GPU id = 0 (Imagination PowerVR Rogue GX6250)
> Layer-Device Extensions: count = 0
>
> GPU id = 1 (llvmpipe (LLVM 17.0.6, 128 bits))
> Layer-Device Extensions: count = 0
>
> Device Properties and Extensions:
> =================================
> GPU0:
> VkPhysicalDeviceProperties:
> ---------------------------
> apiVersion = 1.0.274 (4194578)
> driverVersion = 24.0.8 (100663304)
> vendorID = 0x1010
> deviceID = 0x6250
> deviceType = PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
> deviceName = Imagination PowerVR Rogue GX6250
> pipelineCacheUUID = 6ddf30eb-d118-41f1-455f-580ae751c27b
>
> VkPhysicalDeviceLimits:
> -----------------------
> maxImageDimension1D = 8192
> maxImageDimension2D = 8192
> maxImageDimension3D = 2048
> maxImageDimensionCube = 8192
> maxImageArrayLayers = 2048
> maxTexelBufferElements = 65536
> maxUniformBufferRange = 134217728
> maxStorageBufferRange = 134217728
> maxPushConstantsSize = 256
> maxMemoryAllocationCount = 4294967295
> maxSamplerAllocationCount = 4294967295
> bufferImageGranularity = 0x00000001
> sparseAddressSpaceSize = 0x4000000000
> maxBoundDescriptorSets = 4
> maxPerStageDescriptorSamplers = 32
> maxPerStageDescriptorUniformBuffers = 64
> maxPerStageDescriptorStorageBuffers = 36
> maxPerStageDescriptorSampledImages = 48
> maxPerStageDescriptorStorageImages = 8
> maxPerStageDescriptorInputAttachments = 8
> maxPerStageResources = 224
> maxDescriptorSetSamplers = 256
> maxDescriptorSetUniformBuffers = 256
> maxDescriptorSetUniformBuffersDynamic = 8
> maxDescriptorSetStorageBuffers = 256
> maxDescriptorSetStorageBuffersDynamic = 8
> maxDescriptorSetSampledImages = 256
> maxDescriptorSetStorageImages = 256
> maxDescriptorSetInputAttachments = 256
> maxVertexInputAttributes = 16
> maxVertexInputBindings = 16
> maxVertexInputAttributeOffset = 65535
> maxVertexInputBindingStride = 2147483648
> maxVertexOutputComponents = 128
> maxTessellationGenerationLevel = 0
> maxTessellationPatchSize = 0
> maxTessellationControlPerVertexInputComponents = 0
> maxTessellationControlPerVertexOutputComponents = 0
> maxTessellationControlPerPatchOutputComponents = 0
> maxTessellationControlTotalOutputComponents = 0
> maxTessellationEvaluationInputComponents = 0
> maxTessellationEvaluationOutputComponents = 0
> maxGeometryShaderInvocations = 0
> maxGeometryInputComponents = 0
> maxGeometryOutputComponents = 0
> maxGeometryOutputVertices = 0
> maxGeometryTotalOutputComponents = 0
> maxFragmentInputComponents = 128
> maxFragmentOutputAttachments = 8
> maxFragmentDualSrcAttachments = 0
> maxFragmentCombinedOutputResources = 52
> maxComputeSharedMemorySize = 16384
> maxComputeWorkGroupCount: count = 3
> 65536
> 65536
> 65536
> maxComputeWorkGroupInvocations = 512
> maxComputeWorkGroupSize: count = 3
> 512
> 512
> 64
> subPixelPrecisionBits = 8
> subTexelPrecisionBits = 8
> mipmapPrecisionBits = 8
> maxDrawIndexedIndexValue = 4294967295
> maxDrawIndirectCount = 2147483648
> maxSamplerLodBias = 16
> maxSamplerAnisotropy = 1
> maxViewports = 1
> maxViewportDimensions: count = 2
> 8192
> 8192
> viewportBoundsRange: count = 2
> -16384
> 16384
> viewportSubPixelBits = 0
> minMemoryMapAlignment = 64
> minTexelBufferOffsetAlignment = 0x00000010
> minUniformBufferOffsetAlignment = 0x00000004
> minStorageBufferOffsetAlignment = 0x00000004
> minTexelOffset = -8
> maxTexelOffset = 7
> minTexelGatherOffset = -8
> maxTexelGatherOffset = 7
> minInterpolationOffset = -0.5
> maxInterpolationOffset = 0.5
> subPixelInterpolationOffsetBits = 4
> maxFramebufferWidth = 8192
> maxFramebufferHeight = 8192
> maxFramebufferLayers = 2048
> framebufferColorSampleCounts: count = 4
> SAMPLE_COUNT_1_BIT
> SAMPLE_COUNT_2_BIT
> SAMPLE_COUNT_4_BIT
> SAMPLE_COUNT_8_BIT
> framebufferDepthSampleCounts: count = 4
> SAMPLE_COUNT_1_BIT
> SAMPLE_COUNT_2_BIT
> SAMPLE_COUNT_4_BIT
> SAMPLE_COUNT_8_BIT
> framebufferStencilSampleCounts: count = 4
> SAMPLE_COUNT_1_BIT
> SAMPLE_COUNT_2_BIT
> SAMPLE_COUNT_4_BIT
> SAMPLE_COUNT_8_BIT
> framebufferNoAttachmentsSampleCounts: count = 4
> SAMPLE_COUNT_1_BIT
> SAMPLE_COUNT_2_BIT
> SAMPLE_COUNT_4_BIT
> SAMPLE_COUNT_8_BIT
> maxColorAttachments = 8
> sampledImageColorSampleCounts: count = 4
> SAMPLE_COUNT_1_BIT
> SAMPLE_COUNT_2_BIT
> SAMPLE_COUNT_4_BIT
> SAMPLE_COUNT_8_BIT
> sampledImageIntegerSampleCounts: count = 4
> SAMPLE_COUNT_1_BIT
> SAMPLE_COUNT_2_BIT
> SAMPLE_COUNT_4_BIT
> SAMPLE_COUNT_8_BIT
> sampledImageDepthSampleCounts: count = 4
> SAMPLE_COUNT_1_BIT
> SAMPLE_COUNT_2_BIT
> SAMPLE_COUNT_4_BIT
> SAMPLE_COUNT_8_BIT
> sampledImageStencilSampleCounts: count = 4
> SAMPLE_COUNT_1_BIT
> SAMPLE_COUNT_2_BIT
> SAMPLE_COUNT_4_BIT
> SAMPLE_COUNT_8_BIT
> storageImageSampleCounts: count = 4
> SAMPLE_COUNT_1_BIT
> SAMPLE_COUNT_2_BIT
> SAMPLE_COUNT_4_BIT
> SAMPLE_COUNT_8_BIT
> maxSampleMaskWords = 1
> timestampComputeAndGraphics = false
> timestampPeriod = 0
> maxClipDistances = 8
> maxCullDistances = 8
> maxCombinedClipAndCullDistances = 8
> discreteQueuePriorities = 2
> pointSizeRange: count = 2
> 1
> 511
> lineWidthRange: count = 2
> 0.0625
> 16
> pointSizeGranularity = 0.0625
> lineWidthGranularity = 0.0625
> strictLines = false
> standardSampleLocations = true
> optimalBufferCopyOffsetAlignment = 0x00000004
> optimalBufferCopyRowPitchAlignment = 0x00000004
> nonCoherentAtomSize = 0x00000001
>
> VkPhysicalDeviceSparseProperties:
> ---------------------------------
> residencyStandard2DBlockShape = false
> residencyStandard2DMultisampleBlockShape = false
> residencyStandard3DBlockShape = false
> residencyAlignedMipSize = false
> residencyNonResidentStrict = false
>
> VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT:
> --------------------------------------------------
> storageTexelBufferOffsetAlignmentBytes = 0x00000010
> storageTexelBufferOffsetSingleTexelAlignment = true
> uniformTexelBufferOffsetAlignmentBytes = 0x00000010
> uniformTexelBufferOffsetSingleTexelAlignment = false
>
> VkPhysicalDeviceTimelineSemaphorePropertiesKHR:
> -----------------------------------------------
> maxTimelineSemaphoreValueDifference = 18446744073709551615
>
> Device Extensions: count = 20
> VK_EXT_external_memory_dma_buf : extension revision 1
> VK_EXT_host_query_reset : extension revision 1
> VK_EXT_private_data : extension revision 1
> VK_EXT_scalar_block_layout : extension revision 1
> VK_EXT_texel_buffer_alignment : extension revision 1
> VK_EXT_tooling_info : extension revision 1
> VK_KHR_bind_memory2 : extension revision 1
> VK_KHR_copy_commands2 : extension revision 1
> VK_KHR_external_fence : extension revision 1
> VK_KHR_external_fence_fd : extension revision 1
> VK_KHR_external_memory : extension revision 1
> VK_KHR_external_memory_fd : extension revision 1
> VK_KHR_external_semaphore : extension revision 1
> VK_KHR_external_semaphore_fd : extension revision 1
> VK_KHR_format_feature_flags2 : extension revision 2
> VK_KHR_get_memory_requirements2 : extension revision 1
> VK_KHR_image_format_list : extension revision 1
> VK_KHR_swapchain : extension revision 70
> VK_KHR_timeline_semaphore : extension revision 2
> VK_KHR_uniform_buffer_standard_layout : extension revision 1
>
> VkQueueFamilyProperties:
> ========================
> queueProperties[0]:
> -------------------
> minImageTransferGranularity = (1,1,1)
> queueCount = 2
> queueFlags = QUEUE_GRAPHICS_BIT | QUEUE_COMPUTE_BIT | QUEUE_TRANSFER_BIT
> timestampValidBits = 0
> present support = false
>
> VkPhysicalDeviceMemoryProperties:
> =================================
> memoryHeaps: count = 1
> memoryHeaps[0]:
> size = 1752969216 (0x687c3000) (1.63 GiB)
> flags: count = 1
> MEMORY_HEAP_DEVICE_LOCAL_BIT
> memoryTypes: count = 1
> memoryTypes[0]:
> heapIndex = 0
> propertyFlags = 0x0007: count = 3
> MEMORY_PROPERTY_DEVICE_LOCAL_BIT
> MEMORY_PROPERTY_HOST_VISIBLE_BIT
> MEMORY_PROPERTY_HOST_COHERENT_BIT
> usable for:
> IMAGE_TILING_OPTIMAL:
> color images
> FORMAT_D16_UNORM
> FORMAT_D32_SFLOAT
> FORMAT_S8_UINT
> FORMAT_D24_UNORM_S8_UINT
> (non-sparse)
> IMAGE_TILING_LINEAR:
> color images
> (non-sparse)
>
> VkPhysicalDeviceFeatures:
> =========================
> robustBufferAccess = true
> fullDrawIndexUint32 = true
> imageCubeArray = true
> independentBlend = false
> geometryShader = false
> tessellationShader = false
> sampleRateShading = true
> dualSrcBlend = false
> logicOp = false
> multiDrawIndirect = true
> drawIndirectFirstInstance = true
> depthClamp = true
> depthBiasClamp = true
> fillModeNonSolid = false
> depthBounds = false
> wideLines = true
> largePoints = true
> alphaToOne = false
> multiViewport = false
> samplerAnisotropy = false
> textureCompressionETC2 = true
> textureCompressionASTC_LDR = false
> textureCompressionBC = false
> occlusionQueryPrecise = false
> pipelineStatisticsQuery = false
> vertexPipelineStoresAndAtomics = true
> fragmentStoresAndAtomics = true
> shaderTessellationAndGeometryPointSize = false
> shaderImageGatherExtended = false
> shaderStorageImageExtendedFormats = true
> shaderStorageImageMultisample = false
> shaderStorageImageReadWithoutFormat = true
> shaderStorageImageWriteWithoutFormat = false
> shaderUniformBufferArrayDynamicIndexing = true
> shaderSampledImageArrayDynamicIndexing = true
> shaderStorageBufferArrayDynamicIndexing = true
> shaderStorageImageArrayDynamicIndexing = true
> shaderClipDistance = false
> shaderCullDistance = false
> shaderFloat64 = false
> shaderInt64 = true
> shaderInt16 = true
> shaderResourceResidency = false
> shaderResourceMinLod = false
> sparseBinding = false
> sparseResidencyBuffer = false
> sparseResidencyImage2D = false
> sparseResidencyImage3D = false
> sparseResidency2Samples = false
> sparseResidency4Samples = false
> sparseResidency8Samples = false
> sparseResidency16Samples = false
> sparseResidencyAliased = false
> variableMultisampleRate = false
> inheritedQueries = false
>
> VkPhysicalDeviceHostQueryResetFeaturesEXT:
> ------------------------------------------
> hostQueryReset = true
>
> VkPhysicalDevicePrivateDataFeaturesEXT:
> ---------------------------------------
> privateData = true
>
> VkPhysicalDeviceScalarBlockLayoutFeaturesEXT:
> ---------------------------------------------
> scalarBlockLayout = true
>
> VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT:
> ------------------------------------------------
> texelBufferAlignment = true
>
> VkPhysicalDeviceTimelineSemaphoreFeaturesKHR:
> ---------------------------------------------
> timelineSemaphore = true
>
> VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR:
> -------------------------------------------------------
> uniformBufferStandardLayout = true
>
>
> GPU1:
> VkPhysicalDeviceProperties:
> ---------------------------
> apiVersion = 1.3.274 (4206866)
> driverVersion = 0.0.1 (1)
> vendorID = 0x10005
> deviceID = 0x0000
> deviceType = PHYSICAL_DEVICE_TYPE_CPU
> deviceName = llvmpipe (LLVM 17.0.6, 128 bits)
> pipelineCacheUUID = 32342e30-2e38-2d31-2b70-316161616161
>
> VkPhysicalDeviceLimits:
> -----------------------
> maxImageDimension1D = 16384
> maxImageDimension2D = 16384
> maxImageDimension3D = 4096
> maxImageDimensionCube = 32768
> maxImageArrayLayers = 2048
> maxTexelBufferElements = 134217728
> maxUniformBufferRange = 65536
> maxStorageBufferRange = 134217728
> maxPushConstantsSize = 256
> maxMemoryAllocationCount = 4294967295
> maxSamplerAllocationCount = 32768
> bufferImageGranularity = 0x00000040
> sparseAddressSpaceSize = 0x00000000
> maxBoundDescriptorSets = 8
> maxPerStageDescriptorSamplers = 1000000
> maxPerStageDescriptorUniformBuffers = 1000000
> maxPerStageDescriptorStorageBuffers = 1000000
> maxPerStageDescriptorSampledImages = 1000000
> maxPerStageDescriptorStorageImages = 1000000
> maxPerStageDescriptorInputAttachments = 1000000
> maxPerStageResources = 1000000
> maxDescriptorSetSamplers = 1000000
> maxDescriptorSetUniformBuffers = 1000000
> maxDescriptorSetUniformBuffersDynamic = 1000000
> maxDescriptorSetStorageBuffers = 1000000
> maxDescriptorSetStorageBuffersDynamic = 1000000
> maxDescriptorSetSampledImages = 1000000
> maxDescriptorSetStorageImages = 1000000
> maxDescriptorSetInputAttachments = 1000000
> maxVertexInputAttributes = 32
> maxVertexInputBindings = 32
> maxVertexInputAttributeOffset = 2047
> maxVertexInputBindingStride = 2048
> maxVertexOutputComponents = 128
> maxTessellationGenerationLevel = 64
> maxTessellationPatchSize = 32
> maxTessellationControlPerVertexInputComponents = 128
> maxTessellationControlPerVertexOutputComponents = 128
> maxTessellationControlPerPatchOutputComponents = 128
> maxTessellationControlTotalOutputComponents = 4096
> maxTessellationEvaluationInputComponents = 128
> maxTessellationEvaluationOutputComponents = 128
> maxGeometryShaderInvocations = 32
> maxGeometryInputComponents = 64
> maxGeometryOutputComponents = 128
> maxGeometryOutputVertices = 1024
> maxGeometryTotalOutputComponents = 1024
> maxFragmentInputComponents = 128
> maxFragmentOutputAttachments = 8
> maxFragmentDualSrcAttachments = 2
> maxFragmentCombinedOutputResources = 104
> maxComputeSharedMemorySize = 32768
> maxComputeWorkGroupCount: count = 3
> 65535
> 65535
> 65535
> maxComputeWorkGroupInvocations = 1024
> maxComputeWorkGroupSize: count = 3
> 1024
> 1024
> 1024
> subPixelPrecisionBits = 8
> subTexelPrecisionBits = 8
> mipmapPrecisionBits = 4
> maxDrawIndexedIndexValue = 4294967295
> maxDrawIndirectCount = 4294967295
> maxSamplerLodBias = 16
> maxSamplerAnisotropy = 16
> maxViewports = 16
> maxViewportDimensions: count = 2
> 16384
> 16384
> viewportBoundsRange: count = 2
> -32768
> 32768
> viewportSubPixelBits = 0
> minMemoryMapAlignment = 64
> minTexelBufferOffsetAlignment = 0x00000010
> minUniformBufferOffsetAlignment = 0x00000010
> minStorageBufferOffsetAlignment = 0x00000010
> minTexelOffset = -32
> maxTexelOffset = 31
> minTexelGatherOffset = -32
> maxTexelGatherOffset = 31
> minInterpolationOffset = -2
> maxInterpolationOffset = 2
> subPixelInterpolationOffsetBits = 8
> maxFramebufferWidth = 16384
> maxFramebufferHeight = 16384
> maxFramebufferLayers = 2048
> framebufferColorSampleCounts: count = 2
> SAMPLE_COUNT_1_BIT
> SAMPLE_COUNT_4_BIT
> framebufferDepthSampleCounts: count = 2
> SAMPLE_COUNT_1_BIT
> SAMPLE_COUNT_4_BIT
> framebufferStencilSampleCounts: count = 2
> SAMPLE_COUNT_1_BIT
> SAMPLE_COUNT_4_BIT
> framebufferNoAttachmentsSampleCounts: count = 2
> SAMPLE_COUNT_1_BIT
> SAMPLE_COUNT_4_BIT
> maxColorAttachments = 8
> sampledImageColorSampleCounts: count = 2
> SAMPLE_COUNT_1_BIT
> SAMPLE_COUNT_4_BIT
> sampledImageIntegerSampleCounts: count = 2
> SAMPLE_COUNT_1_BIT
> SAMPLE_COUNT_4_BIT
> sampledImageDepthSampleCounts: count = 2
> SAMPLE_COUNT_1_BIT
> SAMPLE_COUNT_4_BIT
> sampledImageStencilSampleCounts: count = 2
> SAMPLE_COUNT_1_BIT
> SAMPLE_COUNT_4_BIT
> storageImageSampleCounts: count = 2
> SAMPLE_COUNT_1_BIT
> SAMPLE_COUNT_4_BIT
> maxSampleMaskWords = 1
> timestampComputeAndGraphics = true
> timestampPeriod = 1
> maxClipDistances = 8
> maxCullDistances = 8
> maxCombinedClipAndCullDistances = 8
> discreteQueuePriorities = 2
> pointSizeRange: count = 2
> 0
> 255
> lineWidthRange: count = 2
> 1
> 255
> pointSizeGranularity = 0.125
> lineWidthGranularity = 0.0078125
> strictLines = true
> standardSampleLocations = true
> optimalBufferCopyOffsetAlignment = 0x00000080
> optimalBufferCopyRowPitchAlignment = 0x00000080
> nonCoherentAtomSize = 0x00000040
>
> VkPhysicalDeviceSparseProperties:
> ---------------------------------
> residencyStandard2DBlockShape = false
> residencyStandard2DMultisampleBlockShape = false
> residencyStandard3DBlockShape = false
> residencyAlignedMipSize = false
> residencyNonResidentStrict = false
>
> VkPhysicalDeviceCustomBorderColorPropertiesEXT:
> -----------------------------------------------
> maxCustomBorderColorSamplers = 32768
>
> VkPhysicalDeviceDescriptorBufferDensityMapPropertiesEXT:
> --------------------------------------------------------
> combinedImageSamplerDensityMapDescriptorSize = 0
>
> VkPhysicalDeviceDescriptorBufferPropertiesEXT:
> ----------------------------------------------
> combinedImageSamplerDescriptorSingleArray = true
> bufferlessPushDescriptors = true
> allowSamplerImageViewPostSubmitCreation = false
> descriptorBufferOffsetAlignment = 0x00000004
> maxDescriptorBufferBindings = 8
> maxResourceDescriptorBufferBindings = 8
> maxSamplerDescriptorBufferBindings = 8
> maxEmbeddedImmutableSamplerBindings = 8
> maxEmbeddedImmutableSamplers = 2032
> bufferCaptureReplayDescriptorDataSize = 0
> imageCaptureReplayDescriptorDataSize = 0
> imageViewCaptureReplayDescriptorDataSize = 0
> samplerCaptureReplayDescriptorDataSize = 0
> accelerationStructureCaptureReplayDescriptorDataSize = 0
> samplerDescriptorSize = 256
> combinedImageSamplerDescriptorSize = 256
> sampledImageDescriptorSize = 256
> storageImageDescriptorSize = 256
> uniformTexelBufferDescriptorSize = 256
> robustUniformTexelBufferDescriptorSize = 256
> storageTexelBufferDescriptorSize = 256
> robustStorageTexelBufferDescriptorSize = 256
> uniformBufferDescriptorSize = 256
> robustUniformBufferDescriptorSize = 256
> storageBufferDescriptorSize = 256
> robustStorageBufferDescriptorSize = 256
> inputAttachmentDescriptorSize = 256
> accelerationStructureDescriptorSize = 0
> maxSamplerDescriptorBufferRange = 0x08000000
> maxResourceDescriptorBufferRange = 0x10000000
> samplerDescriptorBufferAddressSpaceSize = 0x08000000
> resourceDescriptorBufferAddressSpaceSize = 0x08000000
> descriptorBufferAddressSpaceSize = 0x08000000
>
> VkPhysicalDeviceExtendedDynamicState3PropertiesEXT:
> ---------------------------------------------------
> dynamicPrimitiveTopologyUnrestricted = true
>
> VkPhysicalDeviceExternalMemoryHostPropertiesEXT:
> ------------------------------------------------
> minImportedHostPointerAlignment = 0x00001000
>
> VkPhysicalDeviceGraphicsPipelineLibraryPropertiesEXT:
> -----------------------------------------------------
> graphicsPipelineLibraryFastLinking = true
> graphicsPipelineLibraryIndependentInterpolationDecoration = true
>
> VkPhysicalDeviceLineRasterizationPropertiesKHR:
> -----------------------------------------------
> lineSubPixelPrecisionBits = 8
>
> VkPhysicalDeviceMaintenance5PropertiesKHR:
> ------------------------------------------
> earlyFragmentMultisampleCoverageAfterSampleCounting = true
> earlyFragmentSampleMaskTestBeforeSampleCounting = false
> depthStencilSwizzleOneSupport = false
> polygonModePointSize = true
> nonStrictSinglePixelWideLinesUseParallelogram = false
> nonStrictWideLinesUseParallelogram = false
>
> VkPhysicalDeviceMaintenance6PropertiesKHR:
> ------------------------------------------
> blockTexelViewCompatibleMultipleLayers = true
> maxCombinedImageSamplerDescriptorCount = 3
> fragmentShadingRateClampCombinerInputs = false
>
> VkPhysicalDeviceMeshShaderPropertiesEXT:
> ----------------------------------------
> maxTaskWorkGroupTotalCount = 4194304
> maxTaskWorkGroupCount: count = 3
> 65536
> 65536
> 65536
> maxTaskWorkGroupInvocations = 1024
> maxTaskWorkGroupSize: count = 3
> 1024
> 1024
> 1024
> maxTaskPayloadSize = 16384
> maxTaskSharedMemorySize = 32768
> maxTaskPayloadAndSharedMemorySize = 32768
> maxMeshWorkGroupTotalCount = 4194304
> maxMeshWorkGroupCount: count = 3
> 65536
> 65536
> 65536
> maxMeshWorkGroupInvocations = 1024
> maxMeshWorkGroupSize: count = 3
> 1024
> 1024
> 1024
> maxMeshSharedMemorySize = 28672
> maxMeshPayloadAndSharedMemorySize = 45056
> maxMeshOutputMemorySize = 32768
> maxMeshPayloadAndOutputMemorySize = 49152
> maxMeshOutputComponents = 128
> maxMeshOutputVertices = 256
> maxMeshOutputPrimitives = 256
> maxMeshOutputLayers = 8
> maxMeshMultiviewViewCount = 0
> meshOutputPerVertexGranularity = 1
> meshOutputPerPrimitiveGranularity = 1
> maxPreferredTaskWorkGroupInvocations = 64
> maxPreferredMeshWorkGroupInvocations = 128
> prefersLocalInvocationVertexOutput = true
> prefersLocalInvocationPrimitiveOutput = true
> prefersCompactVertexOutput = true
> prefersCompactPrimitiveOutput = false
>
> VkPhysicalDeviceMultiDrawPropertiesEXT:
> ---------------------------------------
> maxMultiDrawCount = 2048
>
> VkPhysicalDeviceNestedCommandBufferPropertiesEXT:
> -------------------------------------------------
> maxCommandBufferNestingLevel = 4294967295
>
> VkPhysicalDeviceProvokingVertexPropertiesEXT:
> ---------------------------------------------
> provokingVertexModePerPipeline = true
> transformFeedbackPreservesTriangleFanProvokingVertex = true
>
> VkPhysicalDevicePushDescriptorPropertiesKHR:
> --------------------------------------------
> maxPushDescriptors = 32
>
> VkPhysicalDeviceRobustness2PropertiesEXT:
> -----------------------------------------
> robustStorageBufferAccessSizeAlignment = 0x00000001
> robustUniformBufferAccessSizeAlignment = 0x00000001
>
> VkPhysicalDeviceShaderObjectPropertiesEXT:
> ------------------------------------------
> shaderBinaryUUID = 32342e30-2e38-2d31-2b70-316161616161
> shaderBinaryVersion = 1
>
> VkPhysicalDeviceTransformFeedbackPropertiesEXT:
> -----------------------------------------------
> maxTransformFeedbackStreams = 4
> maxTransformFeedbackBuffers = 4
> maxTransformFeedbackBufferSize = 0xffffffff
> maxTransformFeedbackStreamDataSize = 512
> maxTransformFeedbackBufferDataSize = 512
> maxTransformFeedbackBufferDataStride = 512
> transformFeedbackQueries = true
> transformFeedbackStreamsLinesTriangles = false
> transformFeedbackRasterizationStreamSelect = false
> transformFeedbackDraw = true
>
> VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT:
> ----------------------------------------------------
> maxVertexAttribDivisor = 4294967295
>
> VkPhysicalDeviceVulkan11Properties:
> -----------------------------------
> deviceUUID = 6d657361-3234-2e30-2e38-2d312b703100
> driverUUID = 6c6c766d-7069-7065-5555-494400000000
> deviceNodeMask = 0
> deviceLUIDValid = false
> subgroupSize = 4
> subgroupSupportedStages: count = 4
> SHADER_STAGE_FRAGMENT_BIT
> SHADER_STAGE_COMPUTE_BIT
> SHADER_STAGE_TASK_BIT_EXT
> SHADER_STAGE_MESH_BIT_EXT
> subgroupSupportedOperations: count = 7
> SUBGROUP_FEATURE_BASIC_BIT
> SUBGROUP_FEATURE_VOTE_BIT
> SUBGROUP_FEATURE_ARITHMETIC_BIT
> SUBGROUP_FEATURE_BALLOT_BIT
> SUBGROUP_FEATURE_SHUFFLE_BIT
> SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
> SUBGROUP_FEATURE_QUAD_BIT
> subgroupQuadOperationsInAllStages = false
> pointClippingBehavior = POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
> maxMultiviewViewCount = 6
> maxMultiviewInstanceIndex = 2147483647
> protectedNoFault = false
> maxPerSetDescriptors = 1000000
> maxMemoryAllocationSize = 0x80000000
>
> VkPhysicalDeviceVulkan12Properties:
> -----------------------------------
> driverID = DRIVER_ID_MESA_LLVMPIPE
> driverName = llvmpipe
> driverInfo = Mesa 24.0.8-1+p1 (LLVM 17.0.6)
> conformanceVersion:
> major = 1
> minor = 3
> subminor = 1
> patch = 1
> denormBehaviorIndependence = SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL
> roundingModeIndependence = SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL
> shaderSignedZeroInfNanPreserveFloat16 = true
> shaderSignedZeroInfNanPreserveFloat32 = true
> shaderSignedZeroInfNanPreserveFloat64 = true
> shaderDenormPreserveFloat16 = false
> shaderDenormPreserveFloat32 = false
> shaderDenormPreserveFloat64 = false
> shaderDenormFlushToZeroFloat16 = false
> shaderDenormFlushToZeroFloat32 = false
> shaderDenormFlushToZeroFloat64 = false
> shaderRoundingModeRTEFloat16 = true
> shaderRoundingModeRTEFloat32 = true
> shaderRoundingModeRTEFloat64 = true
> shaderRoundingModeRTZFloat16 = false
> shaderRoundingModeRTZFloat32 = false
> shaderRoundingModeRTZFloat64 = false
> maxUpdateAfterBindDescriptorsInAllPools = 4294967295
> shaderUniformBufferArrayNonUniformIndexingNative = true
> shaderSampledImageArrayNonUniformIndexingNative = true
> shaderStorageBufferArrayNonUniformIndexingNative = true
> shaderStorageImageArrayNonUniformIndexingNative = true
> shaderInputAttachmentArrayNonUniformIndexingNative = true
> robustBufferAccessUpdateAfterBind = true
> quadDivergentImplicitLod = true
> maxPerStageDescriptorUpdateAfterBindSamplers = 1000000
> maxPerStageDescriptorUpdateAfterBindUniformBuffers = 1000000
> maxPerStageDescriptorUpdateAfterBindStorageBuffers = 1000000
> maxPerStageDescriptorUpdateAfterBindSampledImages = 1000000
> maxPerStageDescriptorUpdateAfterBindStorageImages = 1000000
> maxPerStageDescriptorUpdateAfterBindInputAttachments = 1000000
> maxPerStageUpdateAfterBindResources = 1000000
> maxDescriptorSetUpdateAfterBindSamplers = 1000000
> maxDescriptorSetUpdateAfterBindUniformBuffers = 1000000
> maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = 1000000
> maxDescriptorSetUpdateAfterBindStorageBuffers = 1000000
> maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = 1000000
> maxDescriptorSetUpdateAfterBindSampledImages = 1000000
> maxDescriptorSetUpdateAfterBindStorageImages = 1000000
> maxDescriptorSetUpdateAfterBindInputAttachments = 1000000
> supportedDepthResolveModes: count = 2
> RESOLVE_MODE_SAMPLE_ZERO_BIT
> RESOLVE_MODE_AVERAGE_BIT
> supportedStencilResolveModes: count = 1
> RESOLVE_MODE_SAMPLE_ZERO_BIT
> independentResolveNone = false
> independentResolve = false
> filterMinmaxSingleComponentFormats = true
> filterMinmaxImageComponentMapping = true
> maxTimelineSemaphoreValueDifference = 18446744073709551615
> framebufferIntegerColorSampleCounts: count = 1
> SAMPLE_COUNT_1_BIT
>
> VkPhysicalDeviceVulkan13Properties:
> -----------------------------------
> minSubgroupSize = 4
> maxSubgroupSize = 4
> maxComputeWorkgroupSubgroups = 32
> requiredSubgroupSizeStages: count = 2
> SHADER_STAGE_FRAGMENT_BIT
> SHADER_STAGE_COMPUTE_BIT
> maxInlineUniformBlockSize = 4096
> maxPerStageDescriptorInlineUniformBlocks = 8
> maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = 8
> maxDescriptorSetInlineUniformBlocks = 8
> maxDescriptorSetUpdateAfterBindInlineUniformBlocks = 8
> maxInlineUniformTotalSize = 262144
> integerDotProduct8BitUnsignedAccelerated = false
> integerDotProduct8BitSignedAccelerated = false
> integerDotProduct8BitMixedSignednessAccelerated = false
> integerDotProduct4x8BitPackedUnsignedAccelerated = false
> integerDotProduct4x8BitPackedSignedAccelerated = false
> integerDotProduct4x8BitPackedMixedSignednessAccelerated = false
> integerDotProduct16BitUnsignedAccelerated = false
> integerDotProduct16BitSignedAccelerated = false
> integerDotProduct16BitMixedSignednessAccelerated = false
> integerDotProduct32BitUnsignedAccelerated = false
> integerDotProduct32BitSignedAccelerated = false
> integerDotProduct32BitMixedSignednessAccelerated = false
> integerDotProduct64BitUnsignedAccelerated = false
> integerDotProduct64BitSignedAccelerated = false
> integerDotProduct64BitMixedSignednessAccelerated = false
> integerDotProductAccumulatingSaturating8BitUnsignedAccelerated = false
> integerDotProductAccumulatingSaturating8BitSignedAccelerated = false
> integerDotProductAccumulatingSaturating8BitMixedSignednessAccelerated = false
> integerDotProductAccumulatingSaturating4x8BitPackedUnsignedAccelerated = false
> integerDotProductAccumulatingSaturating4x8BitPackedSignedAccelerated = false
> integerDotProductAccumulatingSaturating4x8BitPackedMixedSignednessAccelerated = false
> integerDotProductAccumulatingSaturating16BitUnsignedAccelerated = false
> integerDotProductAccumulatingSaturating16BitSignedAccelerated = false
> integerDotProductAccumulatingSaturating16BitMixedSignednessAccelerated = false
> integerDotProductAccumulatingSaturating32BitUnsignedAccelerated = false
> integerDotProductAccumulatingSaturating32BitSignedAccelerated = false
> integerDotProductAccumulatingSaturating32BitMixedSignednessAccelerated = false
> integerDotProductAccumulatingSaturating64BitUnsignedAccelerated = false
> integerDotProductAccumulatingSaturating64BitSignedAccelerated = false
> integerDotProductAccumulatingSaturating64BitMixedSignednessAccelerated = false
> storageTexelBufferOffsetAlignmentBytes = 0x00000010
> storageTexelBufferOffsetSingleTexelAlignment = true
> uniformTexelBufferOffsetAlignmentBytes = 0x00000010
> uniformTexelBufferOffsetSingleTexelAlignment = true
> maxBufferSize = 0xffffffff
>
> VkPhysicalDeviceHostImageCopyPropertiesEXT:
> -------------------------------------------
> copySrcLayoutCount = 23
> pCopySrcLayouts: count = 23
> IMAGE_LAYOUT_GENERAL
> IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
> IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
> IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
> IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
> IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
> IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
> IMAGE_LAYOUT_PREINITIALIZED
> IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
> IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL
> IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL
> IMAGE_LAYOUT_DEPTH_READ_ONLY_OPTIMAL
> IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL
> IMAGE_LAYOUT_STENCIL_READ_ONLY_OPTIMAL
> IMAGE_LAYOUT_READ_ONLY_OPTIMAL
> IMAGE_LAYOUT_ATTACHMENT_OPTIMAL
> IMAGE_LAYOUT_PRESENT_SRC_KHR
> IMAGE_LAYOUT_VIDEO_DECODE_DST_KHR
> IMAGE_LAYOUT_VIDEO_DECODE_SRC_KHR
> IMAGE_LAYOUT_VIDEO_DECODE_DPB_KHR
> IMAGE_LAYOUT_SHARED_PRESENT_KHR
> IMAGE_LAYOUT_FRAGMENT_DENSITY_MAP_OPTIMAL_EXT
> IMAGE_LAYOUT_FRAGMENT_SHADING_RATE_ATTACHMENT_OPTIMAL_KHR
> copyDstLayoutCount = 23
> pCopyDstLayouts: count = 23
> IMAGE_LAYOUT_GENERAL
> IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
> IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
> IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
> IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
> IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
> IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
> IMAGE_LAYOUT_PREINITIALIZED
> IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
> IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL
> IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL
> IMAGE_LAYOUT_DEPTH_READ_ONLY_OPTIMAL
> IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL
> IMAGE_LAYOUT_STENCIL_READ_ONLY_OPTIMAL
> IMAGE_LAYOUT_READ_ONLY_OPTIMAL
> IMAGE_LAYOUT_ATTACHMENT_OPTIMAL
> IMAGE_LAYOUT_PRESENT_SRC_KHR
> IMAGE_LAYOUT_VIDEO_DECODE_DST_KHR
> IMAGE_LAYOUT_VIDEO_DECODE_SRC_KHR
> IMAGE_LAYOUT_VIDEO_DECODE_DPB_KHR
> IMAGE_LAYOUT_SHARED_PRESENT_KHR
> IMAGE_LAYOUT_FRAGMENT_DENSITY_MAP_OPTIMAL_EXT
> IMAGE_LAYOUT_FRAGMENT_SHADING_RATE_ATTACHMENT_OPTIMAL_KHR
> optimalTilingLayoutUUID = 32342e30-2e38-2d31-2b70-316161616161
> identicalMemoryTypeRequirements = false
>
> Device Extensions: count = 124
> VK_AMDX_shader_enqueue : extension revision 1
> VK_ARM_rasterization_order_attachment_access : extension revision 1
> VK_EXT_4444_formats : extension revision 1
> VK_EXT_attachment_feedback_loop_dynamic_state : extension revision 1
> VK_EXT_attachment_feedback_loop_layout : extension revision 2
> VK_EXT_border_color_swizzle : extension revision 1
> VK_EXT_calibrated_timestamps : extension revision 2
> VK_EXT_color_write_enable : extension revision 1
> VK_EXT_conditional_rendering : extension revision 2
> VK_EXT_custom_border_color : extension revision 12
> VK_EXT_depth_clip_control : extension revision 1
> VK_EXT_depth_clip_enable : extension revision 1
> VK_EXT_depth_range_unrestricted : extension revision 1
> VK_EXT_descriptor_buffer : extension revision 1
> VK_EXT_descriptor_indexing : extension revision 2
> VK_EXT_dynamic_rendering_unused_attachments : extension revision 1
> VK_EXT_extended_dynamic_state : extension revision 1
> VK_EXT_extended_dynamic_state2 : extension revision 1
> VK_EXT_extended_dynamic_state3 : extension revision 2
> VK_EXT_external_memory_host : extension revision 1
> VK_EXT_graphics_pipeline_library : extension revision 1
> VK_EXT_host_image_copy : extension revision 1
> VK_EXT_host_query_reset : extension revision 1
> VK_EXT_image_2d_view_of_3d : extension revision 1
> VK_EXT_image_robustness : extension revision 1
> VK_EXT_image_sliced_view_of_3d : extension revision 1
> VK_EXT_index_type_uint8 : extension revision 1
> VK_EXT_inline_uniform_block : extension revision 1
> VK_EXT_line_rasterization : extension revision 1
> VK_EXT_load_store_op_none : extension revision 1
> VK_EXT_memory_budget : extension revision 1
> VK_EXT_memory_priority : extension revision 1
> VK_EXT_mesh_shader : extension revision 1
> VK_EXT_multi_draw : extension revision 1
> VK_EXT_multisampled_render_to_single_sampled : extension revision 1
> VK_EXT_mutable_descriptor_type : extension revision 1
> VK_EXT_nested_command_buffer : extension revision 1
> VK_EXT_non_seamless_cube_map : extension revision 1
> VK_EXT_pageable_device_local_memory : extension revision 1
> VK_EXT_pipeline_creation_cache_control : extension revision 3
> VK_EXT_pipeline_creation_feedback : extension revision 1
> VK_EXT_post_depth_coverage : extension revision 1
> VK_EXT_primitive_topology_list_restart : extension revision 1
> VK_EXT_primitives_generated_query : extension revision 1
> VK_EXT_private_data : extension revision 1
> VK_EXT_provoking_vertex : extension revision 1
> VK_EXT_rasterization_order_attachment_access : extension revision 1
> VK_EXT_robustness2 : extension revision 1
> VK_EXT_sampler_filter_minmax : extension revision 2
> VK_EXT_scalar_block_layout : extension revision 1
> VK_EXT_separate_stencil_usage : extension revision 1
> VK_EXT_shader_atomic_float : extension revision 1
> VK_EXT_shader_atomic_float2 : extension revision 1
> VK_EXT_shader_demote_to_helper_invocation : extension revision 1
> VK_EXT_shader_object : extension revision 1
> VK_EXT_shader_stencil_export : extension revision 1
> VK_EXT_shader_subgroup_ballot : extension revision 1
> VK_EXT_shader_subgroup_vote : extension revision 1
> VK_EXT_shader_viewport_index_layer : extension revision 1
> VK_EXT_subgroup_size_control : extension revision 2
> VK_EXT_texel_buffer_alignment : extension revision 1
> VK_EXT_transform_feedback : extension revision 1
> VK_EXT_vertex_attribute_divisor : extension revision 3
> VK_EXT_vertex_input_dynamic_state : extension revision 2
> VK_EXT_ycbcr_2plane_444_formats : extension revision 1
> VK_EXT_ycbcr_image_arrays : extension revision 1
> VK_GOOGLE_decorate_string : extension revision 1
> VK_GOOGLE_hlsl_functionality1 : extension revision 1
> VK_KHR_16bit_storage : extension revision 1
> VK_KHR_8bit_storage : extension revision 1
> VK_KHR_bind_memory2 : extension revision 1
> VK_KHR_buffer_device_address : extension revision 1
> VK_KHR_copy_commands2 : extension revision 1
> VK_KHR_create_renderpass2 : extension revision 1
> VK_KHR_dedicated_allocation : extension revision 3
> VK_KHR_depth_stencil_resolve : extension revision 1
> VK_KHR_descriptor_update_template : extension revision 1
> VK_KHR_device_group : extension revision 4
> VK_KHR_draw_indirect_count : extension revision 1
> VK_KHR_driver_properties : extension revision 1
> VK_KHR_dynamic_rendering : extension revision 1
> VK_KHR_external_fence : extension revision 1
> VK_KHR_external_memory : extension revision 1
> VK_KHR_external_memory_fd : extension revision 1
> VK_KHR_external_semaphore : extension revision 1
> VK_KHR_format_feature_flags2 : extension revision 2
> VK_KHR_get_memory_requirements2 : extension revision 1
> VK_KHR_image_format_list : extension revision 1
> VK_KHR_imageless_framebuffer : extension revision 1
> VK_KHR_incremental_present : extension revision 2
> VK_KHR_maintenance1 : extension revision 2
> VK_KHR_maintenance2 : extension revision 1
> VK_KHR_maintenance3 : extension revision 1
> VK_KHR_maintenance4 : extension revision 2
> VK_KHR_maintenance5 : extension revision 1
> VK_KHR_maintenance6 : extension revision 1
> VK_KHR_map_memory2 : extension revision 1
> VK_KHR_multiview : extension revision 1
> VK_KHR_pipeline_library : extension revision 1
> VK_KHR_push_descriptor : extension revision 2
> VK_KHR_relaxed_block_layout : extension revision 1
> VK_KHR_sampler_mirror_clamp_to_edge : extension revision 3
> VK_KHR_sampler_ycbcr_conversion : extension revision 14
> VK_KHR_separate_depth_stencil_layouts : extension revision 1
> VK_KHR_shader_atomic_int64 : extension revision 1
> VK_KHR_shader_clock : extension revision 1
> VK_KHR_shader_draw_parameters : extension revision 1
> VK_KHR_shader_float16_int8 : extension revision 1
> VK_KHR_shader_float_controls : extension revision 4
> VK_KHR_shader_integer_dot_product : extension revision 1
> VK_KHR_shader_non_semantic_info : extension revision 1
> VK_KHR_shader_subgroup_extended_types : extension revision 1
> VK_KHR_shader_terminate_invocation : extension revision 1
> VK_KHR_spirv_1_4 : extension revision 1
> VK_KHR_storage_buffer_storage_class : extension revision 1
> VK_KHR_swapchain : extension revision 70
> VK_KHR_swapchain_mutable_format : extension revision 1
> VK_KHR_synchronization2 : extension revision 1
> VK_KHR_timeline_semaphore : extension revision 2
> VK_KHR_uniform_buffer_standard_layout : extension revision 1
> VK_KHR_variable_pointers : extension revision 1
> VK_KHR_vulkan_memory_model : extension revision 3
> VK_KHR_zero_initialize_workgroup_memory : extension revision 1
> VK_NV_device_generated_commands : extension revision 3
>
> VkQueueFamilyProperties:
> ========================
> queueProperties[0]:
> -------------------
> minImageTransferGranularity = (1,1,1)
> queueCount = 1
> queueFlags = QUEUE_GRAPHICS_BIT | QUEUE_COMPUTE_BIT | QUEUE_TRANSFER_BIT
> timestampValidBits = 64
> present support = false
>
> VkPhysicalDeviceMemoryProperties:
> =================================
> memoryHeaps: count = 1
> memoryHeaps[0]:
> size = 3505938432 (0xd0f86000) (3.27 GiB)
> budget = 3505938432 (0xd0f86000) (3.27 GiB)
> usage = 522092544 (0x1f1e8000) (497.91 MiB)
> flags: count = 1
> MEMORY_HEAP_DEVICE_LOCAL_BIT
> memoryTypes: count = 1
> memoryTypes[0]:
> heapIndex = 0
> propertyFlags = 0x000f: count = 4
> MEMORY_PROPERTY_DEVICE_LOCAL_BIT
> MEMORY_PROPERTY_HOST_VISIBLE_BIT
> MEMORY_PROPERTY_HOST_COHERENT_BIT
> MEMORY_PROPERTY_HOST_CACHED_BIT
> usable for:
> IMAGE_TILING_OPTIMAL:
> color images
> FORMAT_D16_UNORM
> FORMAT_X8_D24_UNORM_PACK32
> FORMAT_D32_SFLOAT
> FORMAT_S8_UINT
> FORMAT_D24_UNORM_S8_UINT
> FORMAT_D32_SFLOAT_S8_UINT
> (non-sparse)
> IMAGE_TILING_LINEAR:
> color images
> (non-sparse)
>
> VkPhysicalDeviceFeatures:
> =========================
> robustBufferAccess = true
> fullDrawIndexUint32 = true
> imageCubeArray = true
> independentBlend = true
> geometryShader = true
> tessellationShader = true
> sampleRateShading = true
> dualSrcBlend = true
> logicOp = true
> multiDrawIndirect = true
> drawIndirectFirstInstance = true
> depthClamp = true
> depthBiasClamp = true
> fillModeNonSolid = true
> depthBounds = false
> wideLines = true
> largePoints = true
> alphaToOne = true
> multiViewport = true
> samplerAnisotropy = true
> textureCompressionETC2 = false
> textureCompressionASTC_LDR = false
> textureCompressionBC = true
> occlusionQueryPrecise = true
> pipelineStatisticsQuery = true
> vertexPipelineStoresAndAtomics = true
> fragmentStoresAndAtomics = true
> shaderTessellationAndGeometryPointSize = true
> shaderImageGatherExtended = true
> shaderStorageImageExtendedFormats = true
> shaderStorageImageMultisample = true
> shaderStorageImageReadWithoutFormat = true
> shaderStorageImageWriteWithoutFormat = true
> shaderUniformBufferArrayDynamicIndexing = true
> shaderSampledImageArrayDynamicIndexing = true
> shaderStorageBufferArrayDynamicIndexing = true
> shaderStorageImageArrayDynamicIndexing = true
> shaderClipDistance = true
> shaderCullDistance = true
> shaderFloat64 = true
> shaderInt64 = true
> shaderInt16 = true
> shaderResourceResidency = false
> shaderResourceMinLod = false
> sparseBinding = false
> sparseResidencyBuffer = false
> sparseResidencyImage2D = false
> sparseResidencyImage3D = false
> sparseResidency2Samples = false
> sparseResidency4Samples = false
> sparseResidency8Samples = false
> sparseResidency16Samples = false
> sparseResidencyAliased = false
> variableMultisampleRate = false
> inheritedQueries = false
>
> VkPhysicalDevice4444FormatsFeaturesEXT:
> ---------------------------------------
> formatA4R4G4B4 = true
> formatA4B4G4R4 = true
>
> VkPhysicalDeviceAttachmentFeedbackLoopDynamicStateFeaturesEXT:
> --------------------------------------------------------------
> attachmentFeedbackLoopDynamicState = true
>
> VkPhysicalDeviceAttachmentFeedbackLoopLayoutFeaturesEXT:
> --------------------------------------------------------
> attachmentFeedbackLoopLayout = true
>
> VkPhysicalDeviceBorderColorSwizzleFeaturesEXT:
> ----------------------------------------------
> borderColorSwizzle = true
> borderColorSwizzleFromImage = true
>
> VkPhysicalDeviceColorWriteEnableFeaturesEXT:
> --------------------------------------------
> colorWriteEnable = true
>
> VkPhysicalDeviceConditionalRenderingFeaturesEXT:
> ------------------------------------------------
> conditionalRendering = true
> inheritedConditionalRendering = false
>
> VkPhysicalDeviceCustomBorderColorFeaturesEXT:
> ---------------------------------------------
> customBorderColors = true
> customBorderColorWithoutFormat = true
>
> VkPhysicalDeviceDepthClipControlFeaturesEXT:
> --------------------------------------------
> depthClipControl = true
>
> VkPhysicalDeviceDepthClipEnableFeaturesEXT:
> -------------------------------------------
> depthClipEnable = true
>
> VkPhysicalDeviceDescriptorBufferFeaturesEXT:
> --------------------------------------------
> descriptorBuffer = true
> descriptorBufferCaptureReplay = false
> descriptorBufferImageLayoutIgnored = true
> descriptorBufferPushDescriptors = true
>
> VkPhysicalDeviceDynamicRenderingUnusedAttachmentsFeaturesEXT:
> -------------------------------------------------------------
> dynamicRenderingUnusedAttachments = true
>
> VkPhysicalDeviceExtendedDynamicState2FeaturesEXT:
> -------------------------------------------------
> extendedDynamicState2 = true
> extendedDynamicState2LogicOp = true
> extendedDynamicState2PatchControlPoints = true
>
> VkPhysicalDeviceExtendedDynamicState3FeaturesEXT:
> -------------------------------------------------
> extendedDynamicState3TessellationDomainOrigin = true
> extendedDynamicState3DepthClampEnable = true
> extendedDynamicState3PolygonMode = true
> extendedDynamicState3RasterizationSamples = true
> extendedDynamicState3SampleMask = true
> extendedDynamicState3AlphaToCoverageEnable = true
> extendedDynamicState3AlphaToOneEnable = true
> extendedDynamicState3LogicOpEnable = true
> extendedDynamicState3ColorBlendEnable = true
> extendedDynamicState3ColorBlendEquation = true
> extendedDynamicState3ColorWriteMask = true
> extendedDynamicState3RasterizationStream = false
> extendedDynamicState3ConservativeRasterizationMode = false
> extendedDynamicState3ExtraPrimitiveOverestimationSize = false
> extendedDynamicState3DepthClipEnable = true
> extendedDynamicState3SampleLocationsEnable = false
> extendedDynamicState3ColorBlendAdvanced = false
> extendedDynamicState3ProvokingVertexMode = true
> extendedDynamicState3LineRasterizationMode = true
> extendedDynamicState3LineStippleEnable = true
> extendedDynamicState3DepthClipNegativeOneToOne = true
> extendedDynamicState3ViewportWScalingEnable = false
> extendedDynamicState3ViewportSwizzle = false
> extendedDynamicState3CoverageToColorEnable = false
> extendedDynamicState3CoverageToColorLocation = false
> extendedDynamicState3CoverageModulationMode = false
> extendedDynamicState3CoverageModulationTableEnable = false
> extendedDynamicState3CoverageModulationTable = false
> extendedDynamicState3CoverageReductionMode = false
> extendedDynamicState3RepresentativeFragmentTestEnable = false
> extendedDynamicState3ShadingRateImageEnable = false
>
> VkPhysicalDeviceExtendedDynamicStateFeaturesEXT:
> ------------------------------------------------
> extendedDynamicState = true
>
> VkPhysicalDeviceGraphicsPipelineLibraryFeaturesEXT:
> ---------------------------------------------------
> graphicsPipelineLibrary = true
>
> VkPhysicalDeviceHostImageCopyFeaturesEXT:
> -----------------------------------------
> hostImageCopy = true
>
> VkPhysicalDeviceImage2DViewOf3DFeaturesEXT:
> -------------------------------------------
> image2DViewOf3D = true
> sampler2DViewOf3D = true
>
> VkPhysicalDeviceImageSlicedViewOf3DFeaturesEXT:
> -----------------------------------------------
> imageSlicedViewOf3D = true
>
> VkPhysicalDeviceIndexTypeUint8FeaturesKHR:
> ------------------------------------------
> indexTypeUint8 = true
>
> VkPhysicalDeviceLineRasterizationFeaturesKHR:
> ---------------------------------------------
> rectangularLines = true
> bresenhamLines = true
> smoothLines = true
> stippledRectangularLines = true
> stippledBresenhamLines = true
> stippledSmoothLines = true
>
> VkPhysicalDeviceMaintenance5FeaturesKHR:
> ----------------------------------------
> maintenance5 = true
>
> VkPhysicalDeviceMaintenance6FeaturesKHR:
> ----------------------------------------
> maintenance6 = true
>
> VkPhysicalDeviceMemoryPriorityFeaturesEXT:
> ------------------------------------------
> memoryPriority = true
>
> VkPhysicalDeviceMeshShaderFeaturesEXT:
> --------------------------------------
> taskShader = true
> meshShader = true
> multiviewMeshShader = false
> primitiveFragmentShadingRateMeshShader = false
> meshShaderQueries = true
>
> VkPhysicalDeviceMultiDrawFeaturesEXT:
> -------------------------------------
> multiDraw = true
>
> VkPhysicalDeviceMultisampledRenderToSingleSampledFeaturesEXT:
> -------------------------------------------------------------
> multisampledRenderToSingleSampled = true
>
> VkPhysicalDeviceMutableDescriptorTypeFeaturesEXT:
> -------------------------------------------------
> mutableDescriptorType = true
>
> VkPhysicalDeviceNestedCommandBufferFeaturesEXT:
> -----------------------------------------------
> nestedCommandBuffer = true
> nestedCommandBufferRendering = true
> nestedCommandBufferSimultaneousUse = true
>
> VkPhysicalDeviceNonSeamlessCubeMapFeaturesEXT:
> ----------------------------------------------
> nonSeamlessCubeMap = true
>
> VkPhysicalDevicePageableDeviceLocalMemoryFeaturesEXT:
> -----------------------------------------------------
> pageableDeviceLocalMemory = true
>
> VkPhysicalDevicePrimitiveTopologyListRestartFeaturesEXT:
> --------------------------------------------------------
> primitiveTopologyListRestart = true
> primitiveTopologyPatchListRestart = true
>
> VkPhysicalDevicePrimitivesGeneratedQueryFeaturesEXT:
> ----------------------------------------------------
> primitivesGeneratedQuery = true
> primitivesGeneratedQueryWithRasterizerDiscard = true
> primitivesGeneratedQueryWithNonZeroStreams = true
>
> VkPhysicalDeviceProvokingVertexFeaturesEXT:
> -------------------------------------------
> provokingVertexLast = true
> transformFeedbackPreservesProvokingVertex = true
>
> VkPhysicalDeviceRasterizationOrderAttachmentAccessFeaturesEXT:
> --------------------------------------------------------------
> rasterizationOrderColorAttachmentAccess = true
> rasterizationOrderDepthAttachmentAccess = true
> rasterizationOrderStencilAttachmentAccess = true
>
> VkPhysicalDeviceRobustness2FeaturesEXT:
> ---------------------------------------
> robustBufferAccess2 = true
> robustImageAccess2 = true
> nullDescriptor = true
>
> VkPhysicalDeviceShaderAtomicFloat2FeaturesEXT:
> ----------------------------------------------
> shaderBufferFloat16Atomics = false
> shaderBufferFloat16AtomicAdd = false
> shaderBufferFloat16AtomicMinMax = false
> shaderBufferFloat32AtomicMinMax = true
> shaderBufferFloat64AtomicMinMax = false
> shaderSharedFloat16Atomics = false
> shaderSharedFloat16AtomicAdd = false
> shaderSharedFloat16AtomicMinMax = false
> shaderSharedFloat32AtomicMinMax = true
> shaderSharedFloat64AtomicMinMax = false
> shaderImageFloat32AtomicMinMax = true
> sparseImageFloat32AtomicMinMax = false
>
> VkPhysicalDeviceShaderAtomicFloatFeaturesEXT:
> ---------------------------------------------
> shaderBufferFloat32Atomics = true
> shaderBufferFloat32AtomicAdd = true
> shaderBufferFloat64Atomics = false
> shaderBufferFloat64AtomicAdd = false
> shaderSharedFloat32Atomics = true
> shaderSharedFloat32AtomicAdd = true
> shaderSharedFloat64Atomics = false
> shaderSharedFloat64AtomicAdd = false
> shaderImageFloat32Atomics = true
> shaderImageFloat32AtomicAdd = true
> sparseImageFloat32Atomics = false
> sparseImageFloat32AtomicAdd = false
>
> VkPhysicalDeviceShaderClockFeaturesKHR:
> ---------------------------------------
> shaderSubgroupClock = true
> shaderDeviceClock = true
>
> VkPhysicalDeviceShaderObjectFeaturesEXT:
> ----------------------------------------
> shaderObject = true
>
> VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT:
> ------------------------------------------------
> texelBufferAlignment = true
>
> VkPhysicalDeviceTransformFeedbackFeaturesEXT:
> ---------------------------------------------
> transformFeedback = true
> geometryStreams = true
>
> VkPhysicalDeviceVertexAttributeDivisorFeaturesKHR:
> --------------------------------------------------
> vertexAttributeInstanceRateDivisor = true
> vertexAttributeInstanceRateZeroDivisor = true
>
> VkPhysicalDeviceVertexInputDynamicStateFeaturesEXT:
> ---------------------------------------------------
> vertexInputDynamicState = true
>
> VkPhysicalDeviceVulkan11Features:
> ---------------------------------
> storageBuffer16BitAccess = true
> uniformAndStorageBuffer16BitAccess = true
> storagePushConstant16 = true
> storageInputOutput16 = false
> multiview = true
> multiviewGeometryShader = true
> multiviewTessellationShader = true
> variablePointersStorageBuffer = true
> variablePointers = true
> protectedMemory = false
> samplerYcbcrConversion = true
> shaderDrawParameters = true
>
> VkPhysicalDeviceVulkan12Features:
> ---------------------------------
> samplerMirrorClampToEdge = true
> drawIndirectCount = true
> storageBuffer8BitAccess = true
> uniformAndStorageBuffer8BitAccess = true
> storagePushConstant8 = true
> shaderBufferInt64Atomics = true
> shaderSharedInt64Atomics = true
> shaderFloat16 = true
> shaderInt8 = true
> descriptorIndexing = true
> shaderInputAttachmentArrayDynamicIndexing = true
> shaderUniformTexelBufferArrayDynamicIndexing = true
> shaderStorageTexelBufferArrayDynamicIndexing = true
> shaderUniformBufferArrayNonUniformIndexing = true
> shaderSampledImageArrayNonUniformIndexing = true
> shaderStorageBufferArrayNonUniformIndexing = true
> shaderStorageImageArrayNonUniformIndexing = true
> shaderInputAttachmentArrayNonUniformIndexing = true
> shaderUniformTexelBufferArrayNonUniformIndexing = true
> shaderStorageTexelBufferArrayNonUniformIndexing = true
> descriptorBindingUniformBufferUpdateAfterBind = true
> descriptorBindingSampledImageUpdateAfterBind = true
> descriptorBindingStorageImageUpdateAfterBind = true
> descriptorBindingStorageBufferUpdateAfterBind = true
> descriptorBindingUniformTexelBufferUpdateAfterBind = true
> descriptorBindingStorageTexelBufferUpdateAfterBind = true
> descriptorBindingUpdateUnusedWhilePending = true
> descriptorBindingPartiallyBound = true
> descriptorBindingVariableDescriptorCount = true
> runtimeDescriptorArray = true
> samplerFilterMinmax = true
> scalarBlockLayout = true
> imagelessFramebuffer = true
> uniformBufferStandardLayout = true
> shaderSubgroupExtendedTypes = true
> separateDepthStencilLayouts = true
> hostQueryReset = true
> timelineSemaphore = true
> bufferDeviceAddress = true
> bufferDeviceAddressCaptureReplay = false
> bufferDeviceAddressMultiDevice = false
> vulkanMemoryModel = true
> vulkanMemoryModelDeviceScope = true
> vulkanMemoryModelAvailabilityVisibilityChains = true
> shaderOutputViewportIndex = true
> shaderOutputLayer = true
> subgroupBroadcastDynamicId = true
>
> VkPhysicalDeviceVulkan13Features:
> ---------------------------------
> robustImageAccess = true
> inlineUniformBlock = true
> descriptorBindingInlineUniformBlockUpdateAfterBind = true
> pipelineCreationCacheControl = true
> privateData = true
> shaderDemoteToHelperInvocation = true
> shaderTerminateInvocation = true
> subgroupSizeControl = true
> computeFullSubgroups = true
> synchronization2 = true
> textureCompressionASTC_HDR = false
> shaderZeroInitializeWorkgroupMemory = true
> dynamicRendering = true
> shaderIntegerDotProduct = true
> maintenance4 = true
>
> VkPhysicalDeviceYcbcr2Plane444FormatsFeaturesEXT:
> -------------------------------------------------
> ycbcr2plane444Formats = true
>
> VkPhysicalDeviceYcbcrImageArraysFeaturesEXT:
> --------------------------------------------
> ycbcrImageArrays = true
>
>
> --
> 2.45.1.288.g0e0cd299f1-goog
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 1/6] dt-bindings: clock: mediatek: Add mt8173 mfgtop
2024-05-30 15:43 ` Conor Dooley
@ 2024-05-31 7:29 ` Chen-Yu Tsai
2024-05-31 14:58 ` Conor Dooley
0 siblings, 1 reply; 38+ messages in thread
From: Chen-Yu Tsai @ 2024-05-31 7:29 UTC (permalink / raw)
To: Conor Dooley
Cc: Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
David Airlie, Daniel Vetter, dri-devel, linux-clk, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel
On Thu, May 30, 2024 at 11:43 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Thu, May 30, 2024 at 04:35:00PM +0800, Chen-Yu Tsai wrote:
> > The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP
> > in the datasheet, that contains clock gates, some power sequence signal
> > delays, and other unknown registers that get toggled when the GPU is
> > powered on.
> >
> > The clock gates are exposed as clocks provided by a clock controller,
> > while the power sequencing bits are exposed as one singular power domain.
> >
> > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> > ---
> > .../clock/mediatek,mt8173-mfgtop.yaml | 71 +++++++++++++++++++
> > include/dt-bindings/clock/mt8173-clk.h | 7 ++
> > 2 files changed, 78 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml
> > new file mode 100644
> > index 000000000000..03c3c1f8cf75
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml
> > @@ -0,0 +1,71 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +
> > +$id: http://devicetree.org/schemas/clock/mediatek,mt8173-mfgtop.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek MT8173 MFG TOP controller
> > +
> > +maintainers:
> > + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> > +
> > +description:
> > + The MFG TOP glue layer controls various signals going to the MFG (GPU)
> > + block on the MT8173.
> > +
> > +properties:
> > + compatible:
> > + const: mediatek,mt8173-mfgtop
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + minItems: 4
>
> minItems is not needed when minItems == maxItems.
Ack.
> > + maxItems: 4
> > +
> > + clock-names:
> > + items:
> > + - const: sys
> > + - const: mem
> > + - const: core
> > + - const: clk26m
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + '#clock-cells':
> > + const: 1
> > +
> > + '#power-domain-cells':
> > + const: 0
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - clock-names
> > + - power-domains
> > + - '#clock-cells'
> > + - '#power-domain-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8173-clk.h>
> > + #include <dt-bindings/power/mt8173-power.h>
> > +
> > + mfgtop: clock-controller@13fff000 {
>
> The label here is used, so drop it.
Assume you mean _not_ used. Dropping. :D
> Otherwise,
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks!
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver
2024-05-30 10:16 ` Chen-Yu Tsai
2024-05-30 12:48 ` AngeloGioacchino Del Regno
@ 2024-05-31 11:17 ` Frank Binns
2024-06-05 8:39 ` Chen-Yu Tsai
2 siblings, 0 replies; 38+ messages in thread
From: Frank Binns @ 2024-05-31 11:17 UTC (permalink / raw)
To: angelogioacchino.delregno@collabora.com, wenst@chromium.org
Cc: robh@kernel.org, tzimmermann@suse.de, mripard@kernel.org,
daniel@ffwll.ch, linux-mediatek@lists.infradead.org,
conor+dt@kernel.org, Matt Coster, linux-kernel@vger.kernel.org,
maarten.lankhorst@linux.intel.com, devicetree@vger.kernel.org,
krzk+dt@kernel.org, dri-devel@lists.freedesktop.org,
airlied@gmail.com, linux-arm-kernel@lists.infradead.org,
linux-clk@vger.kernel.org, sboyd@kernel.org,
matthias.bgg@gmail.com
On Thu, 2024-05-30 at 18:16 +0800, Chen-Yu Tsai wrote:
> On Thu, May 30, 2024 at 5:59 PM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
> > Il 30/05/24 10:35, Chen-Yu Tsai ha scritto:
> > > The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP
> > > in the datasheet, that contains clock gates, some power sequence signal
> > > delays, and other unknown registers that get toggled when the GPU is
> > > powered on.
> > >
> > > The clock gates are exposed as clocks provided by a clock controller,
> > > while the power sequencing bits are exposed as one singular power domain.
> > >
> > > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> > > ---
> > > drivers/clk/mediatek/Kconfig | 9 +
> > > drivers/clk/mediatek/Makefile | 1 +
> > > drivers/clk/mediatek/clk-mt8173-mfgtop.c | 240 +++++++++++++++++++++++
> > > 3 files changed, 250 insertions(+)
> > > create mode 100644 drivers/clk/mediatek/clk-mt8173-mfgtop.c
> > >
> > > diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> > > index 70a005e7e1b1..9e279c739f1c 100644
> > > --- a/drivers/clk/mediatek/Kconfig
> > > +++ b/drivers/clk/mediatek/Kconfig
> > > @@ -500,6 +500,15 @@ config COMMON_CLK_MT8173_IMGSYS
> > > help
> > > This driver supports MediaTek MT8173 imgsys clocks.
> > >
> > > +config COMMON_CLK_MT8173_MFGTOP
> > > + tristate "Clock and power driver for MediaTek MT8173 mfgtop"
> > > + depends on COMMON_CLK_MT8173
> > > + default COMMON_CLK_MT8173
> > > + select PM_GENERIC_DOMAINS
> > > + select PM_GENERIC_DOMAINS_OF
> > > + help
> > > + This driver supports MediaTek MT8173 mfgtop clocks and power domain.
> > > +
> > > config COMMON_CLK_MT8173_MMSYS
> > > tristate "Clock driver for MediaTek MT8173 mmsys"
> > > depends on COMMON_CLK_MT8173
> > > diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> > > index eeccfa039896..fdd3a76e12a1 100644
> > > --- a/drivers/clk/mediatek/Makefile
> > > +++ b/drivers/clk/mediatek/Makefile
> > > @@ -77,6 +77,7 @@ obj-$(CONFIG_COMMON_CLK_MT8167_VDECSYS) += clk-mt8167-vdec.o
> > > obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173-apmixedsys.o clk-mt8173-infracfg.o \
> > > clk-mt8173-pericfg.o clk-mt8173-topckgen.o
> > > obj-$(CONFIG_COMMON_CLK_MT8173_IMGSYS) += clk-mt8173-img.o
> > > +obj-$(CONFIG_COMMON_CLK_MT8173_MFGTOP) += clk-mt8173-mfgtop.o
> > > obj-$(CONFIG_COMMON_CLK_MT8173_MMSYS) += clk-mt8173-mm.o
> > > obj-$(CONFIG_COMMON_CLK_MT8173_VDECSYS) += clk-mt8173-vdecsys.o
> > > obj-$(CONFIG_COMMON_CLK_MT8173_VENCSYS) += clk-mt8173-vencsys.o
> > > diff --git a/drivers/clk/mediatek/clk-mt8173-mfgtop.c b/drivers/clk/mediatek/clk-mt8173-mfgtop.c
> > > new file mode 100644
> > > index 000000000000..85fa7a7453ed
> > > --- /dev/null
> > > +++ b/drivers/clk/mediatek/clk-mt8173-mfgtop.c
> > > @@ -0,0 +1,240 @@
> > > +// SPDX-License-Identifier: GPL-2.0-only
> > > +/*
> > > + * Copyright (c) 2024 Google LLC
> > > + * Author: Chen-Yu Tsai <wenst@chromium.org>
> > > + *
> > > + * Based on driver in downstream ChromeOS v5.15 kernel.
> > > + *
> > > + * Copyright (c) 2014 MediaTek Inc.
> > > + * Author: Chiawen Lee <chiawen.lee@mediatek.com>
> > > + */
> > > +
> > > +#include <dt-bindings/clock/mt8173-clk.h>
> > > +
> > > +#include <linux/bitfield.h>
> > > +#include <linux/clk.h>
> > > +#include <linux/mfd/syscon.h>
> > > +#include <linux/module.h>
> > > +#include <linux/of.h>
> > > +#include <linux/platform_device.h>
> > > +#include <linux/pm_domain.h>
> > > +#include <linux/pm_runtime.h>
> > > +#include <linux/regmap.h>
> > > +
> > > +#include "clk-gate.h"
> > > +#include "clk-mtk.h"
> > > +
> > > +static const struct mtk_gate_regs mfg_cg_regs = {
> > > + .sta_ofs = 0x0000,
> > > + .clr_ofs = 0x0008,
> > > + .set_ofs = 0x0004,
> > > +};
> > > +
> > > +#define GATE_MFG(_id, _name, _parent, _shift, _flags) \
> > > + GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr, _flags)
> >
> > Extra tabulation: please fix
>
> One tab instead of two? OK.
>
> > > +
> > > +/* TODO: The block actually has dividers for the core and mem clocks. */
> > > +static const struct mtk_gate mfg_clks[] = {
> > > + GATE_MFG(CLK_MFG_AXI, "mfg_axi", "axi_mfg_in_sel", 0, CLK_SET_RATE_PARENT),
> > > + GATE_MFG(CLK_MFG_MEM, "mfg_mem", "mem_mfg_in_sel", 1, CLK_SET_RATE_PARENT),
> > > + GATE_MFG(CLK_MFG_G3D, "mfg_g3d", "mfg_sel", 2, CLK_SET_RATE_PARENT),
> > > + GATE_MFG(CLK_MFG_26M, "mfg_26m", "clk26m", 3, 0),
> > > +};
> > > +
> > > +static const struct mtk_clk_desc mfg_desc = {
> > > + .clks = mfg_clks,
> > > + .num_clks = ARRAY_SIZE(mfg_clks),
> > > +};
> > > +
> > > +struct mt8173_mfgtop_data {
> > > + struct clk_hw_onecell_data *clk_data;
> > > + struct regmap *regmap;
> > > + struct generic_pm_domain genpd;
> > > + struct of_phandle_args parent_pd, child_pd;
> > > + struct clk *clk_26m;
> > > +};
> > > +
> > > +static const struct of_device_id of_match_clk_mt8173_mfgtop[] = {
> > > + { .compatible = "mediatek,mt8173-mfgtop", .data = &mfg_desc },
> > > + { /* sentinel */ }
> > > +};
> > > +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_mfgtop);
> >
> > Please move of_match_clk_mt8173_mfgtop before clk_mt8173_mfgtop_drv for consistency
> > with all the other clock drivers.
>
> Ack.
>
> > > +
> > > +/* Delay count in clock cycles */
> > > +#define MFG_ACTIVE_POWER_CON0 0x24
> > > + #define RST_B_DELAY_CNT GENMASK(7, 0) /* pwr_rst_b de-assert delay during power-up */
> > > + #define CLK_EN_DELAY_CNT GENMASK(15, 8) /* CLK_DIS deassert delay during power-up */
> > > + #define CLK_DIS_DELAY_CNT GENMASK(23, 16) /* CLK_DIS assert delay during power-down */
> >
> > The reason why I had EVT_FORCE_ABORT and ACTIVE_PWRCTL_EN in my driver is to
> > document that we're keeping the event force abort disabled and, more importantly,
> > we are keeping the "active power control" feature disabled.
> >
> > Please, add those two - or at least the ACTIVE_PWRCTL_EN - to keep that documented,
> > or this information will be lost for sure.
> > If in the future the ACTIVE_PWRCTL feature will become usable, it's going to be
> > just a 30 seconds change, as the info is already there.
>
> OK.
>
> > > +
> > > +#define MFG_ACTIVE_POWER_CON1 0x28
> > > + #define PWR_ON_S_DELAY_CNT GENMASK(7, 0) /* pwr_on_s assert delay during power-up */
> > > + #define ISO_DELAY_CNT GENMASK(15, 8) /* ISO assert delay during power-down */
> > > + #define ISOOFF_DELAY_CNT GENMASK(23, 16) /* ISO de-assert delay during power-up */
> > > + #define RST__DELAY_CNT GENMASK(31, 24) /* pwr_rsb_b assert delay during power-down */
> > > +
> > > +static int clk_mt8173_mfgtop_power_on(struct generic_pm_domain *domain)
> > > +{
> > > + struct mt8173_mfgtop_data *data = container_of(domain, struct mt8173_mfgtop_data, genpd);
> > > +
> > > + /* drives internal power management */
> > > + clk_prepare_enable(data->clk_26m);
> > > +
> > > + /* Power on/off delays for various signals */
> > > + regmap_write(data->regmap, MFG_ACTIVE_POWER_CON0,
> > > + FIELD_PREP(RST_B_DELAY_CNT, 77) |
> > > + FIELD_PREP(CLK_EN_DELAY_CNT, 61) |
> > > + FIELD_PREP(CLK_DIS_DELAY_CNT, 60));
> >
> > I get that this is kinda odd to read, but still...
> >
> > FIELD_PREP(CLK_DIS_DELAY_CNT, 60) |
> > FIELD_PREP(ACTIVE_PWRCTL_EN, 0));
> >
> > ...please :-)
>
> Sure.
>
> > > + regmap_write(data->regmap, MFG_ACTIVE_POWER_CON1,
> > > + FIELD_PREP(PWR_ON_S_DELAY_CNT, 11) |
> > > + FIELD_PREP(ISO_DELAY_CNT, 68) |
> > > + FIELD_PREP(ISOOFF_DELAY_CNT, 69) |
> > > + FIELD_PREP(RST__DELAY_CNT, 77));
> > > +
> > > + /* Magic numbers related to core switch sequence and delays */
> > > + regmap_write(data->regmap, 0xe0, 0x7a710184);
> > > + regmap_write(data->regmap, 0xe4, 0x835f6856);
> > > + regmap_write(data->regmap, 0xe8, 0x002b0234);
> > > + regmap_write(data->regmap, 0xec, 0x80000000);
> > > + regmap_write(data->regmap, 0xa0, 0x08000000);
> >
> > Is there any way to retrieve information about what those registers are?
>
> I asked. They said the project was too long ago, and they could only
> figure out that it had something to do with core switch sequencing and
> delays between each core, which is what I put in the comment there.
>
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int clk_mt8173_mfgtop_power_off(struct generic_pm_domain *domain)
> > > +{
> > > + struct mt8173_mfgtop_data *data = container_of(domain, struct mt8173_mfgtop_data, genpd);
> > > +
> > > + /* Magic numbers related to core switch sequence and delays */
> > > + regmap_write(data->regmap, 0xec, 0);
> > > +
> > > + /* drives internal power management */
> > > + clk_disable_unprepare(data->clk_26m);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int clk_mt8173_mfgtop_probe(struct platform_device *pdev)
> > > +{
> > > + struct device *dev = &pdev->dev;
> > > + struct device_node *node = dev->of_node;
> > > + struct mt8173_mfgtop_data *data;
> > > + int ret;
> > > +
> > > + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> > > + if (!data)
> > > + return -ENOMEM;
> > > +
> > > + platform_set_drvdata(pdev, data);
> > > +
> > > + data->clk_data = mtk_devm_alloc_clk_data(dev, ARRAY_SIZE(mfg_clks));
> > > + if (!data->clk_data)
> > > + return -ENOMEM;
> > > +
> > > + /* MTK clock gates also uses regmap */
> > > + data->regmap = device_node_to_regmap(node);
> > > + if (IS_ERR(data->regmap))
> > > + return dev_err_probe(dev, PTR_ERR(data->regmap), "Failed to get regmap\n");
> > > +
> > > + data->child_pd.np = node;
> > > + data->child_pd.args_count = 0;
> > > + ret = of_parse_phandle_with_args(node, "power-domains", "#power-domain-cells", 0,
> > > + &data->parent_pd);
> > > + if (ret)
> > > + return dev_err_probe(dev, ret, "Failed to parse power domain\n");
> > > +
> > > + devm_pm_runtime_enable(dev);
> > > + /*
> > > + * Do a pm_runtime_resume_and_get() to workaround a possible
> > > + * deadlock between clk_register() and the genpd framework.
> > > + */
> > > + ret = pm_runtime_resume_and_get(dev);
> > > + if (ret) {
> > > + dev_err_probe(dev, ret, "Failed to runtime resume device\n");
> > > + goto put_of_node;
> > > + }
> > > +
> > > + ret = mtk_clk_register_gates(dev, node, mfg_clks, ARRAY_SIZE(mfg_clks),
> > > + data->clk_data);
> > > + if (ret) {
> > > + dev_err_probe(dev, ret, "Failed to register clock gates\n");
> > > + goto put_pm_runtime;
> > > + }
> > > +
> > > + data->clk_26m = clk_hw_get_clk(data->clk_data->hws[CLK_MFG_26M], "26m");
> > > + if (IS_ERR(data->clk_26m)) {
> > > + dev_err_probe(dev, PTR_ERR(data->clk_26m), "Failed to get 26 MHz clock\n");
> > > + goto unregister_clks;
> > > + }
> > > +
> > > + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data->clk_data);
> > > + if (ret) {
> > > + dev_err_probe(dev, ret, "Failed to add clk OF provider\n");
> > > + goto put_26m_clk;
> > > + }
> > > +
> > > + data->genpd.name = "mfg_apm";
> >
> > "mfg-apm" or "mfg-pwr" please!
>
> Ack.
>
> > Everything else looks good.
> >
> > Thanks for taking care of that, I started this work way too much time ago and
> > realistically I wouldn't have been able to finish it due to time constraints.
> >
> > It's great to see that *finally* we can get some GPU upstream on this old SoC.
> > As its CPUs are really slow, LLVMPipe is quite unusable from a UX perspective
> > hence its only big issue was the lack of 3D HW acceleration.
>
> I think there's still more work on the GPU driver side. I was digging
> through the mailing list to find ways to get it running, and evidently
> it doesn't fully support zink yet.
Upstream Mesa is still missing a lot of changes taking the driver up to Vulkan
1.0 on AXE-1-16M, which is the GPU we've mainly been focusing on. This work can
be found in our Mesa repo on FDO GitLab [1]. Support for GX6250 (Series 6XT) and
BXS-4-64 is currently incomplete (these are the other GPUs we've been adding
support for [2]).
The changes haven't made it upstream yet as we're in the process of reworking
the compiler and compiler/driver interface side of things to address the
inevitable comments we'd get as part of upstreaming. This work should be
complete soon and will go a long way towards improving support for / making it
easier to support more GPUs on the compiler side.
In parallel to this, we've implemented the Vulkan extensions, optional features,
etc needed by Zink [2] and we're currently fixing GLES conformance issues.
Again, we've been focusing on AXE-1-16M. Once we've got GLES conformance passing
we'll be switching our focus to completing support for the BXS-4-64.
Thanks
Frank
[1] https://gitlab.freedesktop.org/imagination/mesa/-/tree/powervr-mesa-next
[2] https://docs.mesa3d.org/drivers/powervr.html
[3] https://gitlab.freedesktop.org/imagination/mesa/-/tree/dev/zink
>
> > This makes machines embedding this SoC usable, and that's simply awesome.
>
> I'll give the patches a week to simmer while I go work on some
> other stuff.
>
> ChenYu
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 4/6] drm/imagination: Add compatible string entry for Series6XT
2024-05-30 8:35 ` [PATCH 4/6] drm/imagination: Add compatible string entry for Series6XT Chen-Yu Tsai
2024-05-30 10:03 ` AngeloGioacchino Del Regno
@ 2024-05-31 11:18 ` Frank Binns
2024-06-03 3:29 ` Chen-Yu Tsai
1 sibling, 1 reply; 38+ messages in thread
From: Frank Binns @ 2024-05-31 11:18 UTC (permalink / raw)
To: matthias.bgg@gmail.com, tzimmermann@suse.de, Matt Coster,
sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
maarten.lankhorst@linux.intel.com, wenst@chromium.org,
mripard@kernel.org, conor+dt@kernel.org,
angelogioacchino.delregno@collabora.com
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, airlied@gmail.com,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, daniel@ffwll.ch,
linux-clk@vger.kernel.org
On Thu, 2024-05-30 at 16:35 +0800, Chen-Yu Tsai wrote:
> The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is part
> of the Series6XT, another variation of the Rogue family of GPUs.
>
> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> ---
> drivers/gpu/drm/imagination/pvr_drv.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/imagination/pvr_drv.c b/drivers/gpu/drm/imagination/pvr_drv.c
> index 5c3b2d58d766..3d1a933c8303 100644
> --- a/drivers/gpu/drm/imagination/pvr_drv.c
> +++ b/drivers/gpu/drm/imagination/pvr_drv.c
> @@ -1475,6 +1475,7 @@ pvr_remove(struct platform_device *plat_dev)
>
> static const struct of_device_id dt_match[] = {
> { .compatible = "img,img-axe", .data = NULL },
> + { .compatible = "img,powervr-6xt", .data = NULL },
I assume that by adding this to the list of supported devices we're essentially
freezing the existing uapi. This concerns me, as we've not yet started running
Vulkan conformance on any Series6XT GPUs and there's a chance we may need to
make some tweaks.
I'm not really sure what the accepted approach is to hardware enablement /
experimental support. I'm not sure if it's sufficient to hide support behind a
Kconfig option and/or module parameter or whether we just have to hold this
patch back for the time being.
Thanks
Frank
> {}
> };
> MODULE_DEVICE_TABLE(of, dt_match);
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 3/6] dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU
2024-05-30 8:35 ` [PATCH 3/6] dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU Chen-Yu Tsai
2024-05-30 10:03 ` AngeloGioacchino Del Regno
2024-05-30 15:38 ` Conor Dooley
@ 2024-05-31 13:37 ` Frank Binns
2024-05-31 14:24 ` Adam Ford
2024-06-04 4:18 ` Chen-Yu Tsai
2 siblings, 2 replies; 38+ messages in thread
From: Frank Binns @ 2024-05-31 13:37 UTC (permalink / raw)
To: matthias.bgg@gmail.com, tzimmermann@suse.de, Matt Coster,
sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
aford173@gmail.com, maarten.lankhorst@linux.intel.com,
wenst@chromium.org, mripard@kernel.org, conor+dt@kernel.org,
angelogioacchino.delregno@collabora.com
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, airlied@gmail.com,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, daniel@ffwll.ch,
linux-clk@vger.kernel.org
Hi ChenYu,
On Thu, 2024-05-30 at 16:35 +0800, Chen-Yu Tsai wrote:
> The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is one
> of the Series6XT GPUs, another sub-family of the Rogue family.
I've added Adam Ford who sent out some DT related patches [1] for the Renesas
variant of GX6250 and the GX6650 (another Series6XT GPU).
>
> This was part of the very first few versions of the PowerVR submission,
> but was later dropped. The compatible string has been updated to follow
> the new naming scheme adopted for the AXE series.
>
> In a previous iteration of the PowerVR binding submission [1], the
> number of clocks required for the 6XT family was mentioned to be
> always 3. This is also reflected here.
>
> [1] https://lore.kernel.org/dri-devel/6eeccb26e09aad67fb30ffcd523c793a43c79c2a.camel@imgtec.com/
>
> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> ---
> .../bindings/gpu/img,powervr-rogue.yaml | 24 +++++++++++++++----
> 1 file changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> index 256e252f8087..48aa205b66b4 100644
> --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> @@ -12,10 +12,17 @@ maintainers:
>
> properties:
> compatible:
> - items:
> - - enum:
> - - ti,am62-gpu
> - - const: img,img-axe # IMG AXE GPU model/revision is fully discoverable
> + oneOf:
> + - items:
> + - enum:
> + - mediatek,mt8173-gpu
> + # PowerVR 6XT GPU model/revision is fully discoverable
> + - const: img,powervr-6xt
> + - items:
> + - enum:
> + - ti,am62-gpu
> + # IMG AXE GPU model/revision is fully discoverable
> + - const: img,img-axe
The Series6XT GPU models have differing numbers of power domains (either 2, 4 or
5). Whereas, the AXE GPUs have a single power domain, so I assume there should
be a related change here.
The GX6250 has two power domains (lets call them A and B). There's a constraint
that if domain B is powered then domain A must also be powered.
In patch 6 [2] it's setting the power domain to MT8173_POWER_DOMAIN_MFG, which I
believe corresponds to power domain B. I assume this works because the MTK power
controller driver is encoding the constraint above, meaning that when we disable
or enable MT8173_POWER_DOMAIN_MFG it's also disabling/enabling MT8173_POWER_DOMA
IN_MFG_2D (domain A).
Thanks
Frank
[1] https://lists.freedesktop.org/archives/dri-devel/2024-February/443548.html
[2] https://lists.freedesktop.org/archives/dri-devel/2024-May/455833.html
>
> reg:
> maxItems: 1
> @@ -56,6 +63,15 @@ allOf:
> properties:
> clocks:
> maxItems: 1
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: img,powervr-6xt
> + then:
> + properties:
> + clocks:
> + minItems: 3
>
> examples:
> - |
_______________________________________________
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 3/6] dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU
2024-05-31 13:37 ` Frank Binns
@ 2024-05-31 14:24 ` Adam Ford
2024-06-04 4:21 ` Chen-Yu Tsai
2024-06-04 4:18 ` Chen-Yu Tsai
1 sibling, 1 reply; 38+ messages in thread
From: Adam Ford @ 2024-05-31 14:24 UTC (permalink / raw)
To: Frank Binns
Cc: matthias.bgg@gmail.com, tzimmermann@suse.de, Matt Coster,
sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
maarten.lankhorst@linux.intel.com, wenst@chromium.org,
mripard@kernel.org, conor+dt@kernel.org,
angelogioacchino.delregno@collabora.com,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, airlied@gmail.com,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, daniel@ffwll.ch,
linux-clk@vger.kernel.org
On Fri, May 31, 2024 at 8:37 AM Frank Binns <Frank.Binns@imgtec.com> wrote:
>
> Hi ChenYu,
>
> On Thu, 2024-05-30 at 16:35 +0800, Chen-Yu Tsai wrote:
> > The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is one
> > of the Series6XT GPUs, another sub-family of the Rogue family.
>
> I've added Adam Ford who sent out some DT related patches [1] for the Renesas
> variant of GX6250 and the GX6650 (another Series6XT GPU).
>
Thanks for including me.
> >
> > This was part of the very first few versions of the PowerVR submission,
> > but was later dropped. The compatible string has been updated to follow
> > the new naming scheme adopted for the AXE series.
> >
> > In a previous iteration of the PowerVR binding submission [1], the
> > number of clocks required for the 6XT family was mentioned to be
> > always 3. This is also reflected here.
> >
> > [1] https://lore.kernel.org/dri-devel/6eeccb26e09aad67fb30ffcd523c793a43c79c2a.camel@imgtec.com/
> >
> > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> > ---
> > .../bindings/gpu/img,powervr-rogue.yaml | 24 +++++++++++++++----
> > 1 file changed, 20 insertions(+), 4 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> > index 256e252f8087..48aa205b66b4 100644
> > --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> > +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> > @@ -12,10 +12,17 @@ maintainers:
> >
> > properties:
> > compatible:
> > - items:
> > - - enum:
> > - - ti,am62-gpu
> > - - const: img,img-axe # IMG AXE GPU model/revision is fully discoverable
> > + oneOf:
> > + - items:
> > + - enum:
> > + - mediatek,mt8173-gpu
> > + # PowerVR 6XT GPU model/revision is fully discoverable
> > + - const: img,powervr-6xt
> > + - items:
> > + - enum:
> > + - ti,am62-gpu
> > + # IMG AXE GPU model/revision is fully discoverable
> > + - const: img,img-axe
>
> The Series6XT GPU models have differing numbers of power domains (either 2, 4 or
> 5). Whereas, the AXE GPUs have a single power domain, so I assume there should
> be a related change here.
>
> The GX6250 has two power domains (lets call them A and B). There's a constraint
> that if domain B is powered then domain A must also be powered.
>
> In patch 6 [2] it's setting the power domain to MT8173_POWER_DOMAIN_MFG, which I
> believe corresponds to power domain B. I assume this works because the MTK power
> controller driver is encoding the constraint above, meaning that when we disable
> or enable MT8173_POWER_DOMAIN_MFG it's also disabling/enabling MT8173_POWER_DOMA
> IN_MFG_2D (domain A).
>
In the cover letter of this series, it was noted that the GPU
enumerates, but it doesn' fully function yet. This is also the case
for both of the Renesas variants I have been testing, and I was nicely
asked to postpone my series until the driver was closer to being
ready.
Even if the driver isn't ready yet, it would be nice to move the
bindings forward.
adam
> Thanks
> Frank
>
> [1] https://lists.freedesktop.org/archives/dri-devel/2024-February/443548.html
> [2] https://lists.freedesktop.org/archives/dri-devel/2024-May/455833.html
>
> >
> > reg:
> > maxItems: 1
> > @@ -56,6 +63,15 @@ allOf:
> > properties:
> > clocks:
> > maxItems: 1
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: img,powervr-6xt
> > + then:
> > + properties:
> > + clocks:
> > + minItems: 3
> >
> > examples:
> > - |
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 1/6] dt-bindings: clock: mediatek: Add mt8173 mfgtop
2024-05-31 7:29 ` Chen-Yu Tsai
@ 2024-05-31 14:58 ` Conor Dooley
0 siblings, 0 replies; 38+ messages in thread
From: Conor Dooley @ 2024-05-31 14:58 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
David Airlie, Daniel Vetter, dri-devel, linux-clk, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 499 bytes --]
On Fri, May 31, 2024 at 03:29:06PM +0800, Chen-Yu Tsai wrote:
> On Thu, May 30, 2024 at 11:43 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Thu, May 30, 2024 at 04:35:00PM +0800, Chen-Yu Tsai wrote:
> > > + #include <dt-bindings/clock/mt8173-clk.h>
> > > + #include <dt-bindings/power/mt8173-power.h>
> > > +
> > > + mfgtop: clock-controller@13fff000 {
> >
> > The label here is used, so drop it.
>
> Assume you mean _not_ used. Dropping. :D
Correct :D
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 0/6] powervr: MT8173 GPU support
[not found] ` <d4a97a657330d50d14cb93954e8b243489bb51ef.camel@imgtec.com>
@ 2024-06-02 19:53 ` Adam Ford
0 siblings, 0 replies; 38+ messages in thread
From: Adam Ford @ 2024-06-02 19:53 UTC (permalink / raw)
To: Frank Binns
Cc: matthias.bgg@gmail.com, tzimmermann@suse.de, Matt Coster,
sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
maarten.lankhorst@linux.intel.com, wenst@chromium.org,
mripard@kernel.org, conor+dt@kernel.org,
angelogioacchino.delregno@collabora.com,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, airlied@gmail.com,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, daniel@ffwll.ch,
linux-clk@vger.kernel.org
On Fri, May 31, 2024 at 6:23 AM Frank Binns <Frank.Binns@imgtec.com> wrote:
>
> Hi ChenYu,
>
> On Fri, 2024-05-31 at 12:00 +0800, Chen-Yu Tsai wrote:
> > On Thu, May 30, 2024 at 4:35 PM Chen-Yu Tsai <wenst@chromium.org> wrote:
> > > Hi everyone,
> > >
> > > This series enables the PowerVR GPU found in the MT8173 SoC, found in
> > > some Chromebooks.
>
> Thank you for the patches, I'm really happy to see these!
>
> > >
> > > This version is different from the initial powervr driver submission [1]
> > > in that it splits out the GPU glue layer support out of the powervr
> > > driver and into a separate clock and power domain driver. The glue code
> > > is otherwise the same, and also the same as found in the ChromeOS
> > > kernels, with some extra comments and macro names added where possible.
> > >
> > > Patch 1 adds a binding for the glue layer, called mfgtop. The glue layer
> > > contains clock and power controls for the GPU.
> > >
> > > Patch 2 adds a driver for the glue layer.
> > >
> > > Patch 3 adds an entry for the MT8173 GPU and 6XT series to the PowerVR
> > > binding.
> > >
> > > Patch 4 adds an entry for the PowerVR 6XT series GPU to the driver.
> > >
> > > Patch 5 corrects the clock for the GPU (called MFG) power domain.
> > >
> > > Patch 6 adds device nodes for the GPU and glue layer to the MT8173 dtsi
> > > file.
> > >
> > > Patch 2 and 6 depend on patch 1 to build. I suppose some common
> > > immutable tree would be needed from the MediaTek maintainers.
> > >
> > > The kernel driver successfully probes the hardware and loads the
> > > "rogue_4.40.2.51_v1.fw" firmware provided by Imagination Technologies [2].
> > > Userspace was tested with Mesa 24.0.8 from Debian Trixie rebuilt with
> > > the powervr vulkan driver enabled. `vulkaninfo` gives some information
> > > about the GPU (attached at the end), but running the `triangle` example
> > > from the Sascha Willems demos [3] with -DUSE_D2D_WSI=ON as recommended [4]
> > > failed with:
> > >
> > > Can't find a display and a display mode!
> > >
> > > Same program worked correctly on a BeaglePlay and displayed a color
> > > gradient triangle. Not sure what went wrong here.
> >
> > Frank mentioned over IRC that giving `triangle` a screen resolution would
> > make it work, and it did! Thanks Frank!
>
> No problem :)
>
> I've not dug into the display mode issue, but I'm wondering if it happens
> because there isn't a mode flagged as the preferred mode.
>
> >
> > OTOH I'm getting some extra warnings not seen on the BeaglePlay:
> >
> > MESA: error: No hard coded passthrough rta vertex shader.
> > Returning empty shader.
> > MESA: warning: ../src/imagination/vulkan/pvr_job_context.c:71:
> > FINISHME: Missing reset support for brn51764
> > MESA: warning: ../src/imagination/vulkan/pvr_job_context.c:74:
> > FINISHME: Missing reset support for brn58839
> > MESA: warning: ../src/imagination/vulkan/pvr_border.c:104:
> > FINISHME: Devices without tpu_border_colour_enhanced require entries
> > for compressed formats to be stored in the table pre-compressed.
> >
> > I also get a constant stream of kernel error messages, all the same:
> >
> > powervr 13000000.gpu: [drm] Received unknown FWCCB command 2abc0069
> >
> > And the first few frames seem to flicker. (Though that could also be the
> > display driver that's at fault.)
>
> The unknown commands are related to the GPU locking up, presumably because bad
> jobs are being submitted, likely due to missing bits of support for the
> Series6XT GPUs in the Vulkan driver / compiler. The unknown commands are the
> firmware notifying the host that the GPU has been reset. The GPU resets would
> explain the flickering you're seeing.
For what it's worth the GX6250 on my Renesas board appears to behave
the same way. I Used a different branch, but applied the patches to
support the BVNC. I then tweaked it for my Renesas hardware. I ran
vkd3d-gears, and I get several frames before it glitched out and
reappeared.
adam
>
> Thanks
> Frank
>
> >
> >
> > For reference, on the BeaglePlay I see:
> >
> > MESA: error: No hard coded idfwdf program. Returning empty program.
> > MESA: error: No hard coded passthrough vertex shader. Returning
> > empty shader.
> > MESA: warning:
> > ../src/imagination/vulkan/pvr_descriptor_set.c:1073: FINISHME: Entry
> > tracker for allocations?
> >
> >
> > Regards
> > ChenYu
> >
> >
> > > Anyway, please have a look and test.
> > >
> > >
> > > Thanks
> > > ChenYu
> > >
> > > [1] https://lore.kernel.org/dri-devel/20220815165156.118212-2-sarah.walker@imgtec.com/
> > > [2] https://gitlab.freedesktop.org/imagination/linux-firmware/-/tree/powervr
> > > [3] https://github.com/SaschaWillems/Vulkan
> > > [4] https://lore.kernel.org/dri-devel/f2b2671e-5acc-4dec-9c2e-3c9cd2e1f19e@imgtec.com/
> > >
> > > Chen-Yu Tsai (6):
> > > dt-bindings: clock: mediatek: Add mt8173 mfgtop
> > > clk: mediatek: Add mt8173-mfgtop driver
> > > dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU
> > > drm/imagination: Add compatible string entry for Series6XT
> > > arm64: dts: mediatek: mt8173: Fix MFG_ASYNC power domain clock
> > > arm64: dts: mediatek: mt8173: Add GPU device nodes
> > >
> > > .../clock/mediatek,mt8173-mfgtop.yaml | 71 ++++++
> > > .../bindings/gpu/img,powervr-rogue.yaml | 24 +-
> > > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 26 +-
> > > drivers/clk/mediatek/Kconfig | 9 +
> > > drivers/clk/mediatek/Makefile | 1 +
> > > drivers/clk/mediatek/clk-mt8173-mfgtop.c | 240 ++++++++++++++++++
> > > drivers/gpu/drm/imagination/pvr_drv.c | 1 +
> > > include/dt-bindings/clock/mt8173-clk.h | 7 +
> > > 8 files changed, 374 insertions(+), 5 deletions(-)
> > > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml
> > > create mode 100644 drivers/clk/mediatek/clk-mt8173-mfgtop.c
> > >
> > >
> > > base-commit: 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
> > >
> > > Vulkan info output:
> > >
> > > WARNING: [Loader Message] Code 0 : terminator_CreateInstance: Received return code -3 from call to vkCreateInstance in ICD /usr/lib/aarch64-linux-gnu/libvulkan_virtio.so. Skipping this driver.
> > > 'DISPLAY' environment variable not set... skipping surface info
> > > ERROR: [../src/panfrost/vulkan/panvk_device.c:386] Code 0 : WARNING: panvk is not a conformant vulkan implementation, pass PAN_I_WANT_A_BROKEN_VULKAN_DRIVER=1 if you know what you're doing. (VK_ERROR_INCOMPATIBLE_DRIVER)
> > > MESA: error: No hard coded idfwdf program. Returning empty program.
> > > MESA: error: No hard coded passthrough rta vertex shader. Returning empty shader.
> > > MESA: error: No hard coded passthrough vertex shader. Returning empty shader.
> > > MESA: warning: ../src/imagination/vulkan/pvr_job_context.c:71: FINISHME: Missing reset support for brn51764
> > > MESA: warning: ../src/imagination/vulkan/pvr_job_context.c:74: FINISHME: Missing reset support for brn58839
> > > MESA: warning: ../src/imagination/vulkan/pvr_border.c:104: FINISHME: Devices without tpu_border_colour_enhanced require entries for compressed formats to be stored in the table pre-compressed.
> > > ==========
> > > VULKANINFO
> > > ==========
> > >
> > > Vulkan Instance Version: 1.3.280
> > >
> > >
> > > Instance Extensions: count = 23
> > > ===============================
> > > VK_EXT_acquire_drm_display : extension revision 1
> > > VK_EXT_acquire_xlib_display : extension revision 1
> > > VK_EXT_debug_report : extension revision 10
> > > VK_EXT_debug_utils : extension revision 2
> > > VK_EXT_direct_mode_display : extension revision 1
> > > VK_EXT_display_surface_counter : extension revision 1
> > > VK_EXT_surface_maintenance1 : extension revision 1
> > > VK_EXT_swapchain_colorspace : extension revision 4
> > > VK_KHR_device_group_creation : extension revision 1
> > > VK_KHR_display : extension revision 23
> > > VK_KHR_external_fence_capabilities : extension revision 1
> > > VK_KHR_external_memory_capabilities : extension revision 1
> > > VK_KHR_external_semaphore_capabilities : extension revision 1
> > > VK_KHR_get_display_properties2 : extension revision 1
> > > VK_KHR_get_physical_device_properties2 : extension revision 2
> > > VK_KHR_get_surface_capabilities2 : extension revision 1
> > > VK_KHR_portability_enumeration : extension revision 1
> > > VK_KHR_surface : extension revision 25
> > > VK_KHR_surface_protected_capabilities : extension revision 1
> > > VK_KHR_wayland_surface : extension revision 6
> > > VK_KHR_xcb_surface : extension revision 6
> > > VK_KHR_xlib_surface : extension revision 6
> > > VK_LUNARG_direct_driver_loading : extension revision 1
> > >
> > > Layers: count = 2
> > > =================
> > > VK_LAYER_MESA_device_select (Linux device selection layer) Vulkan version 1.3.211, layer version 1:
> > > Layer Extensions: count = 0
> > > Devices: count = 2
> > > GPU id = 0 (Imagination PowerVR Rogue GX6250)
> > > Layer-Device Extensions: count = 0
> > >
> > > GPU id = 1 (llvmpipe (LLVM 17.0.6, 128 bits))
> > > Layer-Device Extensions: count = 0
> > >
> > > VK_LAYER_MESA_overlay (Mesa Overlay layer) Vulkan version 1.3.211, layer version 1:
> > > Layer Extensions: count = 0
> > > Devices: count = 2
> > > GPU id = 0 (Imagination PowerVR Rogue GX6250)
> > > Layer-Device Extensions: count = 0
> > >
> > > GPU id = 1 (llvmpipe (LLVM 17.0.6, 128 bits))
> > > Layer-Device Extensions: count = 0
> > >
> > > Device Properties and Extensions:
> > > =================================
> > > GPU0:
> > > VkPhysicalDeviceProperties:
> > > ---------------------------
> > > apiVersion = 1.0.274 (4194578)
> > > driverVersion = 24.0.8 (100663304)
> > > vendorID = 0x1010
> > > deviceID = 0x6250
> > > deviceType = PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
> > > deviceName = Imagination PowerVR Rogue GX6250
> > > pipelineCacheUUID = 6ddf30eb-d118-41f1-455f-580ae751c27b
> > >
> > > VkPhysicalDeviceLimits:
> > > -----------------------
> > > maxImageDimension1D = 8192
> > > maxImageDimension2D = 8192
> > > maxImageDimension3D = 2048
> > > maxImageDimensionCube = 8192
> > > maxImageArrayLayers = 2048
> > > maxTexelBufferElements = 65536
> > > maxUniformBufferRange = 134217728
> > > maxStorageBufferRange = 134217728
> > > maxPushConstantsSize = 256
> > > maxMemoryAllocationCount = 4294967295
> > > maxSamplerAllocationCount = 4294967295
> > > bufferImageGranularity = 0x00000001
> > > sparseAddressSpaceSize = 0x4000000000
> > > maxBoundDescriptorSets = 4
> > > maxPerStageDescriptorSamplers = 32
> > > maxPerStageDescriptorUniformBuffers = 64
> > > maxPerStageDescriptorStorageBuffers = 36
> > > maxPerStageDescriptorSampledImages = 48
> > > maxPerStageDescriptorStorageImages = 8
> > > maxPerStageDescriptorInputAttachments = 8
> > > maxPerStageResources = 224
> > > maxDescriptorSetSamplers = 256
> > > maxDescriptorSetUniformBuffers = 256
> > > maxDescriptorSetUniformBuffersDynamic = 8
> > > maxDescriptorSetStorageBuffers = 256
> > > maxDescriptorSetStorageBuffersDynamic = 8
> > > maxDescriptorSetSampledImages = 256
> > > maxDescriptorSetStorageImages = 256
> > > maxDescriptorSetInputAttachments = 256
> > > maxVertexInputAttributes = 16
> > > maxVertexInputBindings = 16
> > > maxVertexInputAttributeOffset = 65535
> > > maxVertexInputBindingStride = 2147483648
> > > maxVertexOutputComponents = 128
> > > maxTessellationGenerationLevel = 0
> > > maxTessellationPatchSize = 0
> > > maxTessellationControlPerVertexInputComponents = 0
> > > maxTessellationControlPerVertexOutputComponents = 0
> > > maxTessellationControlPerPatchOutputComponents = 0
> > > maxTessellationControlTotalOutputComponents = 0
> > > maxTessellationEvaluationInputComponents = 0
> > > maxTessellationEvaluationOutputComponents = 0
> > > maxGeometryShaderInvocations = 0
> > > maxGeometryInputComponents = 0
> > > maxGeometryOutputComponents = 0
> > > maxGeometryOutputVertices = 0
> > > maxGeometryTotalOutputComponents = 0
> > > maxFragmentInputComponents = 128
> > > maxFragmentOutputAttachments = 8
> > > maxFragmentDualSrcAttachments = 0
> > > maxFragmentCombinedOutputResources = 52
> > > maxComputeSharedMemorySize = 16384
> > > maxComputeWorkGroupCount: count = 3
> > > 65536
> > > 65536
> > > 65536
> > > maxComputeWorkGroupInvocations = 512
> > > maxComputeWorkGroupSize: count = 3
> > > 512
> > > 512
> > > 64
> > > subPixelPrecisionBits = 8
> > > subTexelPrecisionBits = 8
> > > mipmapPrecisionBits = 8
> > > maxDrawIndexedIndexValue = 4294967295
> > > maxDrawIndirectCount = 2147483648
> > > maxSamplerLodBias = 16
> > > maxSamplerAnisotropy = 1
> > > maxViewports = 1
> > > maxViewportDimensions: count = 2
> > > 8192
> > > 8192
> > > viewportBoundsRange: count = 2
> > > -16384
> > > 16384
> > > viewportSubPixelBits = 0
> > > minMemoryMapAlignment = 64
> > > minTexelBufferOffsetAlignment = 0x00000010
> > > minUniformBufferOffsetAlignment = 0x00000004
> > > minStorageBufferOffsetAlignment = 0x00000004
> > > minTexelOffset = -8
> > > maxTexelOffset = 7
> > > minTexelGatherOffset = -8
> > > maxTexelGatherOffset = 7
> > > minInterpolationOffset = -0.5
> > > maxInterpolationOffset = 0.5
> > > subPixelInterpolationOffsetBits = 4
> > > maxFramebufferWidth = 8192
> > > maxFramebufferHeight = 8192
> > > maxFramebufferLayers = 2048
> > > framebufferColorSampleCounts: count = 4
> > > SAMPLE_COUNT_1_BIT
> > > SAMPLE_COUNT_2_BIT
> > > SAMPLE_COUNT_4_BIT
> > > SAMPLE_COUNT_8_BIT
> > > framebufferDepthSampleCounts: count = 4
> > > SAMPLE_COUNT_1_BIT
> > > SAMPLE_COUNT_2_BIT
> > > SAMPLE_COUNT_4_BIT
> > > SAMPLE_COUNT_8_BIT
> > > framebufferStencilSampleCounts: count = 4
> > > SAMPLE_COUNT_1_BIT
> > > SAMPLE_COUNT_2_BIT
> > > SAMPLE_COUNT_4_BIT
> > > SAMPLE_COUNT_8_BIT
> > > framebufferNoAttachmentsSampleCounts: count = 4
> > > SAMPLE_COUNT_1_BIT
> > > SAMPLE_COUNT_2_BIT
> > > SAMPLE_COUNT_4_BIT
> > > SAMPLE_COUNT_8_BIT
> > > maxColorAttachments = 8
> > > sampledImageColorSampleCounts: count = 4
> > > SAMPLE_COUNT_1_BIT
> > > SAMPLE_COUNT_2_BIT
> > > SAMPLE_COUNT_4_BIT
> > > SAMPLE_COUNT_8_BIT
> > > sampledImageIntegerSampleCounts: count = 4
> > > SAMPLE_COUNT_1_BIT
> > > SAMPLE_COUNT_2_BIT
> > > SAMPLE_COUNT_4_BIT
> > > SAMPLE_COUNT_8_BIT
> > > sampledImageDepthSampleCounts: count = 4
> > > SAMPLE_COUNT_1_BIT
> > > SAMPLE_COUNT_2_BIT
> > > SAMPLE_COUNT_4_BIT
> > > SAMPLE_COUNT_8_BIT
> > > sampledImageStencilSampleCounts: count = 4
> > > SAMPLE_COUNT_1_BIT
> > > SAMPLE_COUNT_2_BIT
> > > SAMPLE_COUNT_4_BIT
> > > SAMPLE_COUNT_8_BIT
> > > storageImageSampleCounts: count = 4
> > > SAMPLE_COUNT_1_BIT
> > > SAMPLE_COUNT_2_BIT
> > > SAMPLE_COUNT_4_BIT
> > > SAMPLE_COUNT_8_BIT
> > > maxSampleMaskWords = 1
> > > timestampComputeAndGraphics = false
> > > timestampPeriod = 0
> > > maxClipDistances = 8
> > > maxCullDistances = 8
> > > maxCombinedClipAndCullDistances = 8
> > > discreteQueuePriorities = 2
> > > pointSizeRange: count = 2
> > > 1
> > > 511
> > > lineWidthRange: count = 2
> > > 0.0625
> > > 16
> > > pointSizeGranularity = 0.0625
> > > lineWidthGranularity = 0.0625
> > > strictLines = false
> > > standardSampleLocations = true
> > > optimalBufferCopyOffsetAlignment = 0x00000004
> > > optimalBufferCopyRowPitchAlignment = 0x00000004
> > > nonCoherentAtomSize = 0x00000001
> > >
> > > VkPhysicalDeviceSparseProperties:
> > > ---------------------------------
> > > residencyStandard2DBlockShape = false
> > > residencyStandard2DMultisampleBlockShape = false
> > > residencyStandard3DBlockShape = false
> > > residencyAlignedMipSize = false
> > > residencyNonResidentStrict = false
> > >
> > > VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT:
> > > --------------------------------------------------
> > > storageTexelBufferOffsetAlignmentBytes = 0x00000010
> > > storageTexelBufferOffsetSingleTexelAlignment = true
> > > uniformTexelBufferOffsetAlignmentBytes = 0x00000010
> > > uniformTexelBufferOffsetSingleTexelAlignment = false
> > >
> > > VkPhysicalDeviceTimelineSemaphorePropertiesKHR:
> > > -----------------------------------------------
> > > maxTimelineSemaphoreValueDifference = 18446744073709551615
> > >
> > > Device Extensions: count = 20
> > > VK_EXT_external_memory_dma_buf : extension revision 1
> > > VK_EXT_host_query_reset : extension revision 1
> > > VK_EXT_private_data : extension revision 1
> > > VK_EXT_scalar_block_layout : extension revision 1
> > > VK_EXT_texel_buffer_alignment : extension revision 1
> > > VK_EXT_tooling_info : extension revision 1
> > > VK_KHR_bind_memory2 : extension revision 1
> > > VK_KHR_copy_commands2 : extension revision 1
> > > VK_KHR_external_fence : extension revision 1
> > > VK_KHR_external_fence_fd : extension revision 1
> > > VK_KHR_external_memory : extension revision 1
> > > VK_KHR_external_memory_fd : extension revision 1
> > > VK_KHR_external_semaphore : extension revision 1
> > > VK_KHR_external_semaphore_fd : extension revision 1
> > > VK_KHR_format_feature_flags2 : extension revision 2
> > > VK_KHR_get_memory_requirements2 : extension revision 1
> > > VK_KHR_image_format_list : extension revision 1
> > > VK_KHR_swapchain : extension revision 70
> > > VK_KHR_timeline_semaphore : extension revision 2
> > > VK_KHR_uniform_buffer_standard_layout : extension revision 1
> > >
> > > VkQueueFamilyProperties:
> > > ========================
> > > queueProperties[0]:
> > > -------------------
> > > minImageTransferGranularity = (1,1,1)
> > > queueCount = 2
> > > queueFlags = QUEUE_GRAPHICS_BIT | QUEUE_COMPUTE_BIT | QUEUE_TRANSFER_BIT
> > > timestampValidBits = 0
> > > present support = false
> > >
> > > VkPhysicalDeviceMemoryProperties:
> > > =================================
> > > memoryHeaps: count = 1
> > > memoryHeaps[0]:
> > > size = 1752969216 (0x687c3000) (1.63 GiB)
> > > flags: count = 1
> > > MEMORY_HEAP_DEVICE_LOCAL_BIT
> > > memoryTypes: count = 1
> > > memoryTypes[0]:
> > > heapIndex = 0
> > > propertyFlags = 0x0007: count = 3
> > > MEMORY_PROPERTY_DEVICE_LOCAL_BIT
> > > MEMORY_PROPERTY_HOST_VISIBLE_BIT
> > > MEMORY_PROPERTY_HOST_COHERENT_BIT
> > > usable for:
> > > IMAGE_TILING_OPTIMAL:
> > > color images
> > > FORMAT_D16_UNORM
> > > FORMAT_D32_SFLOAT
> > > FORMAT_S8_UINT
> > > FORMAT_D24_UNORM_S8_UINT
> > > (non-sparse)
> > > IMAGE_TILING_LINEAR:
> > > color images
> > > (non-sparse)
> > >
> > > VkPhysicalDeviceFeatures:
> > > =========================
> > > robustBufferAccess = true
> > > fullDrawIndexUint32 = true
> > > imageCubeArray = true
> > > independentBlend = false
> > > geometryShader = false
> > > tessellationShader = false
> > > sampleRateShading = true
> > > dualSrcBlend = false
> > > logicOp = false
> > > multiDrawIndirect = true
> > > drawIndirectFirstInstance = true
> > > depthClamp = true
> > > depthBiasClamp = true
> > > fillModeNonSolid = false
> > > depthBounds = false
> > > wideLines = true
> > > largePoints = true
> > > alphaToOne = false
> > > multiViewport = false
> > > samplerAnisotropy = false
> > > textureCompressionETC2 = true
> > > textureCompressionASTC_LDR = false
> > > textureCompressionBC = false
> > > occlusionQueryPrecise = false
> > > pipelineStatisticsQuery = false
> > > vertexPipelineStoresAndAtomics = true
> > > fragmentStoresAndAtomics = true
> > > shaderTessellationAndGeometryPointSize = false
> > > shaderImageGatherExtended = false
> > > shaderStorageImageExtendedFormats = true
> > > shaderStorageImageMultisample = false
> > > shaderStorageImageReadWithoutFormat = true
> > > shaderStorageImageWriteWithoutFormat = false
> > > shaderUniformBufferArrayDynamicIndexing = true
> > > shaderSampledImageArrayDynamicIndexing = true
> > > shaderStorageBufferArrayDynamicIndexing = true
> > > shaderStorageImageArrayDynamicIndexing = true
> > > shaderClipDistance = false
> > > shaderCullDistance = false
> > > shaderFloat64 = false
> > > shaderInt64 = true
> > > shaderInt16 = true
> > > shaderResourceResidency = false
> > > shaderResourceMinLod = false
> > > sparseBinding = false
> > > sparseResidencyBuffer = false
> > > sparseResidencyImage2D = false
> > > sparseResidencyImage3D = false
> > > sparseResidency2Samples = false
> > > sparseResidency4Samples = false
> > > sparseResidency8Samples = false
> > > sparseResidency16Samples = false
> > > sparseResidencyAliased = false
> > > variableMultisampleRate = false
> > > inheritedQueries = false
> > >
> > > VkPhysicalDeviceHostQueryResetFeaturesEXT:
> > > ------------------------------------------
> > > hostQueryReset = true
> > >
> > > VkPhysicalDevicePrivateDataFeaturesEXT:
> > > ---------------------------------------
> > > privateData = true
> > >
> > > VkPhysicalDeviceScalarBlockLayoutFeaturesEXT:
> > > ---------------------------------------------
> > > scalarBlockLayout = true
> > >
> > > VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT:
> > > ------------------------------------------------
> > > texelBufferAlignment = true
> > >
> > > VkPhysicalDeviceTimelineSemaphoreFeaturesKHR:
> > > ---------------------------------------------
> > > timelineSemaphore = true
> > >
> > > VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR:
> > > -------------------------------------------------------
> > > uniformBufferStandardLayout = true
> > >
> > >
> > > GPU1:
> > > VkPhysicalDeviceProperties:
> > > ---------------------------
> > > apiVersion = 1.3.274 (4206866)
> > > driverVersion = 0.0.1 (1)
> > > vendorID = 0x10005
> > > deviceID = 0x0000
> > > deviceType = PHYSICAL_DEVICE_TYPE_CPU
> > > deviceName = llvmpipe (LLVM 17.0.6, 128 bits)
> > > pipelineCacheUUID = 32342e30-2e38-2d31-2b70-316161616161
> > >
> > > VkPhysicalDeviceLimits:
> > > -----------------------
> > > maxImageDimension1D = 16384
> > > maxImageDimension2D = 16384
> > > maxImageDimension3D = 4096
> > > maxImageDimensionCube = 32768
> > > maxImageArrayLayers = 2048
> > > maxTexelBufferElements = 134217728
> > > maxUniformBufferRange = 65536
> > > maxStorageBufferRange = 134217728
> > > maxPushConstantsSize = 256
> > > maxMemoryAllocationCount = 4294967295
> > > maxSamplerAllocationCount = 32768
> > > bufferImageGranularity = 0x00000040
> > > sparseAddressSpaceSize = 0x00000000
> > > maxBoundDescriptorSets = 8
> > > maxPerStageDescriptorSamplers = 1000000
> > > maxPerStageDescriptorUniformBuffers = 1000000
> > > maxPerStageDescriptorStorageBuffers = 1000000
> > > maxPerStageDescriptorSampledImages = 1000000
> > > maxPerStageDescriptorStorageImages = 1000000
> > > maxPerStageDescriptorInputAttachments = 1000000
> > > maxPerStageResources = 1000000
> > > maxDescriptorSetSamplers = 1000000
> > > maxDescriptorSetUniformBuffers = 1000000
> > > maxDescriptorSetUniformBuffersDynamic = 1000000
> > > maxDescriptorSetStorageBuffers = 1000000
> > > maxDescriptorSetStorageBuffersDynamic = 1000000
> > > maxDescriptorSetSampledImages = 1000000
> > > maxDescriptorSetStorageImages = 1000000
> > > maxDescriptorSetInputAttachments = 1000000
> > > maxVertexInputAttributes = 32
> > > maxVertexInputBindings = 32
> > > maxVertexInputAttributeOffset = 2047
> > > maxVertexInputBindingStride = 2048
> > > maxVertexOutputComponents = 128
> > > maxTessellationGenerationLevel = 64
> > > maxTessellationPatchSize = 32
> > > maxTessellationControlPerVertexInputComponents = 128
> > > maxTessellationControlPerVertexOutputComponents = 128
> > > maxTessellationControlPerPatchOutputComponents = 128
> > > maxTessellationControlTotalOutputComponents = 4096
> > > maxTessellationEvaluationInputComponents = 128
> > > maxTessellationEvaluationOutputComponents = 128
> > > maxGeometryShaderInvocations = 32
> > > maxGeometryInputComponents = 64
> > > maxGeometryOutputComponents = 128
> > > maxGeometryOutputVertices = 1024
> > > maxGeometryTotalOutputComponents = 1024
> > > maxFragmentInputComponents = 128
> > > maxFragmentOutputAttachments = 8
> > > maxFragmentDualSrcAttachments = 2
> > > maxFragmentCombinedOutputResources = 104
> > > maxComputeSharedMemorySize = 32768
> > > maxComputeWorkGroupCount: count = 3
> > > 65535
> > > 65535
> > > 65535
> > > maxComputeWorkGroupInvocations = 1024
> > > maxComputeWorkGroupSize: count = 3
> > > 1024
> > > 1024
> > > 1024
> > > subPixelPrecisionBits = 8
> > > subTexelPrecisionBits = 8
> > > mipmapPrecisionBits = 4
> > > maxDrawIndexedIndexValue = 4294967295
> > > maxDrawIndirectCount = 4294967295
> > > maxSamplerLodBias = 16
> > > maxSamplerAnisotropy = 16
> > > maxViewports = 16
> > > maxViewportDimensions: count = 2
> > > 16384
> > > 16384
> > > viewportBoundsRange: count = 2
> > > -32768
> > > 32768
> > > viewportSubPixelBits = 0
> > > minMemoryMapAlignment = 64
> > > minTexelBufferOffsetAlignment = 0x00000010
> > > minUniformBufferOffsetAlignment = 0x00000010
> > > minStorageBufferOffsetAlignment = 0x00000010
> > > minTexelOffset = -32
> > > maxTexelOffset = 31
> > > minTexelGatherOffset = -32
> > > maxTexelGatherOffset = 31
> > > minInterpolationOffset = -2
> > > maxInterpolationOffset = 2
> > > subPixelInterpolationOffsetBits = 8
> > > maxFramebufferWidth = 16384
> > > maxFramebufferHeight = 16384
> > > maxFramebufferLayers = 2048
> > > framebufferColorSampleCounts: count = 2
> > > SAMPLE_COUNT_1_BIT
> > > SAMPLE_COUNT_4_BIT
> > > framebufferDepthSampleCounts: count = 2
> > > SAMPLE_COUNT_1_BIT
> > > SAMPLE_COUNT_4_BIT
> > > framebufferStencilSampleCounts: count = 2
> > > SAMPLE_COUNT_1_BIT
> > > SAMPLE_COUNT_4_BIT
> > > framebufferNoAttachmentsSampleCounts: count = 2
> > > SAMPLE_COUNT_1_BIT
> > > SAMPLE_COUNT_4_BIT
> > > maxColorAttachments = 8
> > > sampledImageColorSampleCounts: count = 2
> > > SAMPLE_COUNT_1_BIT
> > > SAMPLE_COUNT_4_BIT
> > > sampledImageIntegerSampleCounts: count = 2
> > > SAMPLE_COUNT_1_BIT
> > > SAMPLE_COUNT_4_BIT
> > > sampledImageDepthSampleCounts: count = 2
> > > SAMPLE_COUNT_1_BIT
> > > SAMPLE_COUNT_4_BIT
> > > sampledImageStencilSampleCounts: count = 2
> > > SAMPLE_COUNT_1_BIT
> > > SAMPLE_COUNT_4_BIT
> > > storageImageSampleCounts: count = 2
> > > SAMPLE_COUNT_1_BIT
> > > SAMPLE_COUNT_4_BIT
> > > maxSampleMaskWords = 1
> > > timestampComputeAndGraphics = true
> > > timestampPeriod = 1
> > > maxClipDistances = 8
> > > maxCullDistances = 8
> > > maxCombinedClipAndCullDistances = 8
> > > discreteQueuePriorities = 2
> > > pointSizeRange: count = 2
> > > 0
> > > 255
> > > lineWidthRange: count = 2
> > > 1
> > > 255
> > > pointSizeGranularity = 0.125
> > > lineWidthGranularity = 0.0078125
> > > strictLines = true
> > > standardSampleLocations = true
> > > optimalBufferCopyOffsetAlignment = 0x00000080
> > > optimalBufferCopyRowPitchAlignment = 0x00000080
> > > nonCoherentAtomSize = 0x00000040
> > >
> > > VkPhysicalDeviceSparseProperties:
> > > ---------------------------------
> > > residencyStandard2DBlockShape = false
> > > residencyStandard2DMultisampleBlockShape = false
> > > residencyStandard3DBlockShape = false
> > > residencyAlignedMipSize = false
> > > residencyNonResidentStrict = false
> > >
> > > VkPhysicalDeviceCustomBorderColorPropertiesEXT:
> > > -----------------------------------------------
> > > maxCustomBorderColorSamplers = 32768
> > >
> > > VkPhysicalDeviceDescriptorBufferDensityMapPropertiesEXT:
> > > --------------------------------------------------------
> > > combinedImageSamplerDensityMapDescriptorSize = 0
> > >
> > > VkPhysicalDeviceDescriptorBufferPropertiesEXT:
> > > ----------------------------------------------
> > > combinedImageSamplerDescriptorSingleArray = true
> > > bufferlessPushDescriptors = true
> > > allowSamplerImageViewPostSubmitCreation = false
> > > descriptorBufferOffsetAlignment = 0x00000004
> > > maxDescriptorBufferBindings = 8
> > > maxResourceDescriptorBufferBindings = 8
> > > maxSamplerDescriptorBufferBindings = 8
> > > maxEmbeddedImmutableSamplerBindings = 8
> > > maxEmbeddedImmutableSamplers = 2032
> > > bufferCaptureReplayDescriptorDataSize = 0
> > > imageCaptureReplayDescriptorDataSize = 0
> > > imageViewCaptureReplayDescriptorDataSize = 0
> > > samplerCaptureReplayDescriptorDataSize = 0
> > > accelerationStructureCaptureReplayDescriptorDataSize = 0
> > > samplerDescriptorSize = 256
> > > combinedImageSamplerDescriptorSize = 256
> > > sampledImageDescriptorSize = 256
> > > storageImageDescriptorSize = 256
> > > uniformTexelBufferDescriptorSize = 256
> > > robustUniformTexelBufferDescriptorSize = 256
> > > storageTexelBufferDescriptorSize = 256
> > > robustStorageTexelBufferDescriptorSize = 256
> > > uniformBufferDescriptorSize = 256
> > > robustUniformBufferDescriptorSize = 256
> > > storageBufferDescriptorSize = 256
> > > robustStorageBufferDescriptorSize = 256
> > > inputAttachmentDescriptorSize = 256
> > > accelerationStructureDescriptorSize = 0
> > > maxSamplerDescriptorBufferRange = 0x08000000
> > > maxResourceDescriptorBufferRange = 0x10000000
> > > samplerDescriptorBufferAddressSpaceSize = 0x08000000
> > > resourceDescriptorBufferAddressSpaceSize = 0x08000000
> > > descriptorBufferAddressSpaceSize = 0x08000000
> > >
> > > VkPhysicalDeviceExtendedDynamicState3PropertiesEXT:
> > > ---------------------------------------------------
> > > dynamicPrimitiveTopologyUnrestricted = true
> > >
> > > VkPhysicalDeviceExternalMemoryHostPropertiesEXT:
> > > ------------------------------------------------
> > > minImportedHostPointerAlignment = 0x00001000
> > >
> > > VkPhysicalDeviceGraphicsPipelineLibraryPropertiesEXT:
> > > -----------------------------------------------------
> > > graphicsPipelineLibraryFastLinking = true
> > > graphicsPipelineLibraryIndependentInterpolationDecoration = true
> > >
> > > VkPhysicalDeviceLineRasterizationPropertiesKHR:
> > > -----------------------------------------------
> > > lineSubPixelPrecisionBits = 8
> > >
> > > VkPhysicalDeviceMaintenance5PropertiesKHR:
> > > ------------------------------------------
> > > earlyFragmentMultisampleCoverageAfterSampleCounting = true
> > > earlyFragmentSampleMaskTestBeforeSampleCounting = false
> > > depthStencilSwizzleOneSupport = false
> > > polygonModePointSize = true
> > > nonStrictSinglePixelWideLinesUseParallelogram = false
> > > nonStrictWideLinesUseParallelogram = false
> > >
> > > VkPhysicalDeviceMaintenance6PropertiesKHR:
> > > ------------------------------------------
> > > blockTexelViewCompatibleMultipleLayers = true
> > > maxCombinedImageSamplerDescriptorCount = 3
> > > fragmentShadingRateClampCombinerInputs = false
> > >
> > > VkPhysicalDeviceMeshShaderPropertiesEXT:
> > > ----------------------------------------
> > > maxTaskWorkGroupTotalCount = 4194304
> > > maxTaskWorkGroupCount: count = 3
> > > 65536
> > > 65536
> > > 65536
> > > maxTaskWorkGroupInvocations = 1024
> > > maxTaskWorkGroupSize: count = 3
> > > 1024
> > > 1024
> > > 1024
> > > maxTaskPayloadSize = 16384
> > > maxTaskSharedMemorySize = 32768
> > > maxTaskPayloadAndSharedMemorySize = 32768
> > > maxMeshWorkGroupTotalCount = 4194304
> > > maxMeshWorkGroupCount: count = 3
> > > 65536
> > > 65536
> > > 65536
> > > maxMeshWorkGroupInvocations = 1024
> > > maxMeshWorkGroupSize: count = 3
> > > 1024
> > > 1024
> > > 1024
> > > maxMeshSharedMemorySize = 28672
> > > maxMeshPayloadAndSharedMemorySize = 45056
> > > maxMeshOutputMemorySize = 32768
> > > maxMeshPayloadAndOutputMemorySize = 49152
> > > maxMeshOutputComponents = 128
> > > maxMeshOutputVertices = 256
> > > maxMeshOutputPrimitives = 256
> > > maxMeshOutputLayers = 8
> > > maxMeshMultiviewViewCount = 0
> > > meshOutputPerVertexGranularity = 1
> > > meshOutputPerPrimitiveGranularity = 1
> > > maxPreferredTaskWorkGroupInvocations = 64
> > > maxPreferredMeshWorkGroupInvocations = 128
> > > prefersLocalInvocationVertexOutput = true
> > > prefersLocalInvocationPrimitiveOutput = true
> > > prefersCompactVertexOutput = true
> > > prefersCompactPrimitiveOutput = false
> > >
> > > VkPhysicalDeviceMultiDrawPropertiesEXT:
> > > ---------------------------------------
> > > maxMultiDrawCount = 2048
> > >
> > > VkPhysicalDeviceNestedCommandBufferPropertiesEXT:
> > > -------------------------------------------------
> > > maxCommandBufferNestingLevel = 4294967295
> > >
> > > VkPhysicalDeviceProvokingVertexPropertiesEXT:
> > > ---------------------------------------------
> > > provokingVertexModePerPipeline = true
> > > transformFeedbackPreservesTriangleFanProvokingVertex = true
> > >
> > > VkPhysicalDevicePushDescriptorPropertiesKHR:
> > > --------------------------------------------
> > > maxPushDescriptors = 32
> > >
> > > VkPhysicalDeviceRobustness2PropertiesEXT:
> > > -----------------------------------------
> > > robustStorageBufferAccessSizeAlignment = 0x00000001
> > > robustUniformBufferAccessSizeAlignment = 0x00000001
> > >
> > > VkPhysicalDeviceShaderObjectPropertiesEXT:
> > > ------------------------------------------
> > > shaderBinaryUUID = 32342e30-2e38-2d31-2b70-316161616161
> > > shaderBinaryVersion = 1
> > >
> > > VkPhysicalDeviceTransformFeedbackPropertiesEXT:
> > > -----------------------------------------------
> > > maxTransformFeedbackStreams = 4
> > > maxTransformFeedbackBuffers = 4
> > > maxTransformFeedbackBufferSize = 0xffffffff
> > > maxTransformFeedbackStreamDataSize = 512
> > > maxTransformFeedbackBufferDataSize = 512
> > > maxTransformFeedbackBufferDataStride = 512
> > > transformFeedbackQueries = true
> > > transformFeedbackStreamsLinesTriangles = false
> > > transformFeedbackRasterizationStreamSelect = false
> > > transformFeedbackDraw = true
> > >
> > > VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT:
> > > ----------------------------------------------------
> > > maxVertexAttribDivisor = 4294967295
> > >
> > > VkPhysicalDeviceVulkan11Properties:
> > > -----------------------------------
> > > deviceUUID = 6d657361-3234-2e30-2e38-2d312b703100
> > > driverUUID = 6c6c766d-7069-7065-5555-494400000000
> > > deviceNodeMask = 0
> > > deviceLUIDValid = false
> > > subgroupSize = 4
> > > subgroupSupportedStages: count = 4
> > > SHADER_STAGE_FRAGMENT_BIT
> > > SHADER_STAGE_COMPUTE_BIT
> > > SHADER_STAGE_TASK_BIT_EXT
> > > SHADER_STAGE_MESH_BIT_EXT
> > > subgroupSupportedOperations: count = 7
> > > SUBGROUP_FEATURE_BASIC_BIT
> > > SUBGROUP_FEATURE_VOTE_BIT
> > > SUBGROUP_FEATURE_ARITHMETIC_BIT
> > > SUBGROUP_FEATURE_BALLOT_BIT
> > > SUBGROUP_FEATURE_SHUFFLE_BIT
> > > SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
> > > SUBGROUP_FEATURE_QUAD_BIT
> > > subgroupQuadOperationsInAllStages = false
> > > pointClippingBehavior = POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
> > > maxMultiviewViewCount = 6
> > > maxMultiviewInstanceIndex = 2147483647
> > > protectedNoFault = false
> > > maxPerSetDescriptors = 1000000
> > > maxMemoryAllocationSize = 0x80000000
> > >
> > > VkPhysicalDeviceVulkan12Properties:
> > > -----------------------------------
> > > driverID = DRIVER_ID_MESA_LLVMPIPE
> > > driverName = llvmpipe
> > > driverInfo = Mesa 24.0.8-1+p1 (LLVM 17.0.6)
> > > conformanceVersion:
> > > major = 1
> > > minor = 3
> > > subminor = 1
> > > patch = 1
> > > denormBehaviorIndependence = SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL
> > > roundingModeIndependence = SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL
> > > shaderSignedZeroInfNanPreserveFloat16 = true
> > > shaderSignedZeroInfNanPreserveFloat32 = true
> > > shaderSignedZeroInfNanPreserveFloat64 = true
> > > shaderDenormPreserveFloat16 = false
> > > shaderDenormPreserveFloat32 = false
> > > shaderDenormPreserveFloat64 = false
> > > shaderDenormFlushToZeroFloat16 = false
> > > shaderDenormFlushToZeroFloat32 = false
> > > shaderDenormFlushToZeroFloat64 = false
> > > shaderRoundingModeRTEFloat16 = true
> > > shaderRoundingModeRTEFloat32 = true
> > > shaderRoundingModeRTEFloat64 = true
> > > shaderRoundingModeRTZFloat16 = false
> > > shaderRoundingModeRTZFloat32 = false
> > > shaderRoundingModeRTZFloat64 = false
> > > maxUpdateAfterBindDescriptorsInAllPools = 4294967295
> > > shaderUniformBufferArrayNonUniformIndexingNative = true
> > > shaderSampledImageArrayNonUniformIndexingNative = true
> > > shaderStorageBufferArrayNonUniformIndexingNative = true
> > > shaderStorageImageArrayNonUniformIndexingNative = true
> > > shaderInputAttachmentArrayNonUniformIndexingNative = true
> > > robustBufferAccessUpdateAfterBind = true
> > > quadDivergentImplicitLod = true
> > > maxPerStageDescriptorUpdateAfterBindSamplers = 1000000
> > > maxPerStageDescriptorUpdateAfterBindUniformBuffers = 1000000
> > > maxPerStageDescriptorUpdateAfterBindStorageBuffers = 1000000
> > > maxPerStageDescriptorUpdateAfterBindSampledImages = 1000000
> > > maxPerStageDescriptorUpdateAfterBindStorageImages = 1000000
> > > maxPerStageDescriptorUpdateAfterBindInputAttachments = 1000000
> > > maxPerStageUpdateAfterBindResources = 1000000
> > > maxDescriptorSetUpdateAfterBindSamplers = 1000000
> > > maxDescriptorSetUpdateAfterBindUniformBuffers = 1000000
> > > maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = 1000000
> > > maxDescriptorSetUpdateAfterBindStorageBuffers = 1000000
> > > maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = 1000000
> > > maxDescriptorSetUpdateAfterBindSampledImages = 1000000
> > > maxDescriptorSetUpdateAfterBindStorageImages = 1000000
> > > maxDescriptorSetUpdateAfterBindInputAttachments = 1000000
> > > supportedDepthResolveModes: count = 2
> > > RESOLVE_MODE_SAMPLE_ZERO_BIT
> > > RESOLVE_MODE_AVERAGE_BIT
> > > supportedStencilResolveModes: count = 1
> > > RESOLVE_MODE_SAMPLE_ZERO_BIT
> > > independentResolveNone = false
> > > independentResolve = false
> > > filterMinmaxSingleComponentFormats = true
> > > filterMinmaxImageComponentMapping = true
> > > maxTimelineSemaphoreValueDifference = 18446744073709551615
> > > framebufferIntegerColorSampleCounts: count = 1
> > > SAMPLE_COUNT_1_BIT
> > >
> > > VkPhysicalDeviceVulkan13Properties:
> > > -----------------------------------
> > > minSubgroupSize = 4
> > > maxSubgroupSize = 4
> > > maxComputeWorkgroupSubgroups = 32
> > > requiredSubgroupSizeStages: count = 2
> > > SHADER_STAGE_FRAGMENT_BIT
> > > SHADER_STAGE_COMPUTE_BIT
> > > maxInlineUniformBlockSize = 4096
> > > maxPerStageDescriptorInlineUniformBlocks = 8
> > > maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = 8
> > > maxDescriptorSetInlineUniformBlocks = 8
> > > maxDescriptorSetUpdateAfterBindInlineUniformBlocks = 8
> > > maxInlineUniformTotalSize = 262144
> > > integerDotProduct8BitUnsignedAccelerated = false
> > > integerDotProduct8BitSignedAccelerated = false
> > > integerDotProduct8BitMixedSignednessAccelerated = false
> > > integerDotProduct4x8BitPackedUnsignedAccelerated = false
> > > integerDotProduct4x8BitPackedSignedAccelerated = false
> > > integerDotProduct4x8BitPackedMixedSignednessAccelerated = false
> > > integerDotProduct16BitUnsignedAccelerated = false
> > > integerDotProduct16BitSignedAccelerated = false
> > > integerDotProduct16BitMixedSignednessAccelerated = false
> > > integerDotProduct32BitUnsignedAccelerated = false
> > > integerDotProduct32BitSignedAccelerated = false
> > > integerDotProduct32BitMixedSignednessAccelerated = false
> > > integerDotProduct64BitUnsignedAccelerated = false
> > > integerDotProduct64BitSignedAccelerated = false
> > > integerDotProduct64BitMixedSignednessAccelerated = false
> > > integerDotProductAccumulatingSaturating8BitUnsignedAccelerated = false
> > > integerDotProductAccumulatingSaturating8BitSignedAccelerated = false
> > > integerDotProductAccumulatingSaturating8BitMixedSignednessAccelerated = false
> > > integerDotProductAccumulatingSaturating4x8BitPackedUnsignedAccelerated = false
> > > integerDotProductAccumulatingSaturating4x8BitPackedSignedAccelerated = false
> > > integerDotProductAccumulatingSaturating4x8BitPackedMixedSignednessAccelerated = false
> > > integerDotProductAccumulatingSaturating16BitUnsignedAccelerated = false
> > > integerDotProductAccumulatingSaturating16BitSignedAccelerated = false
> > > integerDotProductAccumulatingSaturating16BitMixedSignednessAccelerated = false
> > > integerDotProductAccumulatingSaturating32BitUnsignedAccelerated = false
> > > integerDotProductAccumulatingSaturating32BitSignedAccelerated = false
> > > integerDotProductAccumulatingSaturating32BitMixedSignednessAccelerated = false
> > > integerDotProductAccumulatingSaturating64BitUnsignedAccelerated = false
> > > integerDotProductAccumulatingSaturating64BitSignedAccelerated = false
> > > integerDotProductAccumulatingSaturating64BitMixedSignednessAccelerated = false
> > > storageTexelBufferOffsetAlignmentBytes = 0x00000010
> > > storageTexelBufferOffsetSingleTexelAlignment = true
> > > uniformTexelBufferOffsetAlignmentBytes = 0x00000010
> > > uniformTexelBufferOffsetSingleTexelAlignment = true
> > > maxBufferSize = 0xffffffff
> > >
> > > VkPhysicalDeviceHostImageCopyPropertiesEXT:
> > > -------------------------------------------
> > > copySrcLayoutCount = 23
> > > pCopySrcLayouts: count = 23
> > > IMAGE_LAYOUT_GENERAL
> > > IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
> > > IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
> > > IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
> > > IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
> > > IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
> > > IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
> > > IMAGE_LAYOUT_PREINITIALIZED
> > > IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
> > > IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL
> > > IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL
> > > IMAGE_LAYOUT_DEPTH_READ_ONLY_OPTIMAL
> > > IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL
> > > IMAGE_LAYOUT_STENCIL_READ_ONLY_OPTIMAL
> > > IMAGE_LAYOUT_READ_ONLY_OPTIMAL
> > > IMAGE_LAYOUT_ATTACHMENT_OPTIMAL
> > > IMAGE_LAYOUT_PRESENT_SRC_KHR
> > > IMAGE_LAYOUT_VIDEO_DECODE_DST_KHR
> > > IMAGE_LAYOUT_VIDEO_DECODE_SRC_KHR
> > > IMAGE_LAYOUT_VIDEO_DECODE_DPB_KHR
> > > IMAGE_LAYOUT_SHARED_PRESENT_KHR
> > > IMAGE_LAYOUT_FRAGMENT_DENSITY_MAP_OPTIMAL_EXT
> > > IMAGE_LAYOUT_FRAGMENT_SHADING_RATE_ATTACHMENT_OPTIMAL_KHR
> > > copyDstLayoutCount = 23
> > > pCopyDstLayouts: count = 23
> > > IMAGE_LAYOUT_GENERAL
> > > IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
> > > IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
> > > IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
> > > IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
> > > IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
> > > IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
> > > IMAGE_LAYOUT_PREINITIALIZED
> > > IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
> > > IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL
> > > IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL
> > > IMAGE_LAYOUT_DEPTH_READ_ONLY_OPTIMAL
> > > IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL
> > > IMAGE_LAYOUT_STENCIL_READ_ONLY_OPTIMAL
> > > IMAGE_LAYOUT_READ_ONLY_OPTIMAL
> > > IMAGE_LAYOUT_ATTACHMENT_OPTIMAL
> > > IMAGE_LAYOUT_PRESENT_SRC_KHR
> > > IMAGE_LAYOUT_VIDEO_DECODE_DST_KHR
> > > IMAGE_LAYOUT_VIDEO_DECODE_SRC_KHR
> > > IMAGE_LAYOUT_VIDEO_DECODE_DPB_KHR
> > > IMAGE_LAYOUT_SHARED_PRESENT_KHR
> > > IMAGE_LAYOUT_FRAGMENT_DENSITY_MAP_OPTIMAL_EXT
> > > IMAGE_LAYOUT_FRAGMENT_SHADING_RATE_ATTACHMENT_OPTIMAL_KHR
> > > optimalTilingLayoutUUID = 32342e30-2e38-2d31-2b70-316161616161
> > > identicalMemoryTypeRequirements = false
> > >
> > > Device Extensions: count = 124
> > > VK_AMDX_shader_enqueue : extension revision 1
> > > VK_ARM_rasterization_order_attachment_access : extension revision 1
> > > VK_EXT_4444_formats : extension revision 1
> > > VK_EXT_attachment_feedback_loop_dynamic_state : extension revision 1
> > > VK_EXT_attachment_feedback_loop_layout : extension revision 2
> > > VK_EXT_border_color_swizzle : extension revision 1
> > > VK_EXT_calibrated_timestamps : extension revision 2
> > > VK_EXT_color_write_enable : extension revision 1
> > > VK_EXT_conditional_rendering : extension revision 2
> > > VK_EXT_custom_border_color : extension revision 12
> > > VK_EXT_depth_clip_control : extension revision 1
> > > VK_EXT_depth_clip_enable : extension revision 1
> > > VK_EXT_depth_range_unrestricted : extension revision 1
> > > VK_EXT_descriptor_buffer : extension revision 1
> > > VK_EXT_descriptor_indexing : extension revision 2
> > > VK_EXT_dynamic_rendering_unused_attachments : extension revision 1
> > > VK_EXT_extended_dynamic_state : extension revision 1
> > > VK_EXT_extended_dynamic_state2 : extension revision 1
> > > VK_EXT_extended_dynamic_state3 : extension revision 2
> > > VK_EXT_external_memory_host : extension revision 1
> > > VK_EXT_graphics_pipeline_library : extension revision 1
> > > VK_EXT_host_image_copy : extension revision 1
> > > VK_EXT_host_query_reset : extension revision 1
> > > VK_EXT_image_2d_view_of_3d : extension revision 1
> > > VK_EXT_image_robustness : extension revision 1
> > > VK_EXT_image_sliced_view_of_3d : extension revision 1
> > > VK_EXT_index_type_uint8 : extension revision 1
> > > VK_EXT_inline_uniform_block : extension revision 1
> > > VK_EXT_line_rasterization : extension revision 1
> > > VK_EXT_load_store_op_none : extension revision 1
> > > VK_EXT_memory_budget : extension revision 1
> > > VK_EXT_memory_priority : extension revision 1
> > > VK_EXT_mesh_shader : extension revision 1
> > > VK_EXT_multi_draw : extension revision 1
> > > VK_EXT_multisampled_render_to_single_sampled : extension revision 1
> > > VK_EXT_mutable_descriptor_type : extension revision 1
> > > VK_EXT_nested_command_buffer : extension revision 1
> > > VK_EXT_non_seamless_cube_map : extension revision 1
> > > VK_EXT_pageable_device_local_memory : extension revision 1
> > > VK_EXT_pipeline_creation_cache_control : extension revision 3
> > > VK_EXT_pipeline_creation_feedback : extension revision 1
> > > VK_EXT_post_depth_coverage : extension revision 1
> > > VK_EXT_primitive_topology_list_restart : extension revision 1
> > > VK_EXT_primitives_generated_query : extension revision 1
> > > VK_EXT_private_data : extension revision 1
> > > VK_EXT_provoking_vertex : extension revision 1
> > > VK_EXT_rasterization_order_attachment_access : extension revision 1
> > > VK_EXT_robustness2 : extension revision 1
> > > VK_EXT_sampler_filter_minmax : extension revision 2
> > > VK_EXT_scalar_block_layout : extension revision 1
> > > VK_EXT_separate_stencil_usage : extension revision 1
> > > VK_EXT_shader_atomic_float : extension revision 1
> > > VK_EXT_shader_atomic_float2 : extension revision 1
> > > VK_EXT_shader_demote_to_helper_invocation : extension revision 1
> > > VK_EXT_shader_object : extension revision 1
> > > VK_EXT_shader_stencil_export : extension revision 1
> > > VK_EXT_shader_subgroup_ballot : extension revision 1
> > > VK_EXT_shader_subgroup_vote : extension revision 1
> > > VK_EXT_shader_viewport_index_layer : extension revision 1
> > > VK_EXT_subgroup_size_control : extension revision 2
> > > VK_EXT_texel_buffer_alignment : extension revision 1
> > > VK_EXT_transform_feedback : extension revision 1
> > > VK_EXT_vertex_attribute_divisor : extension revision 3
> > > VK_EXT_vertex_input_dynamic_state : extension revision 2
> > > VK_EXT_ycbcr_2plane_444_formats : extension revision 1
> > > VK_EXT_ycbcr_image_arrays : extension revision 1
> > > VK_GOOGLE_decorate_string : extension revision 1
> > > VK_GOOGLE_hlsl_functionality1 : extension revision 1
> > > VK_KHR_16bit_storage : extension revision 1
> > > VK_KHR_8bit_storage : extension revision 1
> > > VK_KHR_bind_memory2 : extension revision 1
> > > VK_KHR_buffer_device_address : extension revision 1
> > > VK_KHR_copy_commands2 : extension revision 1
> > > VK_KHR_create_renderpass2 : extension revision 1
> > > VK_KHR_dedicated_allocation : extension revision 3
> > > VK_KHR_depth_stencil_resolve : extension revision 1
> > > VK_KHR_descriptor_update_template : extension revision 1
> > > VK_KHR_device_group : extension revision 4
> > > VK_KHR_draw_indirect_count : extension revision 1
> > > VK_KHR_driver_properties : extension revision 1
> > > VK_KHR_dynamic_rendering : extension revision 1
> > > VK_KHR_external_fence : extension revision 1
> > > VK_KHR_external_memory : extension revision 1
> > > VK_KHR_external_memory_fd : extension revision 1
> > > VK_KHR_external_semaphore : extension revision 1
> > > VK_KHR_format_feature_flags2 : extension revision 2
> > > VK_KHR_get_memory_requirements2 : extension revision 1
> > > VK_KHR_image_format_list : extension revision 1
> > > VK_KHR_imageless_framebuffer : extension revision 1
> > > VK_KHR_incremental_present : extension revision 2
> > > VK_KHR_maintenance1 : extension revision 2
> > > VK_KHR_maintenance2 : extension revision 1
> > > VK_KHR_maintenance3 : extension revision 1
> > > VK_KHR_maintenance4 : extension revision 2
> > > VK_KHR_maintenance5 : extension revision 1
> > > VK_KHR_maintenance6 : extension revision 1
> > > VK_KHR_map_memory2 : extension revision 1
> > > VK_KHR_multiview : extension revision 1
> > > VK_KHR_pipeline_library : extension revision 1
> > > VK_KHR_push_descriptor : extension revision 2
> > > VK_KHR_relaxed_block_layout : extension revision 1
> > > VK_KHR_sampler_mirror_clamp_to_edge : extension revision 3
> > > VK_KHR_sampler_ycbcr_conversion : extension revision 14
> > > VK_KHR_separate_depth_stencil_layouts : extension revision 1
> > > VK_KHR_shader_atomic_int64 : extension revision 1
> > > VK_KHR_shader_clock : extension revision 1
> > > VK_KHR_shader_draw_parameters : extension revision 1
> > > VK_KHR_shader_float16_int8 : extension revision 1
> > > VK_KHR_shader_float_controls : extension revision 4
> > > VK_KHR_shader_integer_dot_product : extension revision 1
> > > VK_KHR_shader_non_semantic_info : extension revision 1
> > > VK_KHR_shader_subgroup_extended_types : extension revision 1
> > > VK_KHR_shader_terminate_invocation : extension revision 1
> > > VK_KHR_spirv_1_4 : extension revision 1
> > > VK_KHR_storage_buffer_storage_class : extension revision 1
> > > VK_KHR_swapchain : extension revision 70
> > > VK_KHR_swapchain_mutable_format : extension revision 1
> > > VK_KHR_synchronization2 : extension revision 1
> > > VK_KHR_timeline_semaphore : extension revision 2
> > > VK_KHR_uniform_buffer_standard_layout : extension revision 1
> > > VK_KHR_variable_pointers : extension revision 1
> > > VK_KHR_vulkan_memory_model : extension revision 3
> > > VK_KHR_zero_initialize_workgroup_memory : extension revision 1
> > > VK_NV_device_generated_commands : extension revision 3
> > >
> > > VkQueueFamilyProperties:
> > > ========================
> > > queueProperties[0]:
> > > -------------------
> > > minImageTransferGranularity = (1,1,1)
> > > queueCount = 1
> > > queueFlags = QUEUE_GRAPHICS_BIT | QUEUE_COMPUTE_BIT | QUEUE_TRANSFER_BIT
> > > timestampValidBits = 64
> > > present support = false
> > >
> > > VkPhysicalDeviceMemoryProperties:
> > > =================================
> > > memoryHeaps: count = 1
> > > memoryHeaps[0]:
> > > size = 3505938432 (0xd0f86000) (3.27 GiB)
> > > budget = 3505938432 (0xd0f86000) (3.27 GiB)
> > > usage = 522092544 (0x1f1e8000) (497.91 MiB)
> > > flags: count = 1
> > > MEMORY_HEAP_DEVICE_LOCAL_BIT
> > > memoryTypes: count = 1
> > > memoryTypes[0]:
> > > heapIndex = 0
> > > propertyFlags = 0x000f: count = 4
> > > MEMORY_PROPERTY_DEVICE_LOCAL_BIT
> > > MEMORY_PROPERTY_HOST_VISIBLE_BIT
> > > MEMORY_PROPERTY_HOST_COHERENT_BIT
> > > MEMORY_PROPERTY_HOST_CACHED_BIT
> > > usable for:
> > > IMAGE_TILING_OPTIMAL:
> > > color images
> > > FORMAT_D16_UNORM
> > > FORMAT_X8_D24_UNORM_PACK32
> > > FORMAT_D32_SFLOAT
> > > FORMAT_S8_UINT
> > > FORMAT_D24_UNORM_S8_UINT
> > > FORMAT_D32_SFLOAT_S8_UINT
> > > (non-sparse)
> > > IMAGE_TILING_LINEAR:
> > > color images
> > > (non-sparse)
> > >
> > > VkPhysicalDeviceFeatures:
> > > =========================
> > > robustBufferAccess = true
> > > fullDrawIndexUint32 = true
> > > imageCubeArray = true
> > > independentBlend = true
> > > geometryShader = true
> > > tessellationShader = true
> > > sampleRateShading = true
> > > dualSrcBlend = true
> > > logicOp = true
> > > multiDrawIndirect = true
> > > drawIndirectFirstInstance = true
> > > depthClamp = true
> > > depthBiasClamp = true
> > > fillModeNonSolid = true
> > > depthBounds = false
> > > wideLines = true
> > > largePoints = true
> > > alphaToOne = true
> > > multiViewport = true
> > > samplerAnisotropy = true
> > > textureCompressionETC2 = false
> > > textureCompressionASTC_LDR = false
> > > textureCompressionBC = true
> > > occlusionQueryPrecise = true
> > > pipelineStatisticsQuery = true
> > > vertexPipelineStoresAndAtomics = true
> > > fragmentStoresAndAtomics = true
> > > shaderTessellationAndGeometryPointSize = true
> > > shaderImageGatherExtended = true
> > > shaderStorageImageExtendedFormats = true
> > > shaderStorageImageMultisample = true
> > > shaderStorageImageReadWithoutFormat = true
> > > shaderStorageImageWriteWithoutFormat = true
> > > shaderUniformBufferArrayDynamicIndexing = true
> > > shaderSampledImageArrayDynamicIndexing = true
> > > shaderStorageBufferArrayDynamicIndexing = true
> > > shaderStorageImageArrayDynamicIndexing = true
> > > shaderClipDistance = true
> > > shaderCullDistance = true
> > > shaderFloat64 = true
> > > shaderInt64 = true
> > > shaderInt16 = true
> > > shaderResourceResidency = false
> > > shaderResourceMinLod = false
> > > sparseBinding = false
> > > sparseResidencyBuffer = false
> > > sparseResidencyImage2D = false
> > > sparseResidencyImage3D = false
> > > sparseResidency2Samples = false
> > > sparseResidency4Samples = false
> > > sparseResidency8Samples = false
> > > sparseResidency16Samples = false
> > > sparseResidencyAliased = false
> > > variableMultisampleRate = false
> > > inheritedQueries = false
> > >
> > > VkPhysicalDevice4444FormatsFeaturesEXT:
> > > ---------------------------------------
> > > formatA4R4G4B4 = true
> > > formatA4B4G4R4 = true
> > >
> > > VkPhysicalDeviceAttachmentFeedbackLoopDynamicStateFeaturesEXT:
> > > --------------------------------------------------------------
> > > attachmentFeedbackLoopDynamicState = true
> > >
> > > VkPhysicalDeviceAttachmentFeedbackLoopLayoutFeaturesEXT:
> > > --------------------------------------------------------
> > > attachmentFeedbackLoopLayout = true
> > >
> > > VkPhysicalDeviceBorderColorSwizzleFeaturesEXT:
> > > ----------------------------------------------
> > > borderColorSwizzle = true
> > > borderColorSwizzleFromImage = true
> > >
> > > VkPhysicalDeviceColorWriteEnableFeaturesEXT:
> > > --------------------------------------------
> > > colorWriteEnable = true
> > >
> > > VkPhysicalDeviceConditionalRenderingFeaturesEXT:
> > > ------------------------------------------------
> > > conditionalRendering = true
> > > inheritedConditionalRendering = false
> > >
> > > VkPhysicalDeviceCustomBorderColorFeaturesEXT:
> > > ---------------------------------------------
> > > customBorderColors = true
> > > customBorderColorWithoutFormat = true
> > >
> > > VkPhysicalDeviceDepthClipControlFeaturesEXT:
> > > --------------------------------------------
> > > depthClipControl = true
> > >
> > > VkPhysicalDeviceDepthClipEnableFeaturesEXT:
> > > -------------------------------------------
> > > depthClipEnable = true
> > >
> > > VkPhysicalDeviceDescriptorBufferFeaturesEXT:
> > > --------------------------------------------
> > > descriptorBuffer = true
> > > descriptorBufferCaptureReplay = false
> > > descriptorBufferImageLayoutIgnored = true
> > > descriptorBufferPushDescriptors = true
> > >
> > > VkPhysicalDeviceDynamicRenderingUnusedAttachmentsFeaturesEXT:
> > > -------------------------------------------------------------
> > > dynamicRenderingUnusedAttachments = true
> > >
> > > VkPhysicalDeviceExtendedDynamicState2FeaturesEXT:
> > > -------------------------------------------------
> > > extendedDynamicState2 = true
> > > extendedDynamicState2LogicOp = true
> > > extendedDynamicState2PatchControlPoints = true
> > >
> > > VkPhysicalDeviceExtendedDynamicState3FeaturesEXT:
> > > -------------------------------------------------
> > > extendedDynamicState3TessellationDomainOrigin = true
> > > extendedDynamicState3DepthClampEnable = true
> > > extendedDynamicState3PolygonMode = true
> > > extendedDynamicState3RasterizationSamples = true
> > > extendedDynamicState3SampleMask = true
> > > extendedDynamicState3AlphaToCoverageEnable = true
> > > extendedDynamicState3AlphaToOneEnable = true
> > > extendedDynamicState3LogicOpEnable = true
> > > extendedDynamicState3ColorBlendEnable = true
> > > extendedDynamicState3ColorBlendEquation = true
> > > extendedDynamicState3ColorWriteMask = true
> > > extendedDynamicState3RasterizationStream = false
> > > extendedDynamicState3ConservativeRasterizationMode = false
> > > extendedDynamicState3ExtraPrimitiveOverestimationSize = false
> > > extendedDynamicState3DepthClipEnable = true
> > > extendedDynamicState3SampleLocationsEnable = false
> > > extendedDynamicState3ColorBlendAdvanced = false
> > > extendedDynamicState3ProvokingVertexMode = true
> > > extendedDynamicState3LineRasterizationMode = true
> > > extendedDynamicState3LineStippleEnable = true
> > > extendedDynamicState3DepthClipNegativeOneToOne = true
> > > extendedDynamicState3ViewportWScalingEnable = false
> > > extendedDynamicState3ViewportSwizzle = false
> > > extendedDynamicState3CoverageToColorEnable = false
> > > extendedDynamicState3CoverageToColorLocation = false
> > > extendedDynamicState3CoverageModulationMode = false
> > > extendedDynamicState3CoverageModulationTableEnable = false
> > > extendedDynamicState3CoverageModulationTable = false
> > > extendedDynamicState3CoverageReductionMode = false
> > > extendedDynamicState3RepresentativeFragmentTestEnable = false
> > > extendedDynamicState3ShadingRateImageEnable = false
> > >
> > > VkPhysicalDeviceExtendedDynamicStateFeaturesEXT:
> > > ------------------------------------------------
> > > extendedDynamicState = true
> > >
> > > VkPhysicalDeviceGraphicsPipelineLibraryFeaturesEXT:
> > > ---------------------------------------------------
> > > graphicsPipelineLibrary = true
> > >
> > > VkPhysicalDeviceHostImageCopyFeaturesEXT:
> > > -----------------------------------------
> > > hostImageCopy = true
> > >
> > > VkPhysicalDeviceImage2DViewOf3DFeaturesEXT:
> > > -------------------------------------------
> > > image2DViewOf3D = true
> > > sampler2DViewOf3D = true
> > >
> > > VkPhysicalDeviceImageSlicedViewOf3DFeaturesEXT:
> > > -----------------------------------------------
> > > imageSlicedViewOf3D = true
> > >
> > > VkPhysicalDeviceIndexTypeUint8FeaturesKHR:
> > > ------------------------------------------
> > > indexTypeUint8 = true
> > >
> > > VkPhysicalDeviceLineRasterizationFeaturesKHR:
> > > ---------------------------------------------
> > > rectangularLines = true
> > > bresenhamLines = true
> > > smoothLines = true
> > > stippledRectangularLines = true
> > > stippledBresenhamLines = true
> > > stippledSmoothLines = true
> > >
> > > VkPhysicalDeviceMaintenance5FeaturesKHR:
> > > ----------------------------------------
> > > maintenance5 = true
> > >
> > > VkPhysicalDeviceMaintenance6FeaturesKHR:
> > > ----------------------------------------
> > > maintenance6 = true
> > >
> > > VkPhysicalDeviceMemoryPriorityFeaturesEXT:
> > > ------------------------------------------
> > > memoryPriority = true
> > >
> > > VkPhysicalDeviceMeshShaderFeaturesEXT:
> > > --------------------------------------
> > > taskShader = true
> > > meshShader = true
> > > multiviewMeshShader = false
> > > primitiveFragmentShadingRateMeshShader = false
> > > meshShaderQueries = true
> > >
> > > VkPhysicalDeviceMultiDrawFeaturesEXT:
> > > -------------------------------------
> > > multiDraw = true
> > >
> > > VkPhysicalDeviceMultisampledRenderToSingleSampledFeaturesEXT:
> > > -------------------------------------------------------------
> > > multisampledRenderToSingleSampled = true
> > >
> > > VkPhysicalDeviceMutableDescriptorTypeFeaturesEXT:
> > > -------------------------------------------------
> > > mutableDescriptorType = true
> > >
> > > VkPhysicalDeviceNestedCommandBufferFeaturesEXT:
> > > -----------------------------------------------
> > > nestedCommandBuffer = true
> > > nestedCommandBufferRendering = true
> > > nestedCommandBufferSimultaneousUse = true
> > >
> > > VkPhysicalDeviceNonSeamlessCubeMapFeaturesEXT:
> > > ----------------------------------------------
> > > nonSeamlessCubeMap = true
> > >
> > > VkPhysicalDevicePageableDeviceLocalMemoryFeaturesEXT:
> > > -----------------------------------------------------
> > > pageableDeviceLocalMemory = true
> > >
> > > VkPhysicalDevicePrimitiveTopologyListRestartFeaturesEXT:
> > > --------------------------------------------------------
> > > primitiveTopologyListRestart = true
> > > primitiveTopologyPatchListRestart = true
> > >
> > > VkPhysicalDevicePrimitivesGeneratedQueryFeaturesEXT:
> > > ----------------------------------------------------
> > > primitivesGeneratedQuery = true
> > > primitivesGeneratedQueryWithRasterizerDiscard = true
> > > primitivesGeneratedQueryWithNonZeroStreams = true
> > >
> > > VkPhysicalDeviceProvokingVertexFeaturesEXT:
> > > -------------------------------------------
> > > provokingVertexLast = true
> > > transformFeedbackPreservesProvokingVertex = true
> > >
> > > VkPhysicalDeviceRasterizationOrderAttachmentAccessFeaturesEXT:
> > > --------------------------------------------------------------
> > > rasterizationOrderColorAttachmentAccess = true
> > > rasterizationOrderDepthAttachmentAccess = true
> > > rasterizationOrderStencilAttachmentAccess = true
> > >
> > > VkPhysicalDeviceRobustness2FeaturesEXT:
> > > ---------------------------------------
> > > robustBufferAccess2 = true
> > > robustImageAccess2 = true
> > > nullDescriptor = true
> > >
> > > VkPhysicalDeviceShaderAtomicFloat2FeaturesEXT:
> > > ----------------------------------------------
> > > shaderBufferFloat16Atomics = false
> > > shaderBufferFloat16AtomicAdd = false
> > > shaderBufferFloat16AtomicMinMax = false
> > > shaderBufferFloat32AtomicMinMax = true
> > > shaderBufferFloat64AtomicMinMax = false
> > > shaderSharedFloat16Atomics = false
> > > shaderSharedFloat16AtomicAdd = false
> > > shaderSharedFloat16AtomicMinMax = false
> > > shaderSharedFloat32AtomicMinMax = true
> > > shaderSharedFloat64AtomicMinMax = false
> > > shaderImageFloat32AtomicMinMax = true
> > > sparseImageFloat32AtomicMinMax = false
> > >
> > > VkPhysicalDeviceShaderAtomicFloatFeaturesEXT:
> > > ---------------------------------------------
> > > shaderBufferFloat32Atomics = true
> > > shaderBufferFloat32AtomicAdd = true
> > > shaderBufferFloat64Atomics = false
> > > shaderBufferFloat64AtomicAdd = false
> > > shaderSharedFloat32Atomics = true
> > > shaderSharedFloat32AtomicAdd = true
> > > shaderSharedFloat64Atomics = false
> > > shaderSharedFloat64AtomicAdd = false
> > > shaderImageFloat32Atomics = true
> > > shaderImageFloat32AtomicAdd = true
> > > sparseImageFloat32Atomics = false
> > > sparseImageFloat32AtomicAdd = false
> > >
> > > VkPhysicalDeviceShaderClockFeaturesKHR:
> > > ---------------------------------------
> > > shaderSubgroupClock = true
> > > shaderDeviceClock = true
> > >
> > > VkPhysicalDeviceShaderObjectFeaturesEXT:
> > > ----------------------------------------
> > > shaderObject = true
> > >
> > > VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT:
> > > ------------------------------------------------
> > > texelBufferAlignment = true
> > >
> > > VkPhysicalDeviceTransformFeedbackFeaturesEXT:
> > > ---------------------------------------------
> > > transformFeedback = true
> > > geometryStreams = true
> > >
> > > VkPhysicalDeviceVertexAttributeDivisorFeaturesKHR:
> > > --------------------------------------------------
> > > vertexAttributeInstanceRateDivisor = true
> > > vertexAttributeInstanceRateZeroDivisor = true
> > >
> > > VkPhysicalDeviceVertexInputDynamicStateFeaturesEXT:
> > > ---------------------------------------------------
> > > vertexInputDynamicState = true
> > >
> > > VkPhysicalDeviceVulkan11Features:
> > > ---------------------------------
> > > storageBuffer16BitAccess = true
> > > uniformAndStorageBuffer16BitAccess = true
> > > storagePushConstant16 = true
> > > storageInputOutput16 = false
> > > multiview = true
> > > multiviewGeometryShader = true
> > > multiviewTessellationShader = true
> > > variablePointersStorageBuffer = true
> > > variablePointers = true
> > > protectedMemory = false
> > > samplerYcbcrConversion = true
> > > shaderDrawParameters = true
> > >
> > > VkPhysicalDeviceVulkan12Features:
> > > ---------------------------------
> > > samplerMirrorClampToEdge = true
> > > drawIndirectCount = true
> > > storageBuffer8BitAccess = true
> > > uniformAndStorageBuffer8BitAccess = true
> > > storagePushConstant8 = true
> > > shaderBufferInt64Atomics = true
> > > shaderSharedInt64Atomics = true
> > > shaderFloat16 = true
> > > shaderInt8 = true
> > > descriptorIndexing = true
> > > shaderInputAttachmentArrayDynamicIndexing = true
> > > shaderUniformTexelBufferArrayDynamicIndexing = true
> > > shaderStorageTexelBufferArrayDynamicIndexing = true
> > > shaderUniformBufferArrayNonUniformIndexing = true
> > > shaderSampledImageArrayNonUniformIndexing = true
> > > shaderStorageBufferArrayNonUniformIndexing = true
> > > shaderStorageImageArrayNonUniformIndexing = true
> > > shaderInputAttachmentArrayNonUniformIndexing = true
> > > shaderUniformTexelBufferArrayNonUniformIndexing = true
> > > shaderStorageTexelBufferArrayNonUniformIndexing = true
> > > descriptorBindingUniformBufferUpdateAfterBind = true
> > > descriptorBindingSampledImageUpdateAfterBind = true
> > > descriptorBindingStorageImageUpdateAfterBind = true
> > > descriptorBindingStorageBufferUpdateAfterBind = true
> > > descriptorBindingUniformTexelBufferUpdateAfterBind = true
> > > descriptorBindingStorageTexelBufferUpdateAfterBind = true
> > > descriptorBindingUpdateUnusedWhilePending = true
> > > descriptorBindingPartiallyBound = true
> > > descriptorBindingVariableDescriptorCount = true
> > > runtimeDescriptorArray = true
> > > samplerFilterMinmax = true
> > > scalarBlockLayout = true
> > > imagelessFramebuffer = true
> > > uniformBufferStandardLayout = true
> > > shaderSubgroupExtendedTypes = true
> > > separateDepthStencilLayouts = true
> > > hostQueryReset = true
> > > timelineSemaphore = true
> > > bufferDeviceAddress = true
> > > bufferDeviceAddressCaptureReplay = false
> > > bufferDeviceAddressMultiDevice = false
> > > vulkanMemoryModel = true
> > > vulkanMemoryModelDeviceScope = true
> > > vulkanMemoryModelAvailabilityVisibilityChains = true
> > > shaderOutputViewportIndex = true
> > > shaderOutputLayer = true
> > > subgroupBroadcastDynamicId = true
> > >
> > > VkPhysicalDeviceVulkan13Features:
> > > ---------------------------------
> > > robustImageAccess = true
> > > inlineUniformBlock = true
> > > descriptorBindingInlineUniformBlockUpdateAfterBind = true
> > > pipelineCreationCacheControl = true
> > > privateData = true
> > > shaderDemoteToHelperInvocation = true
> > > shaderTerminateInvocation = true
> > > subgroupSizeControl = true
> > > computeFullSubgroups = true
> > > synchronization2 = true
> > > textureCompressionASTC_HDR = false
> > > shaderZeroInitializeWorkgroupMemory = true
> > > dynamicRendering = true
> > > shaderIntegerDotProduct = true
> > > maintenance4 = true
> > >
> > > VkPhysicalDeviceYcbcr2Plane444FormatsFeaturesEXT:
> > > -------------------------------------------------
> > > ycbcr2plane444Formats = true
> > >
> > > VkPhysicalDeviceYcbcrImageArraysFeaturesEXT:
> > > --------------------------------------------
> > > ycbcrImageArrays = true
> > >
> > >
> > > --
> > > 2.45.1.288.g0e0cd299f1-goog
> > >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 4/6] drm/imagination: Add compatible string entry for Series6XT
2024-05-31 11:18 ` Frank Binns
@ 2024-06-03 3:29 ` Chen-Yu Tsai
2024-06-03 7:45 ` Steven Price
0 siblings, 1 reply; 38+ messages in thread
From: Chen-Yu Tsai @ 2024-06-03 3:29 UTC (permalink / raw)
To: Frank Binns
Cc: matthias.bgg@gmail.com, tzimmermann@suse.de, Matt Coster,
sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
maarten.lankhorst@linux.intel.com, mripard@kernel.org,
conor+dt@kernel.org, angelogioacchino.delregno@collabora.com,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, airlied@gmail.com,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, daniel@ffwll.ch,
linux-clk@vger.kernel.org, Boris Brezillon, Steven Price
On Fri, May 31, 2024 at 7:18 PM Frank Binns <Frank.Binns@imgtec.com> wrote:
>
> On Thu, 2024-05-30 at 16:35 +0800, Chen-Yu Tsai wrote:
> > The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is part
> > of the Series6XT, another variation of the Rogue family of GPUs.
> >
> > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> > ---
> > drivers/gpu/drm/imagination/pvr_drv.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/imagination/pvr_drv.c b/drivers/gpu/drm/imagination/pvr_drv.c
> > index 5c3b2d58d766..3d1a933c8303 100644
> > --- a/drivers/gpu/drm/imagination/pvr_drv.c
> > +++ b/drivers/gpu/drm/imagination/pvr_drv.c
> > @@ -1475,6 +1475,7 @@ pvr_remove(struct platform_device *plat_dev)
> >
> > static const struct of_device_id dt_match[] = {
> > { .compatible = "img,img-axe", .data = NULL },
> > + { .compatible = "img,powervr-6xt", .data = NULL },
>
> I assume that by adding this to the list of supported devices we're essentially
> freezing the existing uapi. This concerns me, as we've not yet started running
> Vulkan conformance on any Series6XT GPUs and there's a chance we may need to
> make some tweaks.
>
> I'm not really sure what the accepted approach is to hardware enablement /
> experimental support. I'm not sure if it's sufficient to hide support behind a
> Kconfig option and/or module parameter or whether we just have to hold this
> patch back for the time being.
I guess this is more of a question for the DRM maintainers.
Added a couple Panfrost/Panthor folks for ideas.
ChenYu
> Thanks
> Frank
>
> > {}
> > };
> > MODULE_DEVICE_TABLE(of, dt_match);
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 4/6] drm/imagination: Add compatible string entry for Series6XT
2024-06-03 3:29 ` Chen-Yu Tsai
@ 2024-06-03 7:45 ` Steven Price
0 siblings, 0 replies; 38+ messages in thread
From: Steven Price @ 2024-06-03 7:45 UTC (permalink / raw)
To: Chen-Yu Tsai, Frank Binns
Cc: matthias.bgg@gmail.com, tzimmermann@suse.de, Matt Coster,
sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
maarten.lankhorst@linux.intel.com, mripard@kernel.org,
conor+dt@kernel.org, angelogioacchino.delregno@collabora.com,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, airlied@gmail.com,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, daniel@ffwll.ch,
linux-clk@vger.kernel.org, Boris Brezillon
On 03/06/2024 04:29, Chen-Yu Tsai wrote:
> On Fri, May 31, 2024 at 7:18 PM Frank Binns <Frank.Binns@imgtec.com> wrote:
>>
>> On Thu, 2024-05-30 at 16:35 +0800, Chen-Yu Tsai wrote:
>>> The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is part
>>> of the Series6XT, another variation of the Rogue family of GPUs.
>>>
>>> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
>>> ---
>>> drivers/gpu/drm/imagination/pvr_drv.c | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git a/drivers/gpu/drm/imagination/pvr_drv.c b/drivers/gpu/drm/imagination/pvr_drv.c
>>> index 5c3b2d58d766..3d1a933c8303 100644
>>> --- a/drivers/gpu/drm/imagination/pvr_drv.c
>>> +++ b/drivers/gpu/drm/imagination/pvr_drv.c
>>> @@ -1475,6 +1475,7 @@ pvr_remove(struct platform_device *plat_dev)
>>>
>>> static const struct of_device_id dt_match[] = {
>>> { .compatible = "img,img-axe", .data = NULL },
>>> + { .compatible = "img,powervr-6xt", .data = NULL },
>>
>> I assume that by adding this to the list of supported devices we're essentially
>> freezing the existing uapi. This concerns me, as we've not yet started running
>> Vulkan conformance on any Series6XT GPUs and there's a chance we may need to
>> make some tweaks.
>>
>> I'm not really sure what the accepted approach is to hardware enablement /
>> experimental support. I'm not sure if it's sufficient to hide support behind a
>> Kconfig option and/or module parameter or whether we just have to hold this
>> patch back for the time being.
>
> I guess this is more of a question for the DRM maintainers.
> Added a couple Panfrost/Panthor folks for ideas.
I'm not sure quite what scale of "tweaks" you are expecting. Obviously
adding new uAPI is possible at any time - the only requirement is "don't
break user space" - i.e. don't remove old uAPI. Although obviously you
want to be careful about adding it because that means supporting it
forever more.
Panfrost has had an "unstable_ioctls" module parameter that we've hidden
performance counters behind. (Performance counters are hard from a uAPI
perspective - Panthor has similar issues).
We've also added support for GPUs in a deliberately "crippled" manner
(e.g. only one core group - see panfrost_get_core_mask()). I think we're
mostly just hoping those 'awkward' GPUs are not interesting enough and
we'll never implement full support for them - but if we did I expect
we'd implement support by providing a new uAPI for enabling the second
core group so old user space can continue working with just the single
core group.
Of course if the support for this platform is actually 'broken' (the
talk of GPU resets makes me think so - on Mali requiring a reset is a
"should never happen" situation, but we do have errata...) then it's
probably best holding off merging this until you've got something which
is minimally functional and then add support as necessary. For Vulkan
you can always have user space require a particular DRM kernel version
if you discover extra uAPI is needed.
Steve
_______________________________________________
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 3/6] dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU
2024-05-31 13:37 ` Frank Binns
2024-05-31 14:24 ` Adam Ford
@ 2024-06-04 4:18 ` Chen-Yu Tsai
2024-06-13 9:10 ` Chen-Yu Tsai
1 sibling, 1 reply; 38+ messages in thread
From: Chen-Yu Tsai @ 2024-06-04 4:18 UTC (permalink / raw)
To: Frank Binns
Cc: matthias.bgg@gmail.com, tzimmermann@suse.de, Matt Coster,
sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
aford173@gmail.com, maarten.lankhorst@linux.intel.com,
mripard@kernel.org, conor+dt@kernel.org,
angelogioacchino.delregno@collabora.com,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, airlied@gmail.com,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, daniel@ffwll.ch,
linux-clk@vger.kernel.org
On Fri, May 31, 2024 at 9:37 PM Frank Binns <Frank.Binns@imgtec.com> wrote:
>
> Hi ChenYu,
>
> On Thu, 2024-05-30 at 16:35 +0800, Chen-Yu Tsai wrote:
> > The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is one
> > of the Series6XT GPUs, another sub-family of the Rogue family.
>
> I've added Adam Ford who sent out some DT related patches [1] for the Renesas
> variant of GX6250 and the GX6650 (another Series6XT GPU).
>
> >
> > This was part of the very first few versions of the PowerVR submission,
> > but was later dropped. The compatible string has been updated to follow
> > the new naming scheme adopted for the AXE series.
> >
> > In a previous iteration of the PowerVR binding submission [1], the
> > number of clocks required for the 6XT family was mentioned to be
> > always 3. This is also reflected here.
> >
> > [1] https://lore.kernel.org/dri-devel/6eeccb26e09aad67fb30ffcd523c793a43c79c2a.camel@imgtec.com/
> >
> > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> > ---
> > .../bindings/gpu/img,powervr-rogue.yaml | 24 +++++++++++++++----
> > 1 file changed, 20 insertions(+), 4 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> > index 256e252f8087..48aa205b66b4 100644
> > --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> > +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> > @@ -12,10 +12,17 @@ maintainers:
> >
> > properties:
> > compatible:
> > - items:
> > - - enum:
> > - - ti,am62-gpu
> > - - const: img,img-axe # IMG AXE GPU model/revision is fully discoverable
> > + oneOf:
> > + - items:
> > + - enum:
> > + - mediatek,mt8173-gpu
> > + # PowerVR 6XT GPU model/revision is fully discoverable
> > + - const: img,powervr-6xt
> > + - items:
> > + - enum:
> > + - ti,am62-gpu
> > + # IMG AXE GPU model/revision is fully discoverable
> > + - const: img,img-axe
>
> The Series6XT GPU models have differing numbers of power domains (either 2, 4 or
> 5). Whereas, the AXE GPUs have a single power domain, so I assume there should
> be a related change here.
>
> The GX6250 has two power domains (lets call them A and B). There's a constraint
> that if domain B is powered then domain A must also be powered.
>
> In patch 6 [2] it's setting the power domain to MT8173_POWER_DOMAIN_MFG, which I
> believe corresponds to power domain B. I assume this works because the MTK power
> controller driver is encoding the constraint above, meaning that when we disable
> or enable MT8173_POWER_DOMAIN_MFG it's also disabling/enabling MT8173_POWER_DOMA
> IN_MFG_2D (domain A).
It could also be that the power domains are split in the glue layer and there
is some sequencing handled there. I'll reach out to MediaTek to see if they
can dig up some design specifics.
I assume you would like to see the separate power domains properly modeled
in the device tree?
Thanks
ChenYu
> Thanks
> Frank
>
> [1] https://lists.freedesktop.org/archives/dri-devel/2024-February/443548.html
> [2] https://lists.freedesktop.org/archives/dri-devel/2024-May/455833.html
>
> >
> > reg:
> > maxItems: 1
> > @@ -56,6 +63,15 @@ allOf:
> > properties:
> > clocks:
> > maxItems: 1
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: img,powervr-6xt
> > + then:
> > + properties:
> > + clocks:
> > + minItems: 3
> >
> > examples:
> > - |
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 3/6] dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU
2024-05-31 14:24 ` Adam Ford
@ 2024-06-04 4:21 ` Chen-Yu Tsai
0 siblings, 0 replies; 38+ messages in thread
From: Chen-Yu Tsai @ 2024-06-04 4:21 UTC (permalink / raw)
To: Adam Ford
Cc: Frank Binns, matthias.bgg@gmail.com, tzimmermann@suse.de,
Matt Coster, sboyd@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, maarten.lankhorst@linux.intel.com,
mripard@kernel.org, conor+dt@kernel.org,
angelogioacchino.delregno@collabora.com,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, airlied@gmail.com,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, daniel@ffwll.ch,
linux-clk@vger.kernel.org
On Fri, May 31, 2024 at 10:25 PM Adam Ford <aford173@gmail.com> wrote:
>
> On Fri, May 31, 2024 at 8:37 AM Frank Binns <Frank.Binns@imgtec.com> wrote:
> >
> > Hi ChenYu,
> >
> > On Thu, 2024-05-30 at 16:35 +0800, Chen-Yu Tsai wrote:
> > > The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is one
> > > of the Series6XT GPUs, another sub-family of the Rogue family.
> >
> > I've added Adam Ford who sent out some DT related patches [1] for the Renesas
> > variant of GX6250 and the GX6650 (another Series6XT GPU).
> >
>
> Thanks for including me.
>
> > >
> > > This was part of the very first few versions of the PowerVR submission,
> > > but was later dropped. The compatible string has been updated to follow
> > > the new naming scheme adopted for the AXE series.
> > >
> > > In a previous iteration of the PowerVR binding submission [1], the
> > > number of clocks required for the 6XT family was mentioned to be
> > > always 3. This is also reflected here.
> > >
> > > [1] https://lore.kernel.org/dri-devel/6eeccb26e09aad67fb30ffcd523c793a43c79c2a.camel@imgtec.com/
> > >
> > > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> > > ---
> > > .../bindings/gpu/img,powervr-rogue.yaml | 24 +++++++++++++++----
> > > 1 file changed, 20 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> > > index 256e252f8087..48aa205b66b4 100644
> > > --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> > > +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> > > @@ -12,10 +12,17 @@ maintainers:
> > >
> > > properties:
> > > compatible:
> > > - items:
> > > - - enum:
> > > - - ti,am62-gpu
> > > - - const: img,img-axe # IMG AXE GPU model/revision is fully discoverable
> > > + oneOf:
> > > + - items:
> > > + - enum:
> > > + - mediatek,mt8173-gpu
> > > + # PowerVR 6XT GPU model/revision is fully discoverable
> > > + - const: img,powervr-6xt
> > > + - items:
> > > + - enum:
> > > + - ti,am62-gpu
> > > + # IMG AXE GPU model/revision is fully discoverable
> > > + - const: img,img-axe
> >
> > The Series6XT GPU models have differing numbers of power domains (either 2, 4 or
> > 5). Whereas, the AXE GPUs have a single power domain, so I assume there should
> > be a related change here.
> >
> > The GX6250 has two power domains (lets call them A and B). There's a constraint
> > that if domain B is powered then domain A must also be powered.
> >
> > In patch 6 [2] it's setting the power domain to MT8173_POWER_DOMAIN_MFG, which I
> > believe corresponds to power domain B. I assume this works because the MTK power
> > controller driver is encoding the constraint above, meaning that when we disable
> > or enable MT8173_POWER_DOMAIN_MFG it's also disabling/enabling MT8173_POWER_DOMA
> > IN_MFG_2D (domain A).
> >
>
> In the cover letter of this series, it was noted that the GPU
> enumerates, but it doesn' fully function yet. This is also the case
> for both of the Renesas variants I have been testing, and I was nicely
> asked to postpone my series until the driver was closer to being
> ready.
Yeah. Frank laid out the current state of GX6250 support and future plans
in his reply to the clk driver patch.
> Even if the driver isn't ready yet, it would be nice to move the
> bindings forward.
Agreed. It would be nice to have an agreed upon set of bindings. We
can then move our downstream stuff comply with it.
Thanks
ChenYu
> adam
>
> > Thanks
> > Frank
> >
> > [1] https://lists.freedesktop.org/archives/dri-devel/2024-February/443548.html
> > [2] https://lists.freedesktop.org/archives/dri-devel/2024-May/455833.html
> >
> > >
> > > reg:
> > > maxItems: 1
> > > @@ -56,6 +63,15 @@ allOf:
> > > properties:
> > > clocks:
> > > maxItems: 1
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + const: img,powervr-6xt
> > > + then:
> > > + properties:
> > > + clocks:
> > > + minItems: 3
> > >
> > > examples:
> > > - |
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 5/6] arm64: dts: mediatek: mt8173: Fix MFG_ASYNC power domain clock
2024-05-30 10:03 ` AngeloGioacchino Del Regno
@ 2024-06-05 8:25 ` Chen-Yu Tsai
2024-06-05 11:25 ` AngeloGioacchino Del Regno
0 siblings, 1 reply; 38+ messages in thread
From: Chen-Yu Tsai @ 2024-06-05 8:25 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, David Airlie, Daniel Vetter,
dri-devel, linux-clk, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel
On Thu, May 30, 2024 at 6:03 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Il 30/05/24 10:35, Chen-Yu Tsai ha scritto:
> > The MFG_ASYNC domain, which is likely associated to the whole MFG block,
> > currently specifies clk26m as its domain clock. This is bogus, since the
> > clock is an external crystal with no controls. Also, the MFG block has
> > a independent CLK_TOP_AXI_MFG_IN_SEL clock, which according to the block
> > diagram, gates access to the hardware registers. Having this one as the
> > domain clock makes much more sense. This also fixes access to the MFGTOP
> > registers.
> >
> > Change the MFG_ASYNC domain clock to CLK_TOP_AXI_MFG_IN_SEL.
> >
> > Fixes: 8b6562644df9 ("arm64: dts: mediatek: Add mt8173 power domain controller")
> > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
>
> Just one question... what happens if there's no GPU support at all and this
> power domain gets powered off?
>
> I expect the answer to be "nothing", so I'm preventively giving you my
Well it's powered off by default. Just double checked, and without the final
patch:
# cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
domain status children
performance
/device runtime status
----------------------------------------------------------------------------------------------
mfg off-0
0
mfg_2d off-0
0
mfg
mfg_async off-0
0
mfg_2d
And with the last patch but with the powervr removed:
# cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
domain status children
performance
/device runtime status
----------------------------------------------------------------------------------------------
mfg_apm off-0
0
mfg off-0
0
mfg_apm
/devices/platform/soc/13fff000.clock-controller suspended
0
mfg_2d off-0
0
mfg
mfg_async off-0
0
mfg_2d
Things seem to work OK. I can SSH in, and the framebuffer console on the screen
works fine.
Note that accessing the regmap through debugfs doesn't do much good. regmap
doesn't handle runtime PM. And the syscon regmap isn't even tied to a
struct device. Dumping the regmap through debugfs while the power domain
is off gives all zeroes, likely due to bus isolation.
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Thanks!
ChenYu
> ....but if I'm wrong and the answer isn't exactly "nothing", then I still agree
> with this commit, but only after removing the Fixes tag.
>
> Cheers,
> Angelo
>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index 3458be7f7f61..136b28f80cc2 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -497,7 +497,7 @@ power-domain@MT8173_POWER_DOMAIN_USB {
> > };
> > mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
> > reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
> > - clocks = <&clk26m>;
> > + clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>;
> > clock-names = "mfg";
> > #address-cells = <1>;
> > #size-cells = <0>;
>
>
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver
2024-05-30 10:16 ` Chen-Yu Tsai
2024-05-30 12:48 ` AngeloGioacchino Del Regno
2024-05-31 11:17 ` Frank Binns
@ 2024-06-05 8:39 ` Chen-Yu Tsai
2024-06-05 11:26 ` AngeloGioacchino Del Regno
2 siblings, 1 reply; 38+ messages in thread
From: Chen-Yu Tsai @ 2024-06-05 8:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, David Airlie, Daniel Vetter,
dri-devel, linux-clk, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel
On Thu, May 30, 2024 at 6:16 PM Chen-Yu Tsai <wenst@chromium.org> wrote:
>
> On Thu, May 30, 2024 at 5:59 PM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
> >
> > Il 30/05/24 10:35, Chen-Yu Tsai ha scritto:
> > > The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP
> > > in the datasheet, that contains clock gates, some power sequence signal
> > > delays, and other unknown registers that get toggled when the GPU is
> > > powered on.
> > >
> > > The clock gates are exposed as clocks provided by a clock controller,
> > > while the power sequencing bits are exposed as one singular power domain.
> > >
> > > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> > > ---
> > > drivers/clk/mediatek/Kconfig | 9 +
> > > drivers/clk/mediatek/Makefile | 1 +
> > > drivers/clk/mediatek/clk-mt8173-mfgtop.c | 240 +++++++++++++++++++++++
> > > 3 files changed, 250 insertions(+)
> > > create mode 100644 drivers/clk/mediatek/clk-mt8173-mfgtop.c
> > >
> > > diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> > > index 70a005e7e1b1..9e279c739f1c 100644
> > > --- a/drivers/clk/mediatek/Kconfig
> > > +++ b/drivers/clk/mediatek/Kconfig
> > > @@ -500,6 +500,15 @@ config COMMON_CLK_MT8173_IMGSYS
> > > help
> > > This driver supports MediaTek MT8173 imgsys clocks.
> > >
> > > +config COMMON_CLK_MT8173_MFGTOP
> > > + tristate "Clock and power driver for MediaTek MT8173 mfgtop"
> > > + depends on COMMON_CLK_MT8173
> > > + default COMMON_CLK_MT8173
> > > + select PM_GENERIC_DOMAINS
> > > + select PM_GENERIC_DOMAINS_OF
> > > + help
> > > + This driver supports MediaTek MT8173 mfgtop clocks and power domain.
> > > +
> > > config COMMON_CLK_MT8173_MMSYS
> > > tristate "Clock driver for MediaTek MT8173 mmsys"
> > > depends on COMMON_CLK_MT8173
> > > diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> > > index eeccfa039896..fdd3a76e12a1 100644
> > > --- a/drivers/clk/mediatek/Makefile
> > > +++ b/drivers/clk/mediatek/Makefile
> > > @@ -77,6 +77,7 @@ obj-$(CONFIG_COMMON_CLK_MT8167_VDECSYS) += clk-mt8167-vdec.o
> > > obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173-apmixedsys.o clk-mt8173-infracfg.o \
> > > clk-mt8173-pericfg.o clk-mt8173-topckgen.o
> > > obj-$(CONFIG_COMMON_CLK_MT8173_IMGSYS) += clk-mt8173-img.o
> > > +obj-$(CONFIG_COMMON_CLK_MT8173_MFGTOP) += clk-mt8173-mfgtop.o
> > > obj-$(CONFIG_COMMON_CLK_MT8173_MMSYS) += clk-mt8173-mm.o
> > > obj-$(CONFIG_COMMON_CLK_MT8173_VDECSYS) += clk-mt8173-vdecsys.o
> > > obj-$(CONFIG_COMMON_CLK_MT8173_VENCSYS) += clk-mt8173-vencsys.o
> > > diff --git a/drivers/clk/mediatek/clk-mt8173-mfgtop.c b/drivers/clk/mediatek/clk-mt8173-mfgtop.c
> > > new file mode 100644
> > > index 000000000000..85fa7a7453ed
> > > --- /dev/null
> > > +++ b/drivers/clk/mediatek/clk-mt8173-mfgtop.c
> > > @@ -0,0 +1,240 @@
> > > +// SPDX-License-Identifier: GPL-2.0-only
> > > +/*
> > > + * Copyright (c) 2024 Google LLC
> > > + * Author: Chen-Yu Tsai <wenst@chromium.org>
> > > + *
> > > + * Based on driver in downstream ChromeOS v5.15 kernel.
> > > + *
> > > + * Copyright (c) 2014 MediaTek Inc.
> > > + * Author: Chiawen Lee <chiawen.lee@mediatek.com>
> > > + */
> > > +
> > > +#include <dt-bindings/clock/mt8173-clk.h>
> > > +
> > > +#include <linux/bitfield.h>
> > > +#include <linux/clk.h>
> > > +#include <linux/mfd/syscon.h>
> > > +#include <linux/module.h>
> > > +#include <linux/of.h>
> > > +#include <linux/platform_device.h>
> > > +#include <linux/pm_domain.h>
> > > +#include <linux/pm_runtime.h>
> > > +#include <linux/regmap.h>
> > > +
> > > +#include "clk-gate.h"
> > > +#include "clk-mtk.h"
> > > +
> > > +static const struct mtk_gate_regs mfg_cg_regs = {
> > > + .sta_ofs = 0x0000,
> > > + .clr_ofs = 0x0008,
> > > + .set_ofs = 0x0004,
> > > +};
> > > +
> > > +#define GATE_MFG(_id, _name, _parent, _shift, _flags) \
> > > + GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr, _flags)
> >
> > Extra tabulation: please fix
>
> One tab instead of two? OK.
>
> > > +
> > > +/* TODO: The block actually has dividers for the core and mem clocks. */
> > > +static const struct mtk_gate mfg_clks[] = {
> > > + GATE_MFG(CLK_MFG_AXI, "mfg_axi", "axi_mfg_in_sel", 0, CLK_SET_RATE_PARENT),
> > > + GATE_MFG(CLK_MFG_MEM, "mfg_mem", "mem_mfg_in_sel", 1, CLK_SET_RATE_PARENT),
> > > + GATE_MFG(CLK_MFG_G3D, "mfg_g3d", "mfg_sel", 2, CLK_SET_RATE_PARENT),
> > > + GATE_MFG(CLK_MFG_26M, "mfg_26m", "clk26m", 3, 0),
> > > +};
> > > +
> > > +static const struct mtk_clk_desc mfg_desc = {
> > > + .clks = mfg_clks,
> > > + .num_clks = ARRAY_SIZE(mfg_clks),
> > > +};
> > > +
> > > +struct mt8173_mfgtop_data {
> > > + struct clk_hw_onecell_data *clk_data;
> > > + struct regmap *regmap;
> > > + struct generic_pm_domain genpd;
> > > + struct of_phandle_args parent_pd, child_pd;
> > > + struct clk *clk_26m;
> > > +};
> > > +
> > > +static const struct of_device_id of_match_clk_mt8173_mfgtop[] = {
> > > + { .compatible = "mediatek,mt8173-mfgtop", .data = &mfg_desc },
> > > + { /* sentinel */ }
> > > +};
> > > +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_mfgtop);
> >
> > Please move of_match_clk_mt8173_mfgtop before clk_mt8173_mfgtop_drv for consistency
> > with all the other clock drivers.
>
> Ack.
>
> > > +
> > > +/* Delay count in clock cycles */
> > > +#define MFG_ACTIVE_POWER_CON0 0x24
> > > + #define RST_B_DELAY_CNT GENMASK(7, 0) /* pwr_rst_b de-assert delay during power-up */
> > > + #define CLK_EN_DELAY_CNT GENMASK(15, 8) /* CLK_DIS deassert delay during power-up */
> > > + #define CLK_DIS_DELAY_CNT GENMASK(23, 16) /* CLK_DIS assert delay during power-down */
> >
> > The reason why I had EVT_FORCE_ABORT and ACTIVE_PWRCTL_EN in my driver is to
> > document that we're keeping the event force abort disabled and, more importantly,
> > we are keeping the "active power control" feature disabled.
> >
> > Please, add those two - or at least the ACTIVE_PWRCTL_EN - to keep that documented,
> > or this information will be lost for sure.
> > If in the future the ACTIVE_PWRCTL feature will become usable, it's going to be
> > just a 30 seconds change, as the info is already there.
>
> OK.
>
> > > +
> > > +#define MFG_ACTIVE_POWER_CON1 0x28
> > > + #define PWR_ON_S_DELAY_CNT GENMASK(7, 0) /* pwr_on_s assert delay during power-up */
> > > + #define ISO_DELAY_CNT GENMASK(15, 8) /* ISO assert delay during power-down */
> > > + #define ISOOFF_DELAY_CNT GENMASK(23, 16) /* ISO de-assert delay during power-up */
> > > + #define RST__DELAY_CNT GENMASK(31, 24) /* pwr_rsb_b assert delay during power-down */
> > > +
> > > +static int clk_mt8173_mfgtop_power_on(struct generic_pm_domain *domain)
> > > +{
> > > + struct mt8173_mfgtop_data *data = container_of(domain, struct mt8173_mfgtop_data, genpd);
> > > +
> > > + /* drives internal power management */
> > > + clk_prepare_enable(data->clk_26m);
> > > +
> > > + /* Power on/off delays for various signals */
> > > + regmap_write(data->regmap, MFG_ACTIVE_POWER_CON0,
> > > + FIELD_PREP(RST_B_DELAY_CNT, 77) |
> > > + FIELD_PREP(CLK_EN_DELAY_CNT, 61) |
> > > + FIELD_PREP(CLK_DIS_DELAY_CNT, 60));
> >
> > I get that this is kinda odd to read, but still...
> >
> > FIELD_PREP(CLK_DIS_DELAY_CNT, 60) |
> > FIELD_PREP(ACTIVE_PWRCTL_EN, 0));
> >
> > ...please :-)
>
> Sure.
>
> > > + regmap_write(data->regmap, MFG_ACTIVE_POWER_CON1,
> > > + FIELD_PREP(PWR_ON_S_DELAY_CNT, 11) |
> > > + FIELD_PREP(ISO_DELAY_CNT, 68) |
> > > + FIELD_PREP(ISOOFF_DELAY_CNT, 69) |
> > > + FIELD_PREP(RST__DELAY_CNT, 77));
> > > +
> > > + /* Magic numbers related to core switch sequence and delays */
> > > + regmap_write(data->regmap, 0xe0, 0x7a710184);
> > > + regmap_write(data->regmap, 0xe4, 0x835f6856);
> > > + regmap_write(data->regmap, 0xe8, 0x002b0234);
> > > + regmap_write(data->regmap, 0xec, 0x80000000);
> > > + regmap_write(data->regmap, 0xa0, 0x08000000);
> >
> > Is there any way to retrieve information about what those registers are?
>
> I asked. They said the project was too long ago, and they could only
> figure out that it had something to do with core switch sequencing and
> delays between each core, which is what I put in the comment there.
>
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int clk_mt8173_mfgtop_power_off(struct generic_pm_domain *domain)
> > > +{
> > > + struct mt8173_mfgtop_data *data = container_of(domain, struct mt8173_mfgtop_data, genpd);
> > > +
> > > + /* Magic numbers related to core switch sequence and delays */
> > > + regmap_write(data->regmap, 0xec, 0);
> > > +
> > > + /* drives internal power management */
> > > + clk_disable_unprepare(data->clk_26m);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int clk_mt8173_mfgtop_probe(struct platform_device *pdev)
> > > +{
> > > + struct device *dev = &pdev->dev;
> > > + struct device_node *node = dev->of_node;
> > > + struct mt8173_mfgtop_data *data;
> > > + int ret;
> > > +
> > > + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> > > + if (!data)
> > > + return -ENOMEM;
> > > +
> > > + platform_set_drvdata(pdev, data);
> > > +
> > > + data->clk_data = mtk_devm_alloc_clk_data(dev, ARRAY_SIZE(mfg_clks));
> > > + if (!data->clk_data)
> > > + return -ENOMEM;
> > > +
> > > + /* MTK clock gates also uses regmap */
> > > + data->regmap = device_node_to_regmap(node);
> > > + if (IS_ERR(data->regmap))
> > > + return dev_err_probe(dev, PTR_ERR(data->regmap), "Failed to get regmap\n");
> > > +
> > > + data->child_pd.np = node;
> > > + data->child_pd.args_count = 0;
> > > + ret = of_parse_phandle_with_args(node, "power-domains", "#power-domain-cells", 0,
> > > + &data->parent_pd);
> > > + if (ret)
> > > + return dev_err_probe(dev, ret, "Failed to parse power domain\n");
> > > +
> > > + devm_pm_runtime_enable(dev);
> > > + /*
> > > + * Do a pm_runtime_resume_and_get() to workaround a possible
> > > + * deadlock between clk_register() and the genpd framework.
> > > + */
> > > + ret = pm_runtime_resume_and_get(dev);
> > > + if (ret) {
> > > + dev_err_probe(dev, ret, "Failed to runtime resume device\n");
> > > + goto put_of_node;
> > > + }
> > > +
> > > + ret = mtk_clk_register_gates(dev, node, mfg_clks, ARRAY_SIZE(mfg_clks),
> > > + data->clk_data);
> > > + if (ret) {
> > > + dev_err_probe(dev, ret, "Failed to register clock gates\n");
> > > + goto put_pm_runtime;
> > > + }
> > > +
> > > + data->clk_26m = clk_hw_get_clk(data->clk_data->hws[CLK_MFG_26M], "26m");
> > > + if (IS_ERR(data->clk_26m)) {
> > > + dev_err_probe(dev, PTR_ERR(data->clk_26m), "Failed to get 26 MHz clock\n");
> > > + goto unregister_clks;
> > > + }
> > > +
> > > + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data->clk_data);
> > > + if (ret) {
> > > + dev_err_probe(dev, ret, "Failed to add clk OF provider\n");
> > > + goto put_26m_clk;
> > > + }
> > > +
> > > + data->genpd.name = "mfg_apm";
> >
> > "mfg-apm" or "mfg-pwr" please!
>
> Ack.
On second thought, mfg-top seems like a better name, since it matches
the datasheet.
ChenYu
> > Everything else looks good.
> >
> > Thanks for taking care of that, I started this work way too much time ago and
> > realistically I wouldn't have been able to finish it due to time constraints.
> >
> > It's great to see that *finally* we can get some GPU upstream on this old SoC.
> > As its CPUs are really slow, LLVMPipe is quite unusable from a UX perspective
> > hence its only big issue was the lack of 3D HW acceleration.
>
> I think there's still more work on the GPU driver side. I was digging
> through the mailing list to find ways to get it running, and evidently
> it doesn't fully support zink yet.
>
> > This makes machines embedding this SoC usable, and that's simply awesome.
>
> I'll give the patches a week to simmer while I go work on some
> other stuff.
>
> ChenYu
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 5/6] arm64: dts: mediatek: mt8173: Fix MFG_ASYNC power domain clock
2024-06-05 8:25 ` Chen-Yu Tsai
@ 2024-06-05 11:25 ` AngeloGioacchino Del Regno
2024-06-06 3:28 ` Chen-Yu Tsai
0 siblings, 1 reply; 38+ messages in thread
From: AngeloGioacchino Del Regno @ 2024-06-05 11:25 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, David Airlie, Daniel Vetter,
dri-devel, linux-clk, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel
Il 05/06/24 10:25, Chen-Yu Tsai ha scritto:
> On Thu, May 30, 2024 at 6:03 PM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
>>
>> Il 30/05/24 10:35, Chen-Yu Tsai ha scritto:
>>> The MFG_ASYNC domain, which is likely associated to the whole MFG block,
>>> currently specifies clk26m as its domain clock. This is bogus, since the
>>> clock is an external crystal with no controls. Also, the MFG block has
>>> a independent CLK_TOP_AXI_MFG_IN_SEL clock, which according to the block
>>> diagram, gates access to the hardware registers. Having this one as the
>>> domain clock makes much more sense. This also fixes access to the MFGTOP
>>> registers.
>>>
>>> Change the MFG_ASYNC domain clock to CLK_TOP_AXI_MFG_IN_SEL.
>>>
>>> Fixes: 8b6562644df9 ("arm64: dts: mediatek: Add mt8173 power domain controller")
>>> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
>>
>> Just one question... what happens if there's no GPU support at all and this
>> power domain gets powered off?
>>
>> I expect the answer to be "nothing", so I'm preventively giving you my
>
> Well it's powered off by default. Just double checked, and without the final
> patch:
>
> # cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
> domain status children
> performance
> /device runtime status
> ----------------------------------------------------------------------------------------------
> mfg off-0
> 0
> mfg_2d off-0
> 0
> mfg
> mfg_async off-0
> 0
> mfg_2d
>
> And with the last patch but with the powervr removed:
>
> # cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
> domain status children
> performance
> /device runtime status
> ----------------------------------------------------------------------------------------------
> mfg_apm off-0
> 0
> mfg off-0
> 0
> mfg_apm
> /devices/platform/soc/13fff000.clock-controller suspended
> 0
> mfg_2d off-0
> 0
> mfg
> mfg_async off-0
> 0
> mfg_2d
>
> Things seem to work OK. I can SSH in, and the framebuffer console on the screen
> works fine.
>
>
> Note that accessing the regmap through debugfs doesn't do much good. regmap
> doesn't handle runtime PM. And the syscon regmap isn't even tied to a
> struct device. Dumping the regmap through debugfs while the power domain
> is off gives all zeroes, likely due to bus isolation.
>
The last part where you say "gives all zeroes" is actually the best outcome that
I could have ever expected.
So, well, many thanks for this very nice analysis and test.
>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
I confirm my green light. It's beautiful when this kind of patches come upstream
especially with your replies actually removing any kind of possible doubt.
>
> Thanks!
Thank *you* for caring about this old platform!
Cheers,
Angelo
>
> ChenYu
>
>> ....but if I'm wrong and the answer isn't exactly "nothing", then I still agree
>> with this commit, but only after removing the Fixes tag.
>>
>> Cheers,
>> Angelo
>>
>>> ---
>>> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>>> index 3458be7f7f61..136b28f80cc2 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>>> @@ -497,7 +497,7 @@ power-domain@MT8173_POWER_DOMAIN_USB {
>>> };
>>> mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
>>> reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
>>> - clocks = <&clk26m>;
>>> + clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>;
>>> clock-names = "mfg";
>>> #address-cells = <1>;
>>> #size-cells = <0>;
>>
>>
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver
2024-06-05 8:39 ` Chen-Yu Tsai
@ 2024-06-05 11:26 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 38+ messages in thread
From: AngeloGioacchino Del Regno @ 2024-06-05 11:26 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, David Airlie, Daniel Vetter,
dri-devel, linux-clk, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel
Il 05/06/24 10:39, Chen-Yu Tsai ha scritto:
> On Thu, May 30, 2024 at 6:16 PM Chen-Yu Tsai <wenst@chromium.org> wrote:
>>
>> On Thu, May 30, 2024 at 5:59 PM AngeloGioacchino Del Regno
>> <angelogioacchino.delregno@collabora.com> wrote:
>>>
>>> Il 30/05/24 10:35, Chen-Yu Tsai ha scritto:
>>>> The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP
>>>> in the datasheet, that contains clock gates, some power sequence signal
>>>> delays, and other unknown registers that get toggled when the GPU is
>>>> powered on.
>>>>
>>>> The clock gates are exposed as clocks provided by a clock controller,
>>>> while the power sequencing bits are exposed as one singular power domain.
>>>>
>>>> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
>>>> ---
>>>> drivers/clk/mediatek/Kconfig | 9 +
>>>> drivers/clk/mediatek/Makefile | 1 +
>>>> drivers/clk/mediatek/clk-mt8173-mfgtop.c | 240 +++++++++++++++++++++++
>>>> 3 files changed, 250 insertions(+)
>>>> create mode 100644 drivers/clk/mediatek/clk-mt8173-mfgtop.c
>>>>
>>>> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
>>>> index 70a005e7e1b1..9e279c739f1c 100644
>>>> --- a/drivers/clk/mediatek/Kconfig
>>>> +++ b/drivers/clk/mediatek/Kconfig
>>>> @@ -500,6 +500,15 @@ config COMMON_CLK_MT8173_IMGSYS
>>>> help
>>>> This driver supports MediaTek MT8173 imgsys clocks.
>>>>
>>>> +config COMMON_CLK_MT8173_MFGTOP
>>>> + tristate "Clock and power driver for MediaTek MT8173 mfgtop"
>>>> + depends on COMMON_CLK_MT8173
>>>> + default COMMON_CLK_MT8173
>>>> + select PM_GENERIC_DOMAINS
>>>> + select PM_GENERIC_DOMAINS_OF
>>>> + help
>>>> + This driver supports MediaTek MT8173 mfgtop clocks and power domain.
>>>> +
>>>> config COMMON_CLK_MT8173_MMSYS
>>>> tristate "Clock driver for MediaTek MT8173 mmsys"
>>>> depends on COMMON_CLK_MT8173
>>>> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
>>>> index eeccfa039896..fdd3a76e12a1 100644
>>>> --- a/drivers/clk/mediatek/Makefile
>>>> +++ b/drivers/clk/mediatek/Makefile
>>>> @@ -77,6 +77,7 @@ obj-$(CONFIG_COMMON_CLK_MT8167_VDECSYS) += clk-mt8167-vdec.o
>>>> obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173-apmixedsys.o clk-mt8173-infracfg.o \
>>>> clk-mt8173-pericfg.o clk-mt8173-topckgen.o
>>>> obj-$(CONFIG_COMMON_CLK_MT8173_IMGSYS) += clk-mt8173-img.o
>>>> +obj-$(CONFIG_COMMON_CLK_MT8173_MFGTOP) += clk-mt8173-mfgtop.o
>>>> obj-$(CONFIG_COMMON_CLK_MT8173_MMSYS) += clk-mt8173-mm.o
>>>> obj-$(CONFIG_COMMON_CLK_MT8173_VDECSYS) += clk-mt8173-vdecsys.o
>>>> obj-$(CONFIG_COMMON_CLK_MT8173_VENCSYS) += clk-mt8173-vencsys.o
>>>> diff --git a/drivers/clk/mediatek/clk-mt8173-mfgtop.c b/drivers/clk/mediatek/clk-mt8173-mfgtop.c
>>>> new file mode 100644
>>>> index 000000000000..85fa7a7453ed
>>>> --- /dev/null
>>>> +++ b/drivers/clk/mediatek/clk-mt8173-mfgtop.c
>>>> @@ -0,0 +1,240 @@
>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>> +/*
>>>> + * Copyright (c) 2024 Google LLC
>>>> + * Author: Chen-Yu Tsai <wenst@chromium.org>
>>>> + *
>>>> + * Based on driver in downstream ChromeOS v5.15 kernel.
>>>> + *
>>>> + * Copyright (c) 2014 MediaTek Inc.
>>>> + * Author: Chiawen Lee <chiawen.lee@mediatek.com>
>>>> + */
>>>> +
>>>> +#include <dt-bindings/clock/mt8173-clk.h>
>>>> +
>>>> +#include <linux/bitfield.h>
>>>> +#include <linux/clk.h>
>>>> +#include <linux/mfd/syscon.h>
>>>> +#include <linux/module.h>
>>>> +#include <linux/of.h>
>>>> +#include <linux/platform_device.h>
>>>> +#include <linux/pm_domain.h>
>>>> +#include <linux/pm_runtime.h>
>>>> +#include <linux/regmap.h>
>>>> +
>>>> +#include "clk-gate.h"
>>>> +#include "clk-mtk.h"
>>>> +
>>>> +static const struct mtk_gate_regs mfg_cg_regs = {
>>>> + .sta_ofs = 0x0000,
>>>> + .clr_ofs = 0x0008,
>>>> + .set_ofs = 0x0004,
>>>> +};
>>>> +
>>>> +#define GATE_MFG(_id, _name, _parent, _shift, _flags) \
>>>> + GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr, _flags)
>>>
>>> Extra tabulation: please fix
>>
>> One tab instead of two? OK.
>>
>>>> +
>>>> +/* TODO: The block actually has dividers for the core and mem clocks. */
>>>> +static const struct mtk_gate mfg_clks[] = {
>>>> + GATE_MFG(CLK_MFG_AXI, "mfg_axi", "axi_mfg_in_sel", 0, CLK_SET_RATE_PARENT),
>>>> + GATE_MFG(CLK_MFG_MEM, "mfg_mem", "mem_mfg_in_sel", 1, CLK_SET_RATE_PARENT),
>>>> + GATE_MFG(CLK_MFG_G3D, "mfg_g3d", "mfg_sel", 2, CLK_SET_RATE_PARENT),
>>>> + GATE_MFG(CLK_MFG_26M, "mfg_26m", "clk26m", 3, 0),
>>>> +};
>>>> +
>>>> +static const struct mtk_clk_desc mfg_desc = {
>>>> + .clks = mfg_clks,
>>>> + .num_clks = ARRAY_SIZE(mfg_clks),
>>>> +};
>>>> +
>>>> +struct mt8173_mfgtop_data {
>>>> + struct clk_hw_onecell_data *clk_data;
>>>> + struct regmap *regmap;
>>>> + struct generic_pm_domain genpd;
>>>> + struct of_phandle_args parent_pd, child_pd;
>>>> + struct clk *clk_26m;
>>>> +};
>>>> +
>>>> +static const struct of_device_id of_match_clk_mt8173_mfgtop[] = {
>>>> + { .compatible = "mediatek,mt8173-mfgtop", .data = &mfg_desc },
>>>> + { /* sentinel */ }
>>>> +};
>>>> +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_mfgtop);
>>>
>>> Please move of_match_clk_mt8173_mfgtop before clk_mt8173_mfgtop_drv for consistency
>>> with all the other clock drivers.
>>
>> Ack.
>>
>>>> +
>>>> +/* Delay count in clock cycles */
>>>> +#define MFG_ACTIVE_POWER_CON0 0x24
>>>> + #define RST_B_DELAY_CNT GENMASK(7, 0) /* pwr_rst_b de-assert delay during power-up */
>>>> + #define CLK_EN_DELAY_CNT GENMASK(15, 8) /* CLK_DIS deassert delay during power-up */
>>>> + #define CLK_DIS_DELAY_CNT GENMASK(23, 16) /* CLK_DIS assert delay during power-down */
>>>
>>> The reason why I had EVT_FORCE_ABORT and ACTIVE_PWRCTL_EN in my driver is to
>>> document that we're keeping the event force abort disabled and, more importantly,
>>> we are keeping the "active power control" feature disabled.
>>>
>>> Please, add those two - or at least the ACTIVE_PWRCTL_EN - to keep that documented,
>>> or this information will be lost for sure.
>>> If in the future the ACTIVE_PWRCTL feature will become usable, it's going to be
>>> just a 30 seconds change, as the info is already there.
>>
>> OK.
>>
>>>> +
>>>> +#define MFG_ACTIVE_POWER_CON1 0x28
>>>> + #define PWR_ON_S_DELAY_CNT GENMASK(7, 0) /* pwr_on_s assert delay during power-up */
>>>> + #define ISO_DELAY_CNT GENMASK(15, 8) /* ISO assert delay during power-down */
>>>> + #define ISOOFF_DELAY_CNT GENMASK(23, 16) /* ISO de-assert delay during power-up */
>>>> + #define RST__DELAY_CNT GENMASK(31, 24) /* pwr_rsb_b assert delay during power-down */
>>>> +
>>>> +static int clk_mt8173_mfgtop_power_on(struct generic_pm_domain *domain)
>>>> +{
>>>> + struct mt8173_mfgtop_data *data = container_of(domain, struct mt8173_mfgtop_data, genpd);
>>>> +
>>>> + /* drives internal power management */
>>>> + clk_prepare_enable(data->clk_26m);
>>>> +
>>>> + /* Power on/off delays for various signals */
>>>> + regmap_write(data->regmap, MFG_ACTIVE_POWER_CON0,
>>>> + FIELD_PREP(RST_B_DELAY_CNT, 77) |
>>>> + FIELD_PREP(CLK_EN_DELAY_CNT, 61) |
>>>> + FIELD_PREP(CLK_DIS_DELAY_CNT, 60));
>>>
>>> I get that this is kinda odd to read, but still...
>>>
>>> FIELD_PREP(CLK_DIS_DELAY_CNT, 60) |
>>> FIELD_PREP(ACTIVE_PWRCTL_EN, 0));
>>>
>>> ...please :-)
>>
>> Sure.
>>
>>>> + regmap_write(data->regmap, MFG_ACTIVE_POWER_CON1,
>>>> + FIELD_PREP(PWR_ON_S_DELAY_CNT, 11) |
>>>> + FIELD_PREP(ISO_DELAY_CNT, 68) |
>>>> + FIELD_PREP(ISOOFF_DELAY_CNT, 69) |
>>>> + FIELD_PREP(RST__DELAY_CNT, 77));
>>>> +
>>>> + /* Magic numbers related to core switch sequence and delays */
>>>> + regmap_write(data->regmap, 0xe0, 0x7a710184);
>>>> + regmap_write(data->regmap, 0xe4, 0x835f6856);
>>>> + regmap_write(data->regmap, 0xe8, 0x002b0234);
>>>> + regmap_write(data->regmap, 0xec, 0x80000000);
>>>> + regmap_write(data->regmap, 0xa0, 0x08000000);
>>>
>>> Is there any way to retrieve information about what those registers are?
>>
>> I asked. They said the project was too long ago, and they could only
>> figure out that it had something to do with core switch sequencing and
>> delays between each core, which is what I put in the comment there.
>>
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int clk_mt8173_mfgtop_power_off(struct generic_pm_domain *domain)
>>>> +{
>>>> + struct mt8173_mfgtop_data *data = container_of(domain, struct mt8173_mfgtop_data, genpd);
>>>> +
>>>> + /* Magic numbers related to core switch sequence and delays */
>>>> + regmap_write(data->regmap, 0xec, 0);
>>>> +
>>>> + /* drives internal power management */
>>>> + clk_disable_unprepare(data->clk_26m);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int clk_mt8173_mfgtop_probe(struct platform_device *pdev)
>>>> +{
>>>> + struct device *dev = &pdev->dev;
>>>> + struct device_node *node = dev->of_node;
>>>> + struct mt8173_mfgtop_data *data;
>>>> + int ret;
>>>> +
>>>> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
>>>> + if (!data)
>>>> + return -ENOMEM;
>>>> +
>>>> + platform_set_drvdata(pdev, data);
>>>> +
>>>> + data->clk_data = mtk_devm_alloc_clk_data(dev, ARRAY_SIZE(mfg_clks));
>>>> + if (!data->clk_data)
>>>> + return -ENOMEM;
>>>> +
>>>> + /* MTK clock gates also uses regmap */
>>>> + data->regmap = device_node_to_regmap(node);
>>>> + if (IS_ERR(data->regmap))
>>>> + return dev_err_probe(dev, PTR_ERR(data->regmap), "Failed to get regmap\n");
>>>> +
>>>> + data->child_pd.np = node;
>>>> + data->child_pd.args_count = 0;
>>>> + ret = of_parse_phandle_with_args(node, "power-domains", "#power-domain-cells", 0,
>>>> + &data->parent_pd);
>>>> + if (ret)
>>>> + return dev_err_probe(dev, ret, "Failed to parse power domain\n");
>>>> +
>>>> + devm_pm_runtime_enable(dev);
>>>> + /*
>>>> + * Do a pm_runtime_resume_and_get() to workaround a possible
>>>> + * deadlock between clk_register() and the genpd framework.
>>>> + */
>>>> + ret = pm_runtime_resume_and_get(dev);
>>>> + if (ret) {
>>>> + dev_err_probe(dev, ret, "Failed to runtime resume device\n");
>>>> + goto put_of_node;
>>>> + }
>>>> +
>>>> + ret = mtk_clk_register_gates(dev, node, mfg_clks, ARRAY_SIZE(mfg_clks),
>>>> + data->clk_data);
>>>> + if (ret) {
>>>> + dev_err_probe(dev, ret, "Failed to register clock gates\n");
>>>> + goto put_pm_runtime;
>>>> + }
>>>> +
>>>> + data->clk_26m = clk_hw_get_clk(data->clk_data->hws[CLK_MFG_26M], "26m");
>>>> + if (IS_ERR(data->clk_26m)) {
>>>> + dev_err_probe(dev, PTR_ERR(data->clk_26m), "Failed to get 26 MHz clock\n");
>>>> + goto unregister_clks;
>>>> + }
>>>> +
>>>> + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data->clk_data);
>>>> + if (ret) {
>>>> + dev_err_probe(dev, ret, "Failed to add clk OF provider\n");
>>>> + goto put_26m_clk;
>>>> + }
>>>> +
>>>> + data->genpd.name = "mfg_apm";
>>>
>>> "mfg-apm" or "mfg-pwr" please!
>>
>> Ack.
>
> On second thought, mfg-top seems like a better name, since it matches
> the datasheet.
>
Yes, I definitely agree. Let's go for mfg-top.
Cheers!
> ChenYu
>
>>> Everything else looks good.
>>>
>>> Thanks for taking care of that, I started this work way too much time ago and
>>> realistically I wouldn't have been able to finish it due to time constraints.
>>>
>>> It's great to see that *finally* we can get some GPU upstream on this old SoC.
>>> As its CPUs are really slow, LLVMPipe is quite unusable from a UX perspective
>>> hence its only big issue was the lack of 3D HW acceleration.
>>
>> I think there's still more work on the GPU driver side. I was digging
>> through the mailing list to find ways to get it running, and evidently
>> it doesn't fully support zink yet.
>>
>>> This makes machines embedding this SoC usable, and that's simply awesome.
>>
>> I'll give the patches a week to simmer while I go work on some
>> other stuff.
>>
>> ChenYu
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 5/6] arm64: dts: mediatek: mt8173: Fix MFG_ASYNC power domain clock
2024-06-05 11:25 ` AngeloGioacchino Del Regno
@ 2024-06-06 3:28 ` Chen-Yu Tsai
0 siblings, 0 replies; 38+ messages in thread
From: Chen-Yu Tsai @ 2024-06-06 3:28 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, David Airlie, Daniel Vetter,
dri-devel, linux-clk, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel
On Wed, Jun 5, 2024 at 7:25 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Il 05/06/24 10:25, Chen-Yu Tsai ha scritto:
> > On Thu, May 30, 2024 at 6:03 PM AngeloGioacchino Del Regno
> > <angelogioacchino.delregno@collabora.com> wrote:
> >>
> >> Il 30/05/24 10:35, Chen-Yu Tsai ha scritto:
> >>> The MFG_ASYNC domain, which is likely associated to the whole MFG block,
> >>> currently specifies clk26m as its domain clock. This is bogus, since the
> >>> clock is an external crystal with no controls. Also, the MFG block has
> >>> a independent CLK_TOP_AXI_MFG_IN_SEL clock, which according to the block
> >>> diagram, gates access to the hardware registers. Having this one as the
> >>> domain clock makes much more sense. This also fixes access to the MFGTOP
> >>> registers.
> >>>
> >>> Change the MFG_ASYNC domain clock to CLK_TOP_AXI_MFG_IN_SEL.
> >>>
> >>> Fixes: 8b6562644df9 ("arm64: dts: mediatek: Add mt8173 power domain controller")
> >>> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> >>
> >> Just one question... what happens if there's no GPU support at all and this
> >> power domain gets powered off?
> >>
> >> I expect the answer to be "nothing", so I'm preventively giving you my
> >
> > Well it's powered off by default. Just double checked, and without the final
> > patch:
> >
> > # cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
> > domain status children
> > performance
> > /device runtime status
> > ----------------------------------------------------------------------------------------------
> > mfg off-0
> > 0
> > mfg_2d off-0
> > 0
> > mfg
> > mfg_async off-0
> > 0
> > mfg_2d
> >
> > And with the last patch but with the powervr removed:
> >
> > # cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
> > domain status children
> > performance
> > /device runtime status
> > ----------------------------------------------------------------------------------------------
> > mfg_apm off-0
> > 0
> > mfg off-0
> > 0
> > mfg_apm
> > /devices/platform/soc/13fff000.clock-controller suspended
> > 0
> > mfg_2d off-0
> > 0
> > mfg
> > mfg_async off-0
> > 0
> > mfg_2d
> >
> > Things seem to work OK. I can SSH in, and the framebuffer console on the screen
> > works fine.
> >
> >
> > Note that accessing the regmap through debugfs doesn't do much good. regmap
> > doesn't handle runtime PM. And the syscon regmap isn't even tied to a
> > struct device. Dumping the regmap through debugfs while the power domain
> > is off gives all zeroes, likely due to bus isolation.
> >
>
> The last part where you say "gives all zeroes" is actually the best outcome that
> I could have ever expected.
>
> So, well, many thanks for this very nice analysis and test.
>
> >> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>
> I confirm my green light. It's beautiful when this kind of patches come upstream
> especially with your replies actually removing any kind of possible doubt.
>
> >
> > Thanks!
>
> Thank *you* for caring about this old platform!
Can you pick up this patch first?
Frank mentioned that the GPU core takes two power domains. I asked
MediaTek for more information but I don't know how long that will take.
ChenYu
> Cheers,
> Angelo
>
> >
> > ChenYu
> >
> >> ....but if I'm wrong and the answer isn't exactly "nothing", then I still agree
> >> with this commit, but only after removing the Fixes tag.
> >>
> >> Cheers,
> >> Angelo
> >>
> >>> ---
> >>> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +-
> >>> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> >>> index 3458be7f7f61..136b28f80cc2 100644
> >>> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> >>> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> >>> @@ -497,7 +497,7 @@ power-domain@MT8173_POWER_DOMAIN_USB {
> >>> };
> >>> mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
> >>> reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
> >>> - clocks = <&clk26m>;
> >>> + clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>;
> >>> clock-names = "mfg";
> >>> #address-cells = <1>;
> >>> #size-cells = <0>;
> >>
> >>
>
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 3/6] dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU
2024-06-04 4:18 ` Chen-Yu Tsai
@ 2024-06-13 9:10 ` Chen-Yu Tsai
2024-06-13 13:23 ` Adam Ford
0 siblings, 1 reply; 38+ messages in thread
From: Chen-Yu Tsai @ 2024-06-13 9:10 UTC (permalink / raw)
To: Frank Binns, Adam Ford
Cc: matthias.bgg@gmail.com, tzimmermann@suse.de, Matt Coster,
sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
maarten.lankhorst@linux.intel.com, mripard@kernel.org,
conor+dt@kernel.org, angelogioacchino.delregno@collabora.com,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, airlied@gmail.com,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, daniel@ffwll.ch,
linux-clk@vger.kernel.org
On Tue, Jun 4, 2024 at 12:18 PM Chen-Yu Tsai <wenst@chromium.org> wrote:
>
> On Fri, May 31, 2024 at 9:37 PM Frank Binns <Frank.Binns@imgtec.com> wrote:
> >
> > Hi ChenYu,
> >
> > On Thu, 2024-05-30 at 16:35 +0800, Chen-Yu Tsai wrote:
> > > The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is one
> > > of the Series6XT GPUs, another sub-family of the Rogue family.
> >
> > I've added Adam Ford who sent out some DT related patches [1] for the Renesas
> > variant of GX6250 and the GX6650 (another Series6XT GPU).
> >
> > >
> > > This was part of the very first few versions of the PowerVR submission,
> > > but was later dropped. The compatible string has been updated to follow
> > > the new naming scheme adopted for the AXE series.
> > >
> > > In a previous iteration of the PowerVR binding submission [1], the
> > > number of clocks required for the 6XT family was mentioned to be
> > > always 3. This is also reflected here.
> > >
> > > [1] https://lore.kernel.org/dri-devel/6eeccb26e09aad67fb30ffcd523c793a43c79c2a.camel@imgtec.com/
> > >
> > > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> > > ---
> > > .../bindings/gpu/img,powervr-rogue.yaml | 24 +++++++++++++++----
> > > 1 file changed, 20 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> > > index 256e252f8087..48aa205b66b4 100644
> > > --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> > > +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> > > @@ -12,10 +12,17 @@ maintainers:
> > >
> > > properties:
> > > compatible:
> > > - items:
> > > - - enum:
> > > - - ti,am62-gpu
> > > - - const: img,img-axe # IMG AXE GPU model/revision is fully discoverable
> > > + oneOf:
> > > + - items:
> > > + - enum:
> > > + - mediatek,mt8173-gpu
> > > + # PowerVR 6XT GPU model/revision is fully discoverable
> > > + - const: img,powervr-6xt
> > > + - items:
> > > + - enum:
> > > + - ti,am62-gpu
> > > + # IMG AXE GPU model/revision is fully discoverable
> > > + - const: img,img-axe
> >
> > The Series6XT GPU models have differing numbers of power domains (either 2, 4 or
> > 5). Whereas, the AXE GPUs have a single power domain, so I assume there should
> > be a related change here.
> >
> > The GX6250 has two power domains (lets call them A and B). There's a constraint
> > that if domain B is powered then domain A must also be powered.
> >
> > In patch 6 [2] it's setting the power domain to MT8173_POWER_DOMAIN_MFG, which I
> > believe corresponds to power domain B. I assume this works because the MTK power
> > controller driver is encoding the constraint above, meaning that when we disable
> > or enable MT8173_POWER_DOMAIN_MFG it's also disabling/enabling MT8173_POWER_DOMA
> > IN_MFG_2D (domain A).
>
> It could also be that the power domains are split in the glue layer and there
> is some sequencing handled there. I'll reach out to MediaTek to see if they
> can dig up some design specifics.
Unfortunately they said they no longer have that information.
> I assume you would like to see the separate power domains properly modeled
> in the device tree?
So how should we go about this? Adam, do you have this information for
your platform?
Thanks
ChenYu
>
> Thanks
> ChenYu
>
> > Thanks
> > Frank
> >
> > [1] https://lists.freedesktop.org/archives/dri-devel/2024-February/443548.html
> > [2] https://lists.freedesktop.org/archives/dri-devel/2024-May/455833.html
> >
> > >
> > > reg:
> > > maxItems: 1
> > > @@ -56,6 +63,15 @@ allOf:
> > > properties:
> > > clocks:
> > > maxItems: 1
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + const: img,powervr-6xt
> > > + then:
> > > + properties:
> > > + clocks:
> > > + minItems: 3
> > >
> > > examples:
> > > - |
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 3/6] dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU
2024-06-13 9:10 ` Chen-Yu Tsai
@ 2024-06-13 13:23 ` Adam Ford
0 siblings, 0 replies; 38+ messages in thread
From: Adam Ford @ 2024-06-13 13:23 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Frank Binns, matthias.bgg@gmail.com, tzimmermann@suse.de,
Matt Coster, sboyd@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, maarten.lankhorst@linux.intel.com,
mripard@kernel.org, conor+dt@kernel.org,
angelogioacchino.delregno@collabora.com,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, airlied@gmail.com,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, daniel@ffwll.ch,
linux-clk@vger.kernel.org
On Thu, Jun 13, 2024 at 4:10 AM Chen-Yu Tsai <wenst@chromium.org> wrote:
>
> On Tue, Jun 4, 2024 at 12:18 PM Chen-Yu Tsai <wenst@chromium.org> wrote:
> >
> > On Fri, May 31, 2024 at 9:37 PM Frank Binns <Frank.Binns@imgtec.com> wrote:
> > >
> > > Hi ChenYu,
> > >
> > > On Thu, 2024-05-30 at 16:35 +0800, Chen-Yu Tsai wrote:
> > > > The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is one
> > > > of the Series6XT GPUs, another sub-family of the Rogue family.
> > >
> > > I've added Adam Ford who sent out some DT related patches [1] for the Renesas
> > > variant of GX6250 and the GX6650 (another Series6XT GPU).
> > >
> > > >
> > > > This was part of the very first few versions of the PowerVR submission,
> > > > but was later dropped. The compatible string has been updated to follow
> > > > the new naming scheme adopted for the AXE series.
> > > >
> > > > In a previous iteration of the PowerVR binding submission [1], the
> > > > number of clocks required for the 6XT family was mentioned to be
> > > > always 3. This is also reflected here.
> > > >
> > > > [1] https://lore.kernel.org/dri-devel/6eeccb26e09aad67fb30ffcd523c793a43c79c2a.camel@imgtec.com/
> > > >
> > > > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> > > > ---
> > > > .../bindings/gpu/img,powervr-rogue.yaml | 24 +++++++++++++++----
> > > > 1 file changed, 20 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> > > > index 256e252f8087..48aa205b66b4 100644
> > > > --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> > > > +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> > > > @@ -12,10 +12,17 @@ maintainers:
> > > >
> > > > properties:
> > > > compatible:
> > > > - items:
> > > > - - enum:
> > > > - - ti,am62-gpu
> > > > - - const: img,img-axe # IMG AXE GPU model/revision is fully discoverable
> > > > + oneOf:
> > > > + - items:
> > > > + - enum:
> > > > + - mediatek,mt8173-gpu
> > > > + # PowerVR 6XT GPU model/revision is fully discoverable
> > > > + - const: img,powervr-6xt
> > > > + - items:
> > > > + - enum:
> > > > + - ti,am62-gpu
> > > > + # IMG AXE GPU model/revision is fully discoverable
> > > > + - const: img,img-axe
> > >
> > > The Series6XT GPU models have differing numbers of power domains (either 2, 4 or
> > > 5). Whereas, the AXE GPUs have a single power domain, so I assume there should
> > > be a related change here.
> > >
> > > The GX6250 has two power domains (lets call them A and B). There's a constraint
> > > that if domain B is powered then domain A must also be powered.
> > >
> > > In patch 6 [2] it's setting the power domain to MT8173_POWER_DOMAIN_MFG, which I
> > > believe corresponds to power domain B. I assume this works because the MTK power
> > > controller driver is encoding the constraint above, meaning that when we disable
> > > or enable MT8173_POWER_DOMAIN_MFG it's also disabling/enabling MT8173_POWER_DOMA
> > > IN_MFG_2D (domain A).
> >
> > It could also be that the power domains are split in the glue layer and there
> > is some sequencing handled there. I'll reach out to MediaTek to see if they
> > can dig up some design specifics.
>
> Unfortunately they said they no longer have that information.
>
> > I assume you would like to see the separate power domains properly modeled
> > in the device tree?
>
> So how should we go about this? Adam, do you have this information for
> your platform?
In the Renesas platform, I only had to add one clock [1] and one
power-domain [2] to get the GPU to come up. In Renesas' downstream
driver, they only use one clock, but Geert, the Renesas tree
maintainer, sent me the three clocks to assign to the 6xt graphics if
it's determined that 3 clocks are required. In terms of the power
domain, there appear to be 2, but one is dependent on another, so
turning on the 'B' power domain turns on the 'A' power domain
automatically. I should note that I can't get the graphics to
function, since the 6xt isn't supported yet, so there could be some
elements missing that I am unaware of.
adam
[1] - https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/drivers/clk/renesas?h=next-20240613&id=f7b0dfffd3e0897ca73916a0c3d3fb61c61df51e
[2] - https://patchwork.kernel.org/project/linux-renesas-soc/patch/20240227034539.193573-3-aford173@gmail.com/
>
> Thanks
> ChenYu
>
> >
> > Thanks
> > ChenYu
> >
> > > Thanks
> > > Frank
> > >
> > > [1] https://lists.freedesktop.org/archives/dri-devel/2024-February/443548.html
> > > [2] https://lists.freedesktop.org/archives/dri-devel/2024-May/455833.html
> > >
> > > >
> > > > reg:
> > > > maxItems: 1
> > > > @@ -56,6 +63,15 @@ allOf:
> > > > properties:
> > > > clocks:
> > > > maxItems: 1
> > > > + - if:
> > > > + properties:
> > > > + compatible:
> > > > + contains:
> > > > + const: img,powervr-6xt
> > > > + then:
> > > > + properties:
> > > > + clocks:
> > > > + minItems: 3
> > > >
> > > > examples:
> > > > - |
^ permalink raw reply [flat|nested] 38+ messages in thread
end of thread, other threads:[~2024-06-13 13:23 UTC | newest]
Thread overview: 38+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-05-30 8:34 [PATCH 0/6] powervr: MT8173 GPU support Chen-Yu Tsai
2024-05-30 8:35 ` [PATCH 1/6] dt-bindings: clock: mediatek: Add mt8173 mfgtop Chen-Yu Tsai
2024-05-30 15:43 ` Conor Dooley
2024-05-31 7:29 ` Chen-Yu Tsai
2024-05-31 14:58 ` Conor Dooley
2024-05-30 8:35 ` [PATCH 2/6] clk: mediatek: Add mt8173-mfgtop driver Chen-Yu Tsai
2024-05-30 9:59 ` AngeloGioacchino Del Regno
2024-05-30 10:16 ` Chen-Yu Tsai
2024-05-30 12:48 ` AngeloGioacchino Del Regno
2024-05-31 11:17 ` Frank Binns
2024-06-05 8:39 ` Chen-Yu Tsai
2024-06-05 11:26 ` AngeloGioacchino Del Regno
2024-05-30 16:15 ` kernel test robot
2024-05-30 16:26 ` kernel test robot
2024-05-30 18:03 ` kernel test robot
2024-05-30 8:35 ` [PATCH 3/6] dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU Chen-Yu Tsai
2024-05-30 10:03 ` AngeloGioacchino Del Regno
2024-05-30 15:38 ` Conor Dooley
2024-05-31 13:37 ` Frank Binns
2024-05-31 14:24 ` Adam Ford
2024-06-04 4:21 ` Chen-Yu Tsai
2024-06-04 4:18 ` Chen-Yu Tsai
2024-06-13 9:10 ` Chen-Yu Tsai
2024-06-13 13:23 ` Adam Ford
2024-05-30 8:35 ` [PATCH 4/6] drm/imagination: Add compatible string entry for Series6XT Chen-Yu Tsai
2024-05-30 10:03 ` AngeloGioacchino Del Regno
2024-05-31 11:18 ` Frank Binns
2024-06-03 3:29 ` Chen-Yu Tsai
2024-06-03 7:45 ` Steven Price
2024-05-30 8:35 ` [PATCH 5/6] arm64: dts: mediatek: mt8173: Fix MFG_ASYNC power domain clock Chen-Yu Tsai
2024-05-30 10:03 ` AngeloGioacchino Del Regno
2024-06-05 8:25 ` Chen-Yu Tsai
2024-06-05 11:25 ` AngeloGioacchino Del Regno
2024-06-06 3:28 ` Chen-Yu Tsai
2024-05-30 8:35 ` [PATCH 6/6] arm64: dts: mediatek: mt8173: Add GPU device nodes Chen-Yu Tsai
2024-05-30 10:04 ` AngeloGioacchino Del Regno
2024-05-31 4:00 ` [PATCH 0/6] powervr: MT8173 GPU support Chen-Yu Tsai
[not found] ` <d4a97a657330d50d14cb93954e8b243489bb51ef.camel@imgtec.com>
2024-06-02 19:53 ` Adam Ford
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