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Tue, 05 May 2026 07:40:14 -0700 (PDT) X-Forwarded-Encrypted: i=1; AFNElJ9SgzrjJLRYorq8hEUx4Ps5PwbSnpAthiCVa7RHu35uq/1xQiH0BTWhZQbGP8M1Q6k/WX+5KKgNXbJzqLCd01yz@lists.infradead.org X-Gm-Message-State: AOJu0Yw7xTFNzt0QJw5OUEOEcIqOeeAvPXXtwfKYG4hbJSVFRMcE90Hw espTD1KIcLC+q227bSd4fQG756zUVh3im84awgkwFB6Oy49U+PiaCxwLZkWHtsJbLrlx0y/gy82 BX3WZ7G7aFQtYLxhwNDwXVc9unp1C1ik= X-Received: by 2002:a05:651c:1550:b0:38e:cab9:362f with SMTP id 38308e7fff4ca-393b4aee55fmr16699711fa.5.1777992012684; Tue, 05 May 2026 07:40:12 -0700 (PDT) MIME-Version: 1.0 References: <20260428-h616-t113s-hstimer-v3-0-7e02178a93ee@mmpsystems.pl> <20260428-h616-t113s-hstimer-v3-3-7e02178a93ee@mmpsystems.pl> In-Reply-To: <20260428-h616-t113s-hstimer-v3-3-7e02178a93ee@mmpsystems.pl> From: Chen-Yu Tsai Date: Tue, 5 May 2026 22:39:59 +0800 X-Gmail-Original-Message-ID: X-Gm-Features: AVHnY4JJpxD2X70zsLR6EJJtacKJo_DgD2S2p0UG0bbAjRuSSF1pdG6HAo4DjV4 Message-ID: Subject: Re: [PATCH v3 3/4] arm: dts: allwinner: t113s: add hstimer node To: Michal Piekos Cc: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jernej Skrabec , Samuel Holland , Maxime Ripard , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Andre Przywara Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260505_074014_861576_C308D82C X-CRM114-Status: GOOD ( 17.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: wens@kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Apr 29, 2026 at 12:29=E2=80=AFAM Michal Piekos wrote: > > Describe high speed timer block on Allwinner T113-S3. > > Tested on LCPI-PC-T113/F113: > - hstimer is registered as clocksource > - switching clocksource at runtime works > - after rating increase hstimer operates as a broadcast clockevent device > > Signed-off-by: Michal Piekos > --- > arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi b/arch/arm/boot= /dts/allwinner/sun8i-t113s.dtsi > index 424f4a2487e2..40e76cfc8a1d 100644 > --- a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi > +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi > @@ -34,6 +34,17 @@ cpu1: cpu@1 { > }; > }; > > + soc { > + hstimer@3008000 { > + compatible =3D "allwinner,sun20i-d1-hstimer"; > + reg =3D <0x03008000 0x1000>; > + interrupts =3D , > + ; > + clocks =3D <&ccu CLK_BUS_HSTIMER>; > + resets =3D <&ccu RST_BUS_HSTIMER>; > + }; > + }; > + Actually this could probably be added to the common risc-v dtsi file instea= d: arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi That way both the D1 and T113 / T113s benefit. ChenYu > gic: interrupt-controller@1c81000 { > compatible =3D "arm,gic-400"; > reg =3D <0x03021000 0x1000>, > > -- > 2.43.0 > >