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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=NBF9nN1amKjoEJYkIjpsAIirOQycb1TH6Xv8hrGX720=; b=UEhEx1sNGvyWATzIHjzhDW2Qju2ov7QcBI4rlrZoAncFGlAzOGfmC56ewNrfW7X2lt TAGhevpbCSvujCg3V05S7Q+Zq4IcJzPSwqOADK6RQkNStRpVmMvqVawQuW/YIwvn+skx eFTauc4LoRTNNUxpUKwVdRaK7dF0vlOf/l0S2fJUOAooWhS46Ngx8YHS4ELIWaLWp5YO jm3D83BzKIzQLf36wgGJoNqQ4aC0xLKEu7Zn82z/fk+6YE+Enhd0e2p7ZCH8frI6Ubh8 t1aN8AAG8Jp+UJcA7JH7BrlUaOyE34uT7sacYHm1CsGpQFyrw/fDjxGO5ugO7RTI5ihH xTNQ== X-Gm-Message-State: ACrzQf00DoV7VZ9IXSMge0XfCn6a5epQwijEy0lvhlLv7QymwpwE/l98 TxyNNO9pnAk0FIJdOCUhHXAVzWGNGpVMK7Wn0lk= X-Google-Smtp-Source: AMsMyM6xp5XG883Sfz6qxUaX5+gPHPonCP4MPn0vbsj6Bzy6ERW5G8ermHkmXVNLJ97zdVUdhxlu0w7L/DMiIXxWfLY= X-Received: by 2002:a17:906:8442:b0:7ad:960b:ef61 with SMTP id e2-20020a170906844200b007ad960bef61mr2610486ejy.702.1666907755828; Thu, 27 Oct 2022 14:55:55 -0700 (PDT) MIME-Version: 1.0 References: <20220921084302.43631-1-yangyicong@huawei.com> <20220921084302.43631-3-yangyicong@huawei.com> <168eac93-a6ee-0b2e-12bb-4222eff24561@arm.com> <8e391962-4e3a-5a56-64b4-78e8637e3b8c@huawei.com> <87o7tx5oyx.fsf@stealth> In-Reply-To: <87o7tx5oyx.fsf@stealth> From: Barry Song <21cnbao@gmail.com> Date: Fri, 28 Oct 2022 10:55:42 +1300 Message-ID: Subject: Re: [PATCH v4 2/2] arm64: support batched/deferred tlb shootdown during page reclamation To: Punit Agrawal Cc: Anshuman Khandual , Yicong Yang , yangyicong@hisilicon.com, corbet@lwn.net, peterz@infradead.org, arnd@arndb.de, linux-kernel@vger.kernel.org, darren@os.amperecomputing.com, huzhanyuan@oppo.com, lipeifeng@oppo.com, zhangshiming@oppo.com, guojian@oppo.com, realmz6@gmail.com, linux-mips@vger.kernel.org, openrisc@lists.librecores.org, linux-mm@kvack.org, x86@kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, akpm@linux-foundation.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, wangkefeng.wang@huawei.com, xhao@linux.alibaba.com, prime.zeng@hisilicon.com, Barry Song , Nadav Amit , Mel Gorman , catalin.marinas@arm.com, will@kernel.org, linux-doc@vger.kernel.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221027_145558_593741_9C485A30 X-CRM114-Status: GOOD ( 34.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Oct 28, 2022 at 3:19 AM Punit Agrawal wrote: > > > [ Apologies for chiming in late in the conversation ] > > Anshuman Khandual writes: > > > On 9/28/22 05:53, Barry Song wrote: > >> On Tue, Sep 27, 2022 at 10:15 PM Yicong Yang wrote: > >>> > >>> On 2022/9/27 14:16, Anshuman Khandual wrote: > >>>> [...] > >>>> > >>>> On 9/21/22 14:13, Yicong Yang wrote: > >>>>> +static inline bool arch_tlbbatch_should_defer(struct mm_struct *mm) > >>>>> +{ > >>>>> + /* for small systems with small number of CPUs, TLB shootdown is cheap */ > >>>>> + if (num_online_cpus() <= 4) > >>>> > >>>> It would be great to have some more inputs from others, whether 4 (which should > >>>> to be codified into a macro e.g ARM64_NR_CPU_DEFERRED_TLB, or something similar) > >>>> is optimal for an wide range of arm64 platforms. > >>>> > >> > >> I have tested it on a 4-cpus and 8-cpus machine. but i have no machine > >> with 5,6,7 > >> cores. > >> I saw improvement on 8-cpus machines and I found 4-cpus machines don't need > >> this patch. > >> > >> so it seems safe to have > >> if (num_online_cpus() < 8) > >> > >>> > >>> Do you prefer this macro to be static or make it configurable through kconfig then > >>> different platforms can make choice based on their own situations? It maybe hard to > >>> test on all the arm64 platforms. > >> > >> Maybe we can have this default enabled on machines with 8 and more cpus and > >> provide a tlbflush_batched = on or off to allow users enable or > >> disable it according > >> to their hardware and products. Similar example: rodata=on or off. > > > > No, sounds bit excessive. Kernel command line options should not be added > > for every possible run time switch options. > > > >> > >> Hi Anshuman, Will, Catalin, Andrew, > >> what do you think about this approach? > >> > >> BTW, haoxin mentioned another important user scenarios for tlb bach on arm64: > >> https://lore.kernel.org/lkml/393d6318-aa38-01ed-6ad8-f9eac89bf0fc@linux.alibaba.com/ > >> > >> I do believe we need it based on the expensive cost of tlb shootdown in arm64 > >> even by hardware broadcast. > > > > Alright, for now could we enable ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH selectively > > with CONFIG_EXPERT and for num_online_cpus() > 8 ? > > When running the test program in the commit in a VM, I saw benefits from > the patches at all sizes from 2, 4, 8, 32 vcpus. On the test machine, > ptep_clear_flush() went from ~1% in the unpatched version to not showing > up. > > Yicong mentioned that he didn't see any benefit for <= 4 CPUs but is > there any overhead? I am wondering what are the downsides of enabling > the config by default. As we are deferring tlb flush, but sometimes while we are modifying the vma which are deferred, we need to do a sync by flush_tlb_batched_pending() in mprotect() , madvise() to make sure they can see the flushed result. if nobody is doing mprotect(), madvise() etc in the deferred period, the overhead is zero. > > Thanks, > Punit Thanks Barry _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel