[PATCH 0/8] ARM: dts: broadcom-bcmbca: Fixes amd I2C buses

[PATCH 0/8] ARM: dts: broadcom-bcmbca: Fixes amd I2C buses

[Linus Walleij]

This fixes some of my own errors in assigning IRQs to the
32bit ARM BCMBCA peripherals, and adds the I2C bus to the
32bit BCMBCA machines.

Maybe the first fix patches should be applied separately,
I don't think there are many users so I think these can
just be applied as regular patches for -next.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Linus Walleij (8):
      ARM: dts: bcm6878: Fix PL081 DMA block IRQ
      ARM: dts: bcm63138: Fix RNG and DMA IRQs
      ARM: dts: bcm63148: Fix RNG IRQ
      ARM: dts: bcm6846: Add I2C bus block
      ARM: dts: bcm6855: Add I2C bus blocks
      ARM: dts: bcm6878: Add I2C bus block
      ARM: dts: bcm63138: Add STB I2C block
      ARM: dts: bcm63148: Add STB I2C block

 arch/arm/boot/dts/broadcom/bcm63138.dtsi | 13 +++++++++++--
 arch/arm/boot/dts/broadcom/bcm63148.dtsi | 13 +++++++++++--
 arch/arm/boot/dts/broadcom/bcm6846.dtsi  |  9 +++++++++
 arch/arm/boot/dts/broadcom/bcm6855.dtsi  | 18 ++++++++++++++++++
 arch/arm/boot/dts/broadcom/bcm6878.dtsi  | 11 ++++++++++-
 5 files changed, 59 insertions(+), 5 deletions(-)
---
base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585
change-id: 20250901-bcmbca-i2c-dts-1df63defc310

Best regards,
-- 
Linus Walleij <linus.walleij@linaro.org>

[PATCH 1/8] ARM: dts: bcm6878: Fix PL081 DMA block IRQ

[Linus Walleij]

This iRQ is on SPI_TABLE_OFFSET_2 which begins at
64, designated 64+30 = 94.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 arch/arm/boot/dts/broadcom/bcm6878.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/broadcom/bcm6878.dtsi b/arch/arm/boot/dts/broadcom/bcm6878.dtsi
index dd837bf693905736a7b8ef9cfefea8368e6df6ed..5a37bfd7f53f16fa07cc93b570a585ec34f5f443 100644
--- a/arch/arm/boot/dts/broadcom/bcm6878.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm6878.dtsi
@@ -244,7 +244,7 @@ pl081_dma: dma-controller@11000 {
 			// The magic B105F00D info is missing
 			arm,primecell-periphid = <0x00041081>;
 			reg = <0x11000 0x1000>;
-			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 			memcpy-burst-size = <256>;
 			memcpy-bus-width = <32>;
 			clocks = <&periph_clk>;

-- 
2.50.1

[PATCH 2/8] ARM: dts: bcm63138: Fix RNG and DMA IRQs

[Linus Walleij]

The RNG and DMA IRQs are wrong: these begin at
ISR_TABLE3_OFFSET at 94, and are at 94+21 and 94+23
respectively.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 arch/arm/boot/dts/broadcom/bcm63138.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/broadcom/bcm63138.dtsi b/arch/arm/boot/dts/broadcom/bcm63138.dtsi
index 4ec568586b14c89daceddea8f17381f72f512a93..d7410bb1b5a8e221d7ca1f2f299ce6d2bc40b763 100644
--- a/arch/arm/boot/dts/broadcom/bcm63138.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm63138.dtsi
@@ -244,7 +244,7 @@ gpio4: gpio@110 {
 		rng@300 {
 			compatible = "brcm,iproc-rng200";
 			reg = <0x300 0x28>;
-			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
 		serial0: serial@600 {
@@ -317,7 +317,7 @@ pl081_dma: dma-controller@d000 {
 			// The magic B105F00D info is missing
 			arm,primecell-periphid = <0x00041081>;
 			reg = <0xd000 0x1000>;
-			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 			memcpy-burst-size = <256>;
 			memcpy-bus-width = <32>;
 			clocks = <&periph_clk>;

-- 
2.50.1

[PATCH 3/8] ARM: dts: bcm63148: Fix RNG IRQ

[Linus Walleij]

The BCM63148 RNG is at IRS_TABLE3_OFFSET at 94 so
the IRQ is at 94+21 = 115.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 arch/arm/boot/dts/broadcom/bcm63148.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/broadcom/bcm63148.dtsi b/arch/arm/boot/dts/broadcom/bcm63148.dtsi
index e071cddb28fc2888b8f408b4bc275290dd135642..d94da16ab799c0ab25946e9cf24ae25812e85817 100644
--- a/arch/arm/boot/dts/broadcom/bcm63148.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm63148.dtsi
@@ -152,7 +152,7 @@ gpio4: gpio@110 {
 		rng@300 {
 			compatible = "brcm,iproc-rng200";
 			reg = <0x300 0x28>;
-			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
 		uart0: serial@600 {

-- 
2.50.1

[PATCH 4/8] ARM: dts: bcm6846: Add I2C bus block

[Linus Walleij]

The BCM6846 has a STB I2C block.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 arch/arm/boot/dts/broadcom/bcm6846.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/broadcom/bcm6846.dtsi b/arch/arm/boot/dts/broadcom/bcm6846.dtsi
index f5591a45d2e4ad64d8f95680aea327771825252b..ac5c810a92d76f1130d0caf0286d6401e0e7bbe6 100644
--- a/arch/arm/boot/dts/broadcom/bcm6846.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm6846.dtsi
@@ -242,6 +242,15 @@ mdio: mdio@2060 {
 			status = "disabled";
 		};
 
+		i2c0: i2c@2100 {
+			compatible = "brcm,brcmstb-i2c";
+			reg = <0x2100 0x60>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		pl081_dma: dma-controller@59000 {
 			compatible = "arm,pl081", "arm,primecell";
 			// The magic B105F00D info is missing

-- 
2.50.1

[PATCH 5/8] ARM: dts: bcm6855: Add I2C bus blocks

[Linus Walleij]

The BCM6855 has two STB I2C blocks, the second one in
the PERF1 area at 0xff85a800, this is covered by the
current bus range.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 arch/arm/boot/dts/broadcom/bcm6855.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/broadcom/bcm6855.dtsi b/arch/arm/boot/dts/broadcom/bcm6855.dtsi
index a88c3f0fbcb037ee5c6b31933415f90cb51ded2a..d74788c6ebf5f4f69887c496d508c35d276d0b0b 100644
--- a/arch/arm/boot/dts/broadcom/bcm6855.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm6855.dtsi
@@ -240,6 +240,15 @@ nandcs: nand@0 {
 			};
 		};
 
+		i2c0: i2c@2100 {
+			compatible = "brcm,brcmstb-i2c";
+			reg = <0x2100 0x60>;
+			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		leds: led-controller@3000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -278,5 +287,14 @@ uart1: serial@13000 {
 			clock-names = "uartclk", "apb_pclk";
 			status = "disabled";
 		};
+
+		i2c1: i2c@5a800 {
+			compatible = "brcm,brcmstb-i2c";
+			reg = <0x5a800 0x60>;
+			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
 	};
 };

-- 
2.50.1

[PATCH 6/8] ARM: dts: bcm6878: Add I2C bus block

[Linus Walleij]

The BCM6878 has an STB I2C block.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 arch/arm/boot/dts/broadcom/bcm6878.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/broadcom/bcm6878.dtsi b/arch/arm/boot/dts/broadcom/bcm6878.dtsi
index 5a37bfd7f53f16fa07cc93b570a585ec34f5f443..c08f532618493b166b10dbdbd45194ad843baf18 100644
--- a/arch/arm/boot/dts/broadcom/bcm6878.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm6878.dtsi
@@ -239,6 +239,15 @@ nandcs: nand@0 {
 			};
 		};
 
+		i2c0: i2c@2100 {
+			compatible = "brcm,brcmstb-i2c";
+			reg = <0x2100 0x60>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		pl081_dma: dma-controller@11000 {
 			compatible = "arm,pl081", "arm,primecell";
 			// The magic B105F00D info is missing

-- 
2.50.1

[PATCH 7/8] ARM: dts: bcm63138: Add STB I2C block

[Linus Walleij]

The BCM63138 has a STB I2C block.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 arch/arm/boot/dts/broadcom/bcm63138.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/broadcom/bcm63138.dtsi b/arch/arm/boot/dts/broadcom/bcm63138.dtsi
index d7410bb1b5a8e221d7ca1f2f299ce6d2bc40b763..3bf41760ea52a74632744c50a5d096e8b193a046 100644
--- a/arch/arm/boot/dts/broadcom/bcm63138.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm63138.dtsi
@@ -312,6 +312,15 @@ bootlut: bootlut@8000 {
 			reg = <0x8000 0x50>;
 		};
 
+		i2c0: i2c@be00 {
+			compatible = "brcm,brcmstb-i2c";
+			reg = <0xbe00 0x60>;
+			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		pl081_dma: dma-controller@d000 {
 			compatible = "arm,pl081", "arm,primecell";
 			// The magic B105F00D info is missing

-- 
2.50.1

[PATCH 8/8] ARM: dts: bcm63148: Add STB I2C block

[Linus Walleij]

The BCM63148 has a STB I2C block.

The peripheral range needs to be extended to accommodate
it. The Boot LUT is at offset + 0x10000 so extend it to
cover at least that too, 128 KB.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 arch/arm/boot/dts/broadcom/bcm63148.dtsi | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/broadcom/bcm63148.dtsi b/arch/arm/boot/dts/broadcom/bcm63148.dtsi
index d94da16ab799c0ab25946e9cf24ae25812e85817..76c418030fbef3352e8266b679541c9129338eae 100644
--- a/arch/arm/boot/dts/broadcom/bcm63148.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm63148.dtsi
@@ -97,7 +97,7 @@ bus@ff800000 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
-		ranges = <0 0xfffe8000 0x8000>;
+		ranges = <0 0xfffe8000 0x20000>;
 
 		/* GPIOs 0 .. 31 */
 		gpio0: gpio@100 {
@@ -197,5 +197,14 @@ nandcs: nand@0 {
 				reg = <0>;
 			};
 		};
+
+		i2c0: i2c@be00 {
+			compatible = "brcm,brcmstb-i2c";
+			reg = <0xbe00 0x60>;
+			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
 	};
 };

-- 
2.50.1

Re: [PATCH 4/8] ARM: dts: bcm6846: Add I2C bus block

[Florian Fainelli]

On 9/1/2025 5:50 AM, Linus Walleij wrote:
> The BCM6846 has a STB I2C block.
> 
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
>   arch/arm/boot/dts/broadcom/bcm6846.dtsi | 9 +++++++++
>   1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/broadcom/bcm6846.dtsi b/arch/arm/boot/dts/broadcom/bcm6846.dtsi
> index f5591a45d2e4ad64d8f95680aea327771825252b..ac5c810a92d76f1130d0caf0286d6401e0e7bbe6 100644
> --- a/arch/arm/boot/dts/broadcom/bcm6846.dtsi
> +++ b/arch/arm/boot/dts/broadcom/bcm6846.dtsi
> @@ -242,6 +242,15 @@ mdio: mdio@2060 {
>   			status = "disabled";
>   		};
>   
> +		i2c0: i2c@2100 {
> +			compatible = "brcm,brcmstb-i2c";

Historically the BCA SoCs have byte-sized FIFOs rather than word-sized 
FIFOs which is why the compatible string "brcm,brcmper-i2c" was defined. 
I assume this was changed at some point and this works correctly with 
the "brcm,brcmstb-i2c" compatible string.

Was there any I2C peripheral you could interface with?

> +			reg = <0x2100 0x60>;
> +			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
>   		pl081_dma: dma-controller@59000 {
>   			compatible = "arm,pl081", "arm,primecell";
>   			// The magic B105F00D info is missing
> 

-- 
Florian

Re: [PATCH 2/8] ARM: dts: bcm63138: Fix RNG and DMA IRQs

[William Zhang]

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Hi Linus,

On Mon, Sep 1, 2025 at 5:50 AM Linus Walleij <linus.walleij@linaro.org> wrote:
>
> The RNG and DMA IRQs are wrong: these begin at
> ISR_TABLE3_OFFSET at 94, and are at 94+21 and 94+23
ISR_TABLE3_OFFSET is 96 in the legacy 63138_intr.h.
INTERRUPT_ID_RNG is (ISR_TABLE3_OFFSET + 21)
which is 117. Converting back dtsi SPI interrupt is 117-32 = 85
So the original value is correct.  DMA interrupt number need to
be corrected to 87.

Please note there is some inconsistent definition of the ISR table
offset between chips.   But whatever their number is,  the dts SPI interrupt
is always equal to INTERRUPT_ID - 32.

> respectively.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
>  arch/arm/boot/dts/broadcom/bcm63138.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/broadcom/bcm63138.dtsi b/arch/arm/boot/dts/broadcom/bcm63138.dtsi
> index 4ec568586b14c89daceddea8f17381f72f512a93..d7410bb1b5a8e221d7ca1f2f299ce6d2bc40b763 100644
> --- a/arch/arm/boot/dts/broadcom/bcm63138.dtsi
> +++ b/arch/arm/boot/dts/broadcom/bcm63138.dtsi
> @@ -244,7 +244,7 @@ gpio4: gpio@110 {
>                 rng@300 {
>                         compatible = "brcm,iproc-rng200";
>                         reg = <0x300 0x28>;
> -                       interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>                 };
>
>                 serial0: serial@600 {
> @@ -317,7 +317,7 @@ pl081_dma: dma-controller@d000 {
>                         // The magic B105F00D info is missing
>                         arm,primecell-periphid = <0x00041081>;
>                         reg = <0xd000 0x1000>;
> -                       interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
>                         memcpy-burst-size = <256>;
>                         memcpy-bus-width = <32>;
>                         clocks = <&periph_clk>;
>
> --
> 2.50.1
>

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Re: [PATCH 1/8] ARM: dts: bcm6878: Fix PL081 DMA block IRQ

[William Zhang]

[-- Attachment #1: Type: text/plain, Size: 1457 bytes --]

On Mon, Sep 1, 2025 at 5:50 AM Linus Walleij <linus.walleij@linaro.org> wrote:
>
> This iRQ is on SPI_TABLE_OFFSET_2 which begins at
> 64, designated 64+30 = 94.
>
SPI_TABLE_OFFSET_2 is 96 in 6878.  96+30 = 126.  Convert back
dtsi SPI interrupt 126 - 32 = 94

The change is good but just want to point out the table definition
value and the conversion.

Reviewed-by: William Zhang <william.zhang@broadcom.com>

> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
>  arch/arm/boot/dts/broadcom/bcm6878.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/broadcom/bcm6878.dtsi b/arch/arm/boot/dts/broadcom/bcm6878.dtsi
> index dd837bf693905736a7b8ef9cfefea8368e6df6ed..5a37bfd7f53f16fa07cc93b570a585ec34f5f443 100644
> --- a/arch/arm/boot/dts/broadcom/bcm6878.dtsi
> +++ b/arch/arm/boot/dts/broadcom/bcm6878.dtsi
> @@ -244,7 +244,7 @@ pl081_dma: dma-controller@11000 {
>                         // The magic B105F00D info is missing
>                         arm,primecell-periphid = <0x00041081>;
>                         reg = <0x11000 0x1000>;
> -                       interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>                         memcpy-burst-size = <256>;
>                         memcpy-bus-width = <32>;
>                         clocks = <&periph_clk>;
>
> --
> 2.50.1
>

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Re: [PATCH 3/8] ARM: dts: bcm63148: Fix RNG IRQ

[William Zhang]

[-- Attachment #1: Type: text/plain, Size: 1200 bytes --]

On Mon, Sep 1, 2025 at 5:50 AM Linus Walleij <linus.walleij@linaro.org> wrote:
>
> The BCM63148 RNG is at IRS_TABLE3_OFFSET at 94 so
> the IRQ is at 94+21 = 115.
>
TABLE3 offset 96.  96 + 21 - 32 = 85.  Original value is correct.
When in doubt,  you can always cross check
the uart0 interrupt definition.

> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
>  arch/arm/boot/dts/broadcom/bcm63148.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/broadcom/bcm63148.dtsi b/arch/arm/boot/dts/broadcom/bcm63148.dtsi
> index e071cddb28fc2888b8f408b4bc275290dd135642..d94da16ab799c0ab25946e9cf24ae25812e85817 100644
> --- a/arch/arm/boot/dts/broadcom/bcm63148.dtsi
> +++ b/arch/arm/boot/dts/broadcom/bcm63148.dtsi
> @@ -152,7 +152,7 @@ gpio4: gpio@110 {
>                 rng@300 {
>                         compatible = "brcm,iproc-rng200";
>                         reg = <0x300 0x28>;
> -                       interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>                 };
>
>                 uart0: serial@600 {
>
> --
> 2.50.1
>

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Re: [PATCH 7/8] ARM: dts: bcm63138: Add STB I2C block

[William Zhang]

[-- Attachment #1: Type: text/plain, Size: 1339 bytes --]

dtsi interrupt should be 83.

On Mon, Sep 1, 2025 at 5:50 AM Linus Walleij <linus.walleij@linaro.org> wrote:
>
> The BCM63138 has a STB I2C block.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
>  arch/arm/boot/dts/broadcom/bcm63138.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm/boot/dts/broadcom/bcm63138.dtsi b/arch/arm/boot/dts/broadcom/bcm63138.dtsi
> index d7410bb1b5a8e221d7ca1f2f299ce6d2bc40b763..3bf41760ea52a74632744c50a5d096e8b193a046 100644
> --- a/arch/arm/boot/dts/broadcom/bcm63138.dtsi
> +++ b/arch/arm/boot/dts/broadcom/bcm63138.dtsi
> @@ -312,6 +312,15 @@ bootlut: bootlut@8000 {
>                         reg = <0x8000 0x50>;
>                 };
>
> +               i2c0: i2c@be00 {
> +                       compatible = "brcm,brcmstb-i2c";
> +                       reg = <0xbe00 0x60>;
> +                       interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
>                 pl081_dma: dma-controller@d000 {
>                         compatible = "arm,pl081", "arm,primecell";
>                         // The magic B105F00D info is missing
>
> --
> 2.50.1
>

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Re: [PATCH 8/8] ARM: dts: bcm63148: Add STB I2C block

[William Zhang]

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dtsi interrupt number 83.

On Mon, Sep 1, 2025 at 5:50 AM Linus Walleij <linus.walleij@linaro.org> wrote:
>
> The BCM63148 has a STB I2C block.
>
> The peripheral range needs to be extended to accommodate
> it. The Boot LUT is at offset + 0x10000 so extend it to
> cover at least that too, 128 KB.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
>  arch/arm/boot/dts/broadcom/bcm63148.dtsi | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/broadcom/bcm63148.dtsi b/arch/arm/boot/dts/broadcom/bcm63148.dtsi
> index d94da16ab799c0ab25946e9cf24ae25812e85817..76c418030fbef3352e8266b679541c9129338eae 100644
> --- a/arch/arm/boot/dts/broadcom/bcm63148.dtsi
> +++ b/arch/arm/boot/dts/broadcom/bcm63148.dtsi
> @@ -97,7 +97,7 @@ bus@ff800000 {
>                 compatible = "simple-bus";
>                 #address-cells = <1>;
>                 #size-cells = <1>;
> -               ranges = <0 0xfffe8000 0x8000>;
> +               ranges = <0 0xfffe8000 0x20000>;
>
>                 /* GPIOs 0 .. 31 */
>                 gpio0: gpio@100 {
> @@ -197,5 +197,14 @@ nandcs: nand@0 {
>                                 reg = <0>;
>                         };
>                 };
> +
> +               i2c0: i2c@be00 {
> +                       compatible = "brcm,brcmstb-i2c";
> +                       reg = <0xbe00 0x60>;
> +                       interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
>         };
>  };
>
> --
> 2.50.1
>

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Re: [PATCH 4/8] ARM: dts: bcm6846: Add I2C bus block

[Linus Walleij]

On Mon, Sep 1, 2025 at 5:49 PM Florian Fainelli
<florian.fainelli@broadcom.com> wrote:
> On 9/1/2025 5:50 AM, Linus Walleij wrote:


> > +             i2c0: i2c@2100 {
> > +                     compatible = "brcm,brcmstb-i2c";
>
> Historically the BCA SoCs have byte-sized FIFOs rather than word-sized
> FIFOs which is why the compatible string "brcm,brcmper-i2c" was defined.
> I assume this was changed at some point and this works correctly with
> the "brcm,brcmstb-i2c" compatible string.
>
> Was there any I2C peripheral you could interface with?

Good question!

I have an SFP on I2C and it doesn't connect with either mode of the
I2C, I think because I need pin control for BCA working first :(

I look into the i2c_bcm63xxx.c driver by Prataba Reddy, which
is what at least BCM6846 is using. The register access looks like this:

/* Read the value from given bcm63000 register */
static inline int reg_read(uint32* offset)
{
    int ret;
    ret = *offset;
    BCM_LOG_DEBUG(BCM_LOG_ID_I2C, "reg_read: offset = %lx, val is %x\n",
                  (long int)offset, ret);
    return ret;
}

/* Write the given value to given bcm63000 register */
static inline void reg_write(uint32* offset, int val)
{
    BCM_LOG_DEBUG(BCM_LOG_ID_I2C, "reg_write: offset = %lx; val = %x\n",
                  (long int)offset, val);
    *offset = val;
}

And those are used like this for the FIFO (read):

        /* Read the data */
        if (fifo_len == 8)
        {
            for (j = 0; j < xfer_cnt; j++)
                buf[i*fifo_len + j] =
                    (u8)reg_read((uint32 *)&i2c_dev->reg_base->DataOut0 + j);
        }
        else
        {
            int num_dwords = (xfer_cnt)/4;
            int left_over = (xfer_cnt)%4;
            int temp_data=0;
            for (j = 0; j < num_dwords; j++)
            {
#ifdef __LITTLE_ENDIAN
                *((int *)&buf[i*fifo_len + j*4]) =
                    reg_read((uint32 *)&i2c_dev->reg_base->DataOut0 + j);
#else
                *((int *)&buf[i*fifo_len + j*4]) =
                    swab32(reg_read((uint32
*)&i2c_dev->reg_base->DataOut0 + j));
#endif
            }
            if(left_over)
            {
#ifdef __LITTLE_ENDIAN
                temp_data =
                    reg_read((uint32 *)&i2c_dev->reg_base->DataOut0 + j);
#else
                temp_data =
                    swab32(reg_read((uint32
*)&i2c_dev->reg_base->DataOut0 + j));
#endif
                memcpy((char*)&buf[i*fifo_len + j*4],
(char*)&temp_data, left_over);

            }

        }

And for write:

        /* Write the data */
        if (fifo_len == 8)
        {
            for (j = 0; j < xfer_cnt; j++)
                reg_write((uint32 *)&i2c_dev->reg_base->DataIn0 + j,
buf[i * fifo_len + j]);
        }
        else
        {
            int num_dwords = (xfer_cnt + 3)/4;
            for (j = 0; j < num_dwords; j++)
            {
#ifdef __LITTLE_ENDIAN
                reg_write((uint32 *)&i2c_dev->reg_base->DataIn0 + j,
                          *((int *)&buf[i * fifo_len + j*4]));
#else
                reg_write((uint32 *)&i2c_dev->reg_base->DataIn0 + j,
                          swab32(*((int *)&buf[i * fifo_len + j*4])));
#endif
            }
        }


To me this looks like 32bit access and one byte in the LSB of each
32bit word. But the FIFO data_regsz code in i2c-brcmstb.c is a bit
terse here, which one should I be using?

I guess brcm,brcmper-i2c?

Unfortunately Documentation/devicetree/bindings/i2c/brcm,brcmstb-i2c.yaml
isn't very helpful with this, I can patch it after we conclude this.

Yours,
Linus Walleij