* [RFC PATCH v2 1/3] arm64: dts: imx8mm: Add eLCDIF node support
2021-11-11 10:14 [RFC PATCH v2 0/3] arm64: imx8mm: Add MIPI DSI support Jagan Teki
@ 2021-11-11 10:14 ` Jagan Teki
2021-11-12 0:38 ` Tim Harvey
2021-11-11 10:14 ` [RFC PATCH v2 2/3] arm64: dts: imx8mm: Add MIPI DSI pipeline Jagan Teki
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: Jagan Teki @ 2021-11-11 10:14 UTC (permalink / raw)
To: Tim Harvey, Adam Ford, Fabio Estevam, Lucas Stach, Peng Fan,
Shawn Guo, Marek Vasut, Frieder Schrempf
Cc: NXP Linux Team, linux-arm-kernel, dri-devel, linux-amarula,
Matteo Lisi, Jagan Teki
Add eLCDIF controller node for i.MX8MM.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index c2f3f118f82e..caeb93313413 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1068,6 +1068,25 @@ aips4: bus@32c00000 {
#size-cells = <1>;
ranges = <0x32c00000 0x32c00000 0x400000>;
+ lcdif: lcdif@32e00000 {
+ compatible = "fsl,imx28-lcdif";
+ reg = <0x32e00000 0x10000>;
+ clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
+ <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MM_CLK_DISP_APB_ROOT>;
+ clock-names = "pix", "disp_axi", "axi";
+ assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
+ <&clk IMX8MM_CLK_DISP_AXI>,
+ <&clk IMX8MM_CLK_DISP_APB>;
+ assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
+ <&clk IMX8MM_SYS_PLL2_1000M>,
+ <&clk IMX8MM_SYS_PLL1_800M>;
+ assigned-clock-rate = <594000000>, <500000000>, <200000000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
+ status = "disabled";
+ };
+
disp_blk_ctrl: blk-ctrl@32e28000 {
compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
reg = <0x32e28000 0x100>;
--
2.25.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [RFC PATCH v2 1/3] arm64: dts: imx8mm: Add eLCDIF node support
2021-11-11 10:14 ` [RFC PATCH v2 1/3] arm64: dts: imx8mm: Add eLCDIF node support Jagan Teki
@ 2021-11-12 0:38 ` Tim Harvey
0 siblings, 0 replies; 10+ messages in thread
From: Tim Harvey @ 2021-11-12 0:38 UTC (permalink / raw)
To: Jagan Teki
Cc: Adam Ford, Fabio Estevam, Lucas Stach, Peng Fan, Shawn Guo,
Marek Vasut, Frieder Schrempf, NXP Linux Team,
Linux ARM Mailing List, DRI mailing list, linux-amarula,
Matteo Lisi, Device Tree Mailing List
On Thu, Nov 11, 2021 at 2:15 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> Add eLCDIF controller node for i.MX8MM.
>
Jagan,
It doesn't look like you sent this to the Device Tree mainling list so
I added that to cc.
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index c2f3f118f82e..caeb93313413 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1068,6 +1068,25 @@ aips4: bus@32c00000 {
> #size-cells = <1>;
> ranges = <0x32c00000 0x32c00000 0x400000>;
>
> + lcdif: lcdif@32e00000 {
> + compatible = "fsl,imx28-lcdif";
> + reg = <0x32e00000 0x10000>;
> + clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
> + <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
> + <&clk IMX8MM_CLK_DISP_APB_ROOT>;
> + clock-names = "pix", "disp_axi", "axi";
> + assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
> + <&clk IMX8MM_CLK_DISP_AXI>,
> + <&clk IMX8MM_CLK_DISP_APB>;
> + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
> + <&clk IMX8MM_SYS_PLL2_1000M>,
> + <&clk IMX8MM_SYS_PLL1_800M>;
> + assigned-clock-rate = <594000000>, <500000000>, <200000000>;
> + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
> + status = "disabled";
> + };
> +
> disp_blk_ctrl: blk-ctrl@32e28000 {
> compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
> reg = <0x32e28000 0x100>;
> --
> 2.25.1
>
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [RFC PATCH v2 2/3] arm64: dts: imx8mm: Add MIPI DSI pipeline
2021-11-11 10:14 [RFC PATCH v2 0/3] arm64: imx8mm: Add MIPI DSI support Jagan Teki
2021-11-11 10:14 ` [RFC PATCH v2 1/3] arm64: dts: imx8mm: Add eLCDIF node support Jagan Teki
@ 2021-11-11 10:14 ` Jagan Teki
2021-11-11 10:21 ` Marek Vasut
2021-11-12 0:36 ` Tim Harvey
2021-11-11 10:14 ` [RFC PATCH v2 3/3] arm64: dts: imx8mm-icore: Enable LVDS panel for EDIMM2.2 Jagan Teki
2021-11-12 0:10 ` [RFC PATCH v2 0/3] arm64: imx8mm: Add MIPI DSI support Tim Harvey
3 siblings, 2 replies; 10+ messages in thread
From: Jagan Teki @ 2021-11-11 10:14 UTC (permalink / raw)
To: Tim Harvey, Adam Ford, Fabio Estevam, Lucas Stach, Peng Fan,
Shawn Guo, Marek Vasut, Frieder Schrempf
Cc: NXP Linux Team, linux-arm-kernel, dri-devel, linux-amarula,
Matteo Lisi, Jagan Teki
Add MIPI DSI pipeline for i.MX8MM.
Video pipeline start from eLCDIF to MIPI DSI and respective
Panel or Bridge on the backend side.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 55 +++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index caeb93313413..eddf3a467fd2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -188,6 +188,12 @@ clk_ext4: clock-ext4 {
clock-output-names = "clk_ext4";
};
+ mipi_phy: mipi-video-phy {
+ compatible = "fsl,imx8mm-mipi-video-phy";
+ syscon = <&disp_blk_ctrl>;
+ #phy-cells = <1>;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -1085,6 +1091,55 @@ lcdif: lcdif@32e00000 {
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
status = "disabled";
+
+ port {
+ lcdif_out_dsi: endpoint {
+ remote-endpoint = <&dsi_in_lcdif>;
+ };
+ };
+ };
+
+ dsi: dsi@32e10000 {
+ compatible = "fsl,imx8mm-mipi-dsim";
+ reg = <0x32e10000 0x400>;
+ clocks = <&clk IMX8MM_CLK_DSI_CORE>,
+ <&clk IMX8MM_CLK_DSI_PHY_REF>;
+ clock-names = "bus_clk", "sclk_mipi";
+ assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
+ <&clk IMX8MM_VIDEO_PLL1_OUT>,
+ <&clk IMX8MM_CLK_DSI_PHY_REF>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
+ <&clk IMX8MM_VIDEO_PLL1_BYPASS>,
+ <&clk IMX8MM_VIDEO_PLL1_OUT>;
+ assigned-clock-rates = <266000000>, <594000000>, <27000000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&mipi_phy 0>;
+ phy-names = "dsim";
+ power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
+ samsung,burst-clock-frequency = <891000000>;
+ samsung,esc-clock-frequency = <54000000>;
+ samsung,pll-clock-frequency = <27000000>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi_in_lcdif: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&lcdif_out_dsi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
};
disp_blk_ctrl: blk-ctrl@32e28000 {
--
2.25.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [RFC PATCH v2 2/3] arm64: dts: imx8mm: Add MIPI DSI pipeline
2021-11-11 10:14 ` [RFC PATCH v2 2/3] arm64: dts: imx8mm: Add MIPI DSI pipeline Jagan Teki
@ 2021-11-11 10:21 ` Marek Vasut
2021-11-11 16:31 ` Jagan Teki
2021-11-12 0:36 ` Tim Harvey
1 sibling, 1 reply; 10+ messages in thread
From: Marek Vasut @ 2021-11-11 10:21 UTC (permalink / raw)
To: Jagan Teki, Tim Harvey, Adam Ford, Fabio Estevam, Lucas Stach,
Peng Fan, Shawn Guo, Frieder Schrempf
Cc: NXP Linux Team, linux-arm-kernel, dri-devel, linux-amarula,
Matteo Lisi
On 11/11/21 11:14 AM, Jagan Teki wrote:
[...]
> + dsi: dsi@32e10000 {
> + compatible = "fsl,imx8mm-mipi-dsim";
> + reg = <0x32e10000 0x400>;
> + clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> + <&clk IMX8MM_CLK_DSI_PHY_REF>;
> + clock-names = "bus_clk", "sclk_mipi";
> + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> + <&clk IMX8MM_VIDEO_PLL1_OUT>,
> + <&clk IMX8MM_CLK_DSI_PHY_REF>;
> + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
> + <&clk IMX8MM_VIDEO_PLL1_BYPASS>,
> + <&clk IMX8MM_VIDEO_PLL1_OUT>;
> + assigned-clock-rates = <266000000>, <594000000>, <27000000>;
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&mipi_phy 0>;
> + phy-names = "dsim";
> + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
> + samsung,burst-clock-frequency = <891000000>;
> + samsung,esc-clock-frequency = <54000000>;
> + samsung,pll-clock-frequency = <27000000>;
> + status = "disabled";
This 27 MHz is really IMX8MM_CLK_DSI_PHY_REF and
samsung,burst-clock-frequency is really the DSI link clock which is
panel/bridge specific ... but, why do we need to specify such policy in
DT rather than have the panel/bridge drivers negotiate the best clock
settings with DSIM bridge driver ? This should be something which should
be implemented in the DRM subsystem, not hard-coded in DT. These ad-hoc
samsung,*-clock-frequency properties shouldn't even be needed then.
Also, are the DSIM bindings stable now ?
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^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [RFC PATCH v2 2/3] arm64: dts: imx8mm: Add MIPI DSI pipeline
2021-11-11 10:21 ` Marek Vasut
@ 2021-11-11 16:31 ` Jagan Teki
0 siblings, 0 replies; 10+ messages in thread
From: Jagan Teki @ 2021-11-11 16:31 UTC (permalink / raw)
To: Marek Vasut, Laurent Pinchart, Dae
Cc: Tim Harvey, Adam Ford, Fabio Estevam, Lucas Stach, Peng Fan,
Shawn Guo, Frieder Schrempf, NXP Linux Team, linux-arm-kernel,
dri-devel, linux-amarula, Matteo Lisi
On Thu, Nov 11, 2021 at 3:51 PM Marek Vasut <marex@denx.de> wrote:
>
> On 11/11/21 11:14 AM, Jagan Teki wrote:
>
> [...]
>
> > + dsi: dsi@32e10000 {
> > + compatible = "fsl,imx8mm-mipi-dsim";
> > + reg = <0x32e10000 0x400>;
> > + clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> > + <&clk IMX8MM_CLK_DSI_PHY_REF>;
> > + clock-names = "bus_clk", "sclk_mipi";
> > + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> > + <&clk IMX8MM_VIDEO_PLL1_OUT>,
> > + <&clk IMX8MM_CLK_DSI_PHY_REF>;
> > + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
> > + <&clk IMX8MM_VIDEO_PLL1_BYPASS>,
> > + <&clk IMX8MM_VIDEO_PLL1_OUT>;
> > + assigned-clock-rates = <266000000>, <594000000>, <27000000>;
> > + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> > + phys = <&mipi_phy 0>;
> > + phy-names = "dsim";
> > + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
> > + samsung,burst-clock-frequency = <891000000>;
> > + samsung,esc-clock-frequency = <54000000>;
> > + samsung,pll-clock-frequency = <27000000>;
> > + status = "disabled";
>
>
> This 27 MHz is really IMX8MM_CLK_DSI_PHY_REF and
> samsung,burst-clock-frequency is really the DSI link clock which is
> panel/bridge specific ... but, why do we need to specify such policy in
> DT rather than have the panel/bridge drivers negotiate the best clock
> settings with DSIM bridge driver ? This should be something which should
> be implemented in the DRM subsystem, not hard-coded in DT. These ad-hoc
> samsung,*-clock-frequency properties shouldn't even be needed then.
This look confusion for me, all three clock are used it directly from
exynos. and these indeed are computing pll for this bridge and clock
control of dsim registers are updated from this out come values. No
thoughts as of now how to handle these externally and update the
internal register based on those out come values.
>
> Also, are the DSIM bindings stable now ?
Issue still lies on exynos dsi side, the final driver is not binding
properly. I'm trying to send the next version patches only for
existing exynos dsi to convert into bridge. and subsequently adding
i.mx8mm specifics. More problem for me to test it on exynos boards, i
don't have any either.
Jagan.
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [RFC PATCH v2 2/3] arm64: dts: imx8mm: Add MIPI DSI pipeline
2021-11-11 10:14 ` [RFC PATCH v2 2/3] arm64: dts: imx8mm: Add MIPI DSI pipeline Jagan Teki
2021-11-11 10:21 ` Marek Vasut
@ 2021-11-12 0:36 ` Tim Harvey
1 sibling, 0 replies; 10+ messages in thread
From: Tim Harvey @ 2021-11-12 0:36 UTC (permalink / raw)
To: Jagan Teki
Cc: Adam Ford, Fabio Estevam, Lucas Stach, Peng Fan, Shawn Guo,
Marek Vasut, Frieder Schrempf, NXP Linux Team,
Linux ARM Mailing List, DRI mailing list, linux-amarula,
Matteo Lisi, Device Tree Mailing List
On Thu, Nov 11, 2021 at 2:15 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> Add MIPI DSI pipeline for i.MX8MM.
>
> Video pipeline start from eLCDIF to MIPI DSI and respective
> Panel or Bridge on the backend side.
>
> Add support for it.
Jagan,
Thanks for your continued work on IMX8MM DSI support!
It doesn't look like you sent this to the Device Tree mainling list so
I added that to cc.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 55 +++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index caeb93313413..eddf3a467fd2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -188,6 +188,12 @@ clk_ext4: clock-ext4 {
> clock-output-names = "clk_ext4";
> };
>
> + mipi_phy: mipi-video-phy {
> + compatible = "fsl,imx8mm-mipi-video-phy";
> + syscon = <&disp_blk_ctrl>;
> + #phy-cells = <1>;
> + };
> +
> psci {
> compatible = "arm,psci-1.0";
> method = "smc";
> @@ -1085,6 +1091,55 @@ lcdif: lcdif@32e00000 {
> interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
> status = "disabled";
> +
> + port {
> + lcdif_out_dsi: endpoint {
> + remote-endpoint = <&dsi_in_lcdif>;
> + };
> + };
> + };
> +
> + dsi: dsi@32e10000 {
I wonder if this should this be 'mipi_dsi' like the CSI bindings
Adam's submitted here:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20211106155427.753197-2-aford173@gmail.com/
> + compatible = "fsl,imx8mm-mipi-dsim";
> + reg = <0x32e10000 0x400>;
> + clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> + <&clk IMX8MM_CLK_DSI_PHY_REF>;
> + clock-names = "bus_clk", "sclk_mipi";
> + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> + <&clk IMX8MM_VIDEO_PLL1_OUT>,
> + <&clk IMX8MM_CLK_DSI_PHY_REF>;
> + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
> + <&clk IMX8MM_VIDEO_PLL1_BYPASS>,
> + <&clk IMX8MM_VIDEO_PLL1_OUT>;
> + assigned-clock-rates = <266000000>, <594000000>, <27000000>;
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&mipi_phy 0>;
> + phy-names = "dsim";
> + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
> + samsung,burst-clock-frequency = <891000000>;
> + samsung,esc-clock-frequency = <54000000>;
> + samsung,pll-clock-frequency = <27000000>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
I don't think the '#address-cells' and '#size-cells' are needed here
but I defer to the dt experts!
> +
> + dsi_in_lcdif: endpoint@0 {
> + reg = <0>;
Per Adam's comment to my posting this should be just "port {" and we
can get rid of the @0 and the "reg=0"
Best regards,
Tim
> + remote-endpoint = <&lcdif_out_dsi>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> };
>
> disp_blk_ctrl: blk-ctrl@32e28000 {
> --
> 2.25.1
>
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [RFC PATCH v2 3/3] arm64: dts: imx8mm-icore: Enable LVDS panel for EDIMM2.2
2021-11-11 10:14 [RFC PATCH v2 0/3] arm64: imx8mm: Add MIPI DSI support Jagan Teki
2021-11-11 10:14 ` [RFC PATCH v2 1/3] arm64: dts: imx8mm: Add eLCDIF node support Jagan Teki
2021-11-11 10:14 ` [RFC PATCH v2 2/3] arm64: dts: imx8mm: Add MIPI DSI pipeline Jagan Teki
@ 2021-11-11 10:14 ` Jagan Teki
2021-11-12 0:10 ` [RFC PATCH v2 0/3] arm64: imx8mm: Add MIPI DSI support Tim Harvey
3 siblings, 0 replies; 10+ messages in thread
From: Jagan Teki @ 2021-11-11 10:14 UTC (permalink / raw)
To: Tim Harvey, Adam Ford, Fabio Estevam, Lucas Stach, Peng Fan,
Shawn Guo, Marek Vasut, Frieder Schrempf
Cc: NXP Linux Team, linux-arm-kernel, dri-devel, linux-amarula,
Matteo Lisi, Jagan Teki
Enable LVDS Panel for Engicam i.Core MX8MMini EDIMM2.2 board.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
.../freescale/imx8mm-icore-mx8mm-edimm2.2.dts | 85 +++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts
index a4a2ada14835..58065fee27f6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts
@@ -14,9 +14,45 @@ / {
compatible = "engicam,icore-mx8mm-edimm2.2", "engicam,icore-mx8mm",
"fsl,imx8mm";
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ pwms = <&pwm1 0 1000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ };
+
chosen {
stdout-path = &uart2;
};
+
+ panel {
+ compatible = "yes-optoelectronics,ytc700tlag-05-201c";
+ backlight = <&backlight>;
+
+ port {
+ panel_out_bridge: endpoint {
+ remote-endpoint = <&bridge_out_panel>;
+ };
+ };
+ };
+};
+
+&dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ dsi_out_bridge: endpoint {
+ remote-endpoint = <&bridge_in_dsi>;
+ };
+ };
+ };
};
&fec1 {
@@ -35,9 +71,44 @@ &i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
+
+ bridge@2c {
+ compatible = "ti,sn65dsi84";
+ reg = <0x2c>;
+ enable-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dsi_bridge_enable>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ bridge_in_dsi: endpoint {
+ remote-endpoint = <&dsi_out_bridge>;
+ data-lanes = <0 1>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ bridge_out_panel: endpoint {
+ remote-endpoint = <&panel_out_bridge>;
+ };
+ };
+ };
+ };
};
&iomuxc {
+ pinctrl_dsi_bridge_enable: dsibridgeenablegrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19
+ MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@@ -52,6 +123,12 @@ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x19
+ >;
+ };
+
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
@@ -77,6 +154,14 @@ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
};
};
+&lcdif {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
--
2.25.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [RFC PATCH v2 0/3] arm64: imx8mm: Add MIPI DSI support
2021-11-11 10:14 [RFC PATCH v2 0/3] arm64: imx8mm: Add MIPI DSI support Jagan Teki
` (2 preceding siblings ...)
2021-11-11 10:14 ` [RFC PATCH v2 3/3] arm64: dts: imx8mm-icore: Enable LVDS panel for EDIMM2.2 Jagan Teki
@ 2021-11-12 0:10 ` Tim Harvey
2021-11-12 6:47 ` Jagan Teki
3 siblings, 1 reply; 10+ messages in thread
From: Tim Harvey @ 2021-11-12 0:10 UTC (permalink / raw)
To: Jagan Teki, Marek Vasut
Cc: Adam Ford, Fabio Estevam, Lucas Stach, Peng Fan, Shawn Guo,
Frieder Schrempf, NXP Linux Team, Linux ARM Mailing List,
DRI mailing list, linux-amarula, Matteo Lisi, Michael Tretter
On Thu, Nov 11, 2021 at 2:15 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> This series support MIPI DSI on i.MX8MM.
>
> The DSIM bridge still need to work to make it compatible for
> exynos drm dsi hardware block.
>
> This series work directly on to of linux-next with recent
> dispmix-blk-ctrl changes.
>
Jagan,
Thanks - I was able to get this series working using the set of
exynos/drm patches from Michael submitted back in 2020-09-11:
https://patchwork.kernel.org/project/dri-devel/list/?series=347439&archive=both&state=*
> Tested on i.Core MX8M Mini SoM with EDIMM2.2 and CTOUCH2
> Carrier boards.
>
> Required changes:
> 1. DSIM driver
> https://patchwork.kernel.org/project/linux-arm-kernel/cover/20210704090230.26489-1-jagan@amarulasolutions.com/
This exynos/drm RFC series you posted back in July was where I
recalled the discussion about if the exynos driver could be split up
vs duplicating parts of it in a separate driver.
There were also some comments about this series. Can you address those
comments, rebase and resend?
I have not been able to get my hardware to work with this series yet
and am still debugging that (currently crashing in
samsung_dsim_host_attach)
> 2. DPHY change
> https://www.spinics.net/lists/devicetree/msg381691.html
This was originally from Marek submitted on Oct 3 2020: [PATCH] phy:
exynos-mipi-video: Add support for NXP i.MX8MM
This one seems to have been acked but never got picked up for some reason.
Marek, can you add the tags and re-submit?
> 3. Bus format fix
> https://github.com/openedev/linux/commit/6ca9781ed53ea75e26341dd57250e63794638b20
>
Jagan, can you submit this?
Best regards,
Tim
> Complete repo:
> https://github.com/openedev/linux/commits/111021-imx8mm-dsim
>
> Any inputs?
> Jagan.
>
> Jagan Teki (3):
> arm64: dts: imx8mm: Add eLCDIF node support
> arm64: dts: imx8mm: Add MIPI DSI pipeline
> arm64: dts: imx8mm-icore: Enable LVDS panel for EDIMM2.2
>
> .../freescale/imx8mm-icore-mx8mm-edimm2.2.dts | 85 +++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 74 ++++++++++++++++
> 2 files changed, 159 insertions(+)
>
> --
> 2.25.1
>
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^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [RFC PATCH v2 0/3] arm64: imx8mm: Add MIPI DSI support
2021-11-12 0:10 ` [RFC PATCH v2 0/3] arm64: imx8mm: Add MIPI DSI support Tim Harvey
@ 2021-11-12 6:47 ` Jagan Teki
0 siblings, 0 replies; 10+ messages in thread
From: Jagan Teki @ 2021-11-12 6:47 UTC (permalink / raw)
To: Tim Harvey, Laurent Pinchart, Dae
Cc: Marek Vasut, Adam Ford, Fabio Estevam, Lucas Stach, Peng Fan,
Shawn Guo, Frieder Schrempf, NXP Linux Team,
Linux ARM Mailing List, DRI mailing list, linux-amarula,
Matteo Lisi, Michael Tretter
On Fri, Nov 12, 2021 at 5:40 AM Tim Harvey <tharvey@gateworks.com> wrote:
>
> On Thu, Nov 11, 2021 at 2:15 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
> >
> > This series support MIPI DSI on i.MX8MM.
> >
> > The DSIM bridge still need to work to make it compatible for
> > exynos drm dsi hardware block.
> >
> > This series work directly on to of linux-next with recent
> > dispmix-blk-ctrl changes.
> >
>
> Jagan,
>
> Thanks - I was able to get this series working using the set of
> exynos/drm patches from Michael submitted back in 2020-09-11:
> https://patchwork.kernel.org/project/dri-devel/list/?series=347439&archive=both&state=*
>
> > Tested on i.Core MX8M Mini SoM with EDIMM2.2 and CTOUCH2
> > Carrier boards.
> >
> > Required changes:
> > 1. DSIM driver
> > https://patchwork.kernel.org/project/linux-arm-kernel/cover/20210704090230.26489-1-jagan@amarulasolutions.com/
>
> This exynos/drm RFC series you posted back in July was where I
> recalled the discussion about if the exynos driver could be split up
> vs duplicating parts of it in a separate driver.
Not sure Laurent, Inki has some discussion about this [1], looks like
they are still looking for a common driver.
>
> There were also some comments about this series. Can you address those
> comments, rebase and resend?
>
> I have not been able to get my hardware to work with this series yet
> and am still debugging that (currently crashing in
> samsung_dsim_host_attach)
I've initially tried a separate driver instead of exynos.[2]
>
> > 2. DPHY change
> > https://www.spinics.net/lists/devicetree/msg381691.html
>
> This was originally from Marek submitted on Oct 3 2020: [PATCH] phy:
> exynos-mipi-video: Add support for NXP i.MX8MM
I'm thinking this may not be required, as dphy reset can now handle
via blk-ctrl like this [3]. I have tested the reset handling via
blk-ctrl and it works for me.
>
> This one seems to have been acked but never got picked up for some reason.
>
> Marek, can you add the tags and re-submit?
>
> > 3. Bus format fix
> > https://github.com/openedev/linux/commit/6ca9781ed53ea75e26341dd57250e63794638b20
> >
>
> Jagan, can you submit this?
This is indeed not required, drm handles the bridge state via atomic
API's. I did check that as well. I will link my latest series soon.
[1] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210704090230.26489-7-jagan@amarulasolutions.com/
[2] https://patchwork.kernel.org/project/linux-arm-kernel/cover/20210621072424.111733-1-jagan@amarulasolutions.com/
[3] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20211106155427.753197-1-aford173@gmail.com/
Jagan.
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^ permalink raw reply [flat|nested] 10+ messages in thread