From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D90ABC433EF for ; Tue, 12 Apr 2022 08:43:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Q4hz5Hw5HAf9anIexAvJjaNsh8/3j4pOYR/jzCLGqiw=; b=pKuvzSwlDMcf9l 3/nwYLKqkjHy2hKkDCyJCvMn2SNNicg52YqUi2c8F3RcSBSJkrQE+htuvKDIqqe0jK/XN4w2sWDiY YGfCfqtUWwmk8Q+MA4eiuXAo9JGP3f5+565TuOu4XI5gfTqfRhs9VrEisosFrvGr4HBQriErOj3tr Addfznoc8oYF4ixXt+DWE/m+nXbVTG00u7Qtm8XxQ1TaEYNAywV1XV/fucZDF+NA/7cb8c0CWpcxX GkfO2jEOcSP2r9C0O3tdxAR5ky4HHr1HwqOgnFhCcbH2yLlzbBU3RKpeF0uTeKpZd2/JxCTACGqbW 5V1t5UXKMa0uga4oeLmw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1neC6J-00CdW5-OH; Tue, 12 Apr 2022 08:42:15 +0000 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1neC6G-00CdUH-45 for linux-arm-kernel@lists.infradead.org; Tue, 12 Apr 2022 08:42:13 +0000 Received: by mail-wm1-x32f.google.com with SMTP id h16so11496225wmd.0 for ; Tue, 12 Apr 2022 01:42:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=yXu2KEOQrQmmf/qE2DwSD4OVXGnj91SlN5UJEVCoaX4=; b=k1kvR5j2afkTP9a2drwU91TqKmsM7sIfsv9Po7Fo9CFf+2X2chyJ6aos8nW69Qua+x dtulxm7VVZ58zjw088Gd4yfWIhpOyh9Do4WHr18sRZmekJRb9q1Pjb5/bBvSZotyo8tK ChxSVd+o8g4+BMvMnn3eg7/eHa+bbZuP4NF8cmf+osIBKcO86m50ATcqrXCReKN9cLKV ewDviUG2ndzjiFPLKw1a+zAFLwH7zr4cM2BEcOuQPgTGqxaAAJ7AE6CW/ZxodqV/RAes q1hdz8du1VmpGa3BWKQkfLTb4swr6DSR/eFpQb6FgJUOZL90gN5eMKI45GZcXKJcQ1jK s1uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=yXu2KEOQrQmmf/qE2DwSD4OVXGnj91SlN5UJEVCoaX4=; b=nIZ10eQr5Ewdzecxo2mdgxav2KzOy7SEm2F7kuovHaccqMNaq3e8y1wTmLebtA+0ob 52Q3FAySCX8QEAziqiptUJWE9FddOdX+qQqJrzDikmmFfdrGs45EIGCEu6iwqJKenAZH C1i4ooqEide+7vlJREN3PKauiSziar2PpHyHDkGYAKfoL/cRg1QsCujAFcJPJqwJVVyh ZP46VQt0OgjgjWfhMOZRihLfCtMNy93w2LgDvmlgzNA5QrmAu/KYwrVRhVBv8gUjXhtt ez4BKNhUHNKdmW9jo85vDBs76/CIiSxIhCHLzTwZMlu6ZbASTW4ckoTGP8nUeZBVNdET D4Rw== X-Gm-Message-State: AOAM5312SArwJrGWU5Agt8kAN1fuh3riRuZUEWqzaVZmdv3j4Oktpo5p 3THkB703fR8eLi92ahgcsuAr5kY7Im4+/Yp8x0Xv9XBcSt+9GQ== X-Google-Smtp-Source: ABdhPJxYhabPb6gGJkUG38B7sezAvlwxgHjf+aikWna8H1DYx5r56v7GISPk5WOMepJy5u8DYnaVRlDm8q25l9BH0Mk= X-Received: by 2002:a7b:cbc2:0:b0:388:faec:2036 with SMTP id n2-20020a7bcbc2000000b00388faec2036mr3090378wmi.190.1649752930571; Tue, 12 Apr 2022 01:42:10 -0700 (PDT) MIME-Version: 1.0 References: <20220304171913.2292458-1-james.clark@arm.com> <20220304171913.2292458-6-james.clark@arm.com> In-Reply-To: <20220304171913.2292458-6-james.clark@arm.com> From: Mike Leach Date: Tue, 12 Apr 2022 09:41:59 +0100 Message-ID: Subject: Re: [PATCH v3 05/15] coresight: etm4x: Cleanup TRCIDR5 register accesses To: James Clark Cc: suzuki.poulose@arm.com, coresight@lists.linaro.org, Anshuman.Khandual@arm.com, mathieu.poirier@linaro.org, leo.yan@linaro.com, Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220412_014212_181936_D4492A4A X-CRM114-Status: GOOD ( 19.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 4 Mar 2022 at 17:19, James Clark wrote: > > This is a no-op change for style and consistency and has no effect on > the binary output by the compiler. In sysreg.h fields are defined as > the register name followed by the field name and then _MASK. This > allows for grepping for fields by name rather than using magic numbers. > > Signed-off-by: James Clark > --- > .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++------------ > drivers/hwtracing/coresight/coresight-etm4x.h | 7 +++++++ > 2 files changed, 13 insertions(+), 12 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index c52ab7f29f41..3f4263117570 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -1188,26 +1188,20 @@ static void etm4_init_arch_data(void *info) > > etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); > /* NUMEXTIN, bits[8:0] number of external inputs implemented */ > - drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8); > + drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5); > /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ > - drvdata->trcid_size = BMVAL(etmidr5, 16, 21); > + drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); > /* ATBTRIG, bit[22] implementation can support ATB triggers? */ > - if (BMVAL(etmidr5, 22, 22)) > - drvdata->atbtrig = true; > - else > - drvdata->atbtrig = false; > + drvdata->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG); > /* > * LPOVERRIDE, bit[23] implementation supports > * low-power state override > */ > - if (BMVAL(etmidr5, 23, 23) && (!drvdata->skip_power_up)) > - drvdata->lpoverride = true; > - else > - drvdata->lpoverride = false; > + drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up); > /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */ > - drvdata->nrseqstate = BMVAL(etmidr5, 25, 27); > + drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5); > /* NUMCNTR, bits[30:28] number of counters available for tracing */ > - drvdata->nr_cntr = BMVAL(etmidr5, 28, 30); > + drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5); > etm4_cs_lock(drvdata, csa); > cpu_detect_trace_filtering(drvdata); > } > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index c9c5fd655196..3b604cde668b 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -165,6 +165,13 @@ > #define TRCIDR4_NUMCIDC_MASK GENMASK(27, 24) > #define TRCIDR4_NUMVMIDC_MASK GENMASK(31, 28) > > +#define TRCIDR5_NUMEXTIN_MASK GENMASK(8, 0) > +#define TRCIDR5_TRACEIDSIZE_MASK GENMASK(21, 16) > +#define TRCIDR5_ATBTRIG BIT(22) > +#define TRCIDR5_LPOVERRIDE BIT(23) > +#define TRCIDR5_NUMSEQSTATE_MASK GENMASK(27, 25) > +#define TRCIDR5_NUMCNTR_MASK GENMASK(30, 28) > + > /* > * System instructions to access ETM registers. > * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions > -- > 2.28.0 > Reviewed-by: Mike Leach -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel