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From: bhaskarbudiredla@gmail.com (Bhaskara rao Budiredla)
To: linux-arm-kernel@lists.infradead.org
Subject: Programming the boundary between Inner and Outer caches on ARM architecture
Date: Fri, 24 Apr 2015 07:12:10 +0530	[thread overview]
Message-ID: <CAJWVF-xUx_raxFMQ7Un8utOo113D9j42Nuo8TWFrePABDvFELw@mail.gmail.com> (raw)
In-Reply-To: <20150423095349.GB12732@n2100.arm.linux.org.uk>

Thanks Russell for the direction. Then the bug is somewhere within the
assembly source file head.s and must be specific to my local code
base. Got it!!

Thanks,
Bhaskara

On Thu, Apr 23, 2015 at 3:23 PM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Thu, Apr 23, 2015 at 12:12:34AM +0530, Bhaskara rao Budiredla wrote:
>> I am not sure why those are different. During Linux kernel
>> booting, I wrote a function to read the contents of NMRR in
>> build_mem_type_table( ) function. May be I need to sync up with boot
>> loader folks to check why those are set up with different cacheable
>> attributes. This difference was the reason to start this thread.
>
> NMRR is set by the Linux kernel.  Anything that the boot loader does is
> overwritten during the very early kernel boot.
>
> --
> FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up
> according to speedtest.net.



-- 
.

      reply	other threads:[~2015-04-24  1:42 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-09 16:15 Programming the boundary between Inner and Outer caches on ARM architecture Bhaskara rao Budiredla
2015-04-20 10:01 ` Catalin Marinas
2015-04-20 18:53   ` Bhaskara rao Budiredla
2015-04-21 11:00     ` Catalin Marinas
2015-04-22 18:42       ` Bhaskara rao Budiredla
2015-04-22 19:09         ` Bhaskara rao Budiredla
2015-04-24 15:37           ` Catalin Marinas
2015-04-23  9:53         ` Russell King - ARM Linux
2015-04-24  1:42           ` Bhaskara rao Budiredla [this message]

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