[PATCH 0/3]ARM: Exynos5 : Add Power domain device tree support and fix for hardware issue

[PATCH 0/3]ARM: Exynos5 : Add Power domain device tree support and fix for hardware issue

[Prasanna Kumar]

From: Prasanna Kumar <prasanna.ps@samsung.com>

Hello all,

This patch set is for "for-next" branch.

In this patch set, the first patch adds device tree support for
G-Scaler and MFC power domains of Exynos5. 

The second patch enables power domain support for exynos5 in Kconfig

The last patch provides a software fix for hardware issue found in exynos5
while powergating the power domains.

Prasanna Kumar (3):
  ARM: dts: exynos5: Set up power domain for MFC and G-scaler
  arm: exynos5: Enable PM generic domain support in Kconfig
  ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

 arch/arm/boot/dts/exynos5250.dtsi |   15 +++++++++++++++
 arch/arm/mach-exynos/Kconfig      |    1 +
 arch/arm/mach-exynos/pm_domains.c |   27 +++++++++++++++++++++++++++
 3 files changed, 43 insertions(+), 0 deletions(-)

[PATCH 1/3] ARM: dts: exynos5: Set up power domain for MFC and G-scaler

[Prasanna Kumar]

From: Prasanna Kumar <prasanna.ps@samsung.com>

This patch adds device tree nodes for MFC and G-scaler power domains of exynos5.
It binds these power-domain nodes to repsective device tree nodes.

Signed-off-by: Prasanna Kumar <prasanna.ps@samsung.com>
---
 arch/arm/boot/dts/exynos5250.dtsi |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 8f46227..23f9bf1 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -83,6 +83,7 @@
 		compatible = "samsung,mfc-v6";
 		reg = <0x11000000 0x10000>;
 		interrupts = <0 96 0>;
+		samsung,power-domain = <&pd_mfc>;
 	};
 
 	rtc {
@@ -578,28 +579,42 @@
 		};
 	};
 
+	pd_gsc: gsc-power-domain at 0x10044000 {
+		compatible = "samsung,exynos4210-pd";
+		reg = <0x10044000 0x20>;
+	};
+
+	pd_mfc: mfc-power-domain at 0x10044040 {
+		compatible = "samsung,exynos4210-pd";
+		reg = <0x10044040 0x20>;
+	};
+
 	gsc_0:  gsc at 0x13e00000 {
 		compatible = "samsung,exynos5-gsc";
 		reg = <0x13e00000 0x1000>;
 		interrupts = <0 85 0>;
+		samsung,power-domain = <&pd_gsc>;
 	};
 
 	gsc_1:  gsc at 0x13e10000 {
 		compatible = "samsung,exynos5-gsc";
 		reg = <0x13e10000 0x1000>;
 		interrupts = <0 86 0>;
+		samsung,power-domain = <&pd_gsc>;
 	};
 
 	gsc_2:  gsc at 0x13e20000 {
 		compatible = "samsung,exynos5-gsc";
 		reg = <0x13e20000 0x1000>;
 		interrupts = <0 87 0>;
+		samsung,power-domain = <&pd_gsc>;
 	};
 
 	gsc_3:  gsc at 0x13e30000 {
 		compatible = "samsung,exynos5-gsc";
 		reg = <0x13e30000 0x1000>;
 		interrupts = <0 88 0>;
+		samsung,power-domain = <&pd_gsc>;
 	};
 
 	hdmi {
-- 
1.7.0.4

[PATCH 2/3] arm: exynos5: Enable PM generic domain support in Kconfig

[Prasanna Kumar]

From: Prasanna Kumar <prasanna.ps@samsung.com>

This patch adds support to enable PM generic domains
under Exynos5 family

Signed-off-by: Prasanna Kumar <prasanna.ps@samsung.com>
---
 arch/arm/mach-exynos/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 945ce49..c07a29c 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -63,6 +63,7 @@ config SOC_EXYNOS5250
 	depends on ARCH_EXYNOS5
 	select S5P_PM if PM
 	select S5P_SLEEP if PM
+	select PM_GENERIC_DOMAINS if PM
 	select S5P_DEV_MFC
 	select SAMSUNG_DMADEV
 	help
-- 
1.7.0.4

[PATCH 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

[Prasanna Kumar]

From: Prasanna Kumar <prasanna.ps@samsung.com>

This patch adds a software workaround to the hardware
problem found in exynos5 while powergating.

It is observed that CLK_TOP_SRC3 register gets modified if
the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
set to XXTI which results in the device running very slow .
A big drop in performance is noticed whilerunning the video.
This issue also occurs while powergating MFC.

The value of clock source register is restored once the powergating
operation is completed.

Signed-off-by: Prasanna Kumar <prasanna.ps@samsung.com>
---
 arch/arm/mach-exynos/pm_domains.c |   27 +++++++++++++++++++++++++++
 1 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 9f1351d..955cbe3 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -24,6 +24,8 @@
 
 #include <mach/regs-pmu.h>
 #include <plat/devs.h>
+#include <mach/regs-clock.h>
+#include <plat/cpu.h>
 
 /*
  * Exynos specific wrapper around the generic power domain
@@ -41,6 +43,7 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
 	void __iomem *base;
 	u32 timeout, pwr;
 	char *op;
+	u32 tmp = 0;
 
 	pd = container_of(domain, struct exynos_pm_domain, pd);
 	base = pd->base;
@@ -48,6 +51,23 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
 	pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0;
 	__raw_writel(pwr, base);
 
+	/*
+	 *It is found that the CLK SRC register in exynos5
+	 *gets modified when power domain of gsc/mfc/isp/disp1
+	 *is powered off.This happens only after the system is
+	 *suspended and resumed and not before that.
+	 *The following fix adresses this hardware issue.
+	 *It saves the value of clock source register and
+	 *resores it later
+	 */
+
+	if (soc_is_exynos5250()) {
+		if (!power_on) {
+			/* save clock source register */
+			tmp = __raw_readl(EXYNOS5_CLKSRC_TOP3);
+		}
+	}
+
 	/* Wait max 1ms */
 	timeout = 10;
 
@@ -61,6 +81,13 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
 		cpu_relax();
 		usleep_range(80, 100);
 	}
+
+	if (soc_is_exynos5250()) {
+		if (!power_on) {
+			/* restore clock source register */
+			__raw_writel(tmp, EXYNOS5_CLKSRC_TOP3);
+		}
+	}
 	return 0;
 }
 
-- 
1.7.0.4

[PATCH 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

[Thomas Abraham]

On 27 November 2012 17:52, Prasanna Kumar <prasanna.ps@samsung.com> wrote:
> From: Prasanna Kumar <prasanna.ps@samsung.com>
>
> This patch adds a software workaround to the hardware
> problem found in exynos5 while powergating.
>
> It is observed that CLK_TOP_SRC3 register gets modified if
> the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
> set to XXTI which results in the device running very slow .
> A big drop in performance is noticed whilerunning the video.
> This issue also occurs while powergating MFC.
>
> The value of clock source register is restored once the powergating
> operation is completed.
>
> Signed-off-by: Prasanna Kumar <prasanna.ps@samsung.com>
> ---
>  arch/arm/mach-exynos/pm_domains.c |   27 +++++++++++++++++++++++++++
>  1 files changed, 27 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
> index 9f1351d..955cbe3 100644
> --- a/arch/arm/mach-exynos/pm_domains.c
> +++ b/arch/arm/mach-exynos/pm_domains.c
> @@ -24,6 +24,8 @@
>
>  #include <mach/regs-pmu.h>
>  #include <plat/devs.h>
> +#include <mach/regs-clock.h>
> +#include <plat/cpu.h>
>
>  /*
>   * Exynos specific wrapper around the generic power domain
> @@ -41,6 +43,7 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
>         void __iomem *base;
>         u32 timeout, pwr;
>         char *op;
> +       u32 tmp = 0;
>
>         pd = container_of(domain, struct exynos_pm_domain, pd);
>         base = pd->base;
> @@ -48,6 +51,23 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
>         pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0;
>         __raw_writel(pwr, base);
>
> +       /*
> +        *It is found that the CLK SRC register in exynos5
> +        *gets modified when power domain of gsc/mfc/isp/disp1
> +        *is powered off.This happens only after the system is
> +        *suspended and resumed and not before that.
> +        *The following fix adresses this hardware issue.
> +        *It saves the value of clock source register and
> +        *resores it later
> +        */
> +
> +       if (soc_is_exynos5250()) {
> +               if (!power_on) {
> +                       /* save clock source register */
> +                       tmp = __raw_readl(EXYNOS5_CLKSRC_TOP3);
> +               }
> +       }

Does the value of EXYNOS5_CLKSRC_TOP3 register change as soon as the
G-Scaler/MFC devices are power gated?

- If yes, the value of CLKSRC register should be saved before the
power domain register is programmed.

- If not, as mentioned in the comment, if this issue occurs during a
suspend-resume cycle, the value of this register can be saved and
restored in the clock driver code itself.

The other thing that needs to be relooked into here is the use of
EXYNOS5_CLKSRC_TOP3 register address. Currently, the clock registers
are statically io-remapped. With the upcoming migration to common
clock for Exynos5, the clock registers will not be statically
io-remapped but instead remapped during clock initialization. So the
use of EXYNOS5_CLKSRC_TOP3 will not hold and so we need to relook into
this.

> +
>         /* Wait max 1ms */
>         timeout = 10;
>
> @@ -61,6 +81,13 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
>                 cpu_relax();
>                 usleep_range(80, 100);
>         }
> +
> +       if (soc_is_exynos5250()) {

We could use the of_machine_is_compatible api here instead of
soc_is_exynos5250() macro.

> +               if (!power_on) {
> +                       /* restore clock source register */
> +                       __raw_writel(tmp, EXYNOS5_CLKSRC_TOP3);
> +               }
> +       }
>         return 0;
>  }


Thanks,
Thomas.

[PATCH 1/3] ARM: dts: exynos5: Set up power domain for MFC and G-scaler

[Thomas Abraham]

On 27 November 2012 17:52, Prasanna Kumar <prasanna.ps@samsung.com> wrote:
> From: Prasanna Kumar <prasanna.ps@samsung.com>
>
> This patch adds device tree nodes for MFC and G-scaler power domains of exynos5.
> It binds these power-domain nodes to repsective device tree nodes.
>
> Signed-off-by: Prasanna Kumar <prasanna.ps@samsung.com>

Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>

> ---
>  arch/arm/boot/dts/exynos5250.dtsi |   15 +++++++++++++++
>  1 files changed, 15 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index 8f46227..23f9bf1 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -83,6 +83,7 @@
>                 compatible = "samsung,mfc-v6";
>                 reg = <0x11000000 0x10000>;
>                 interrupts = <0 96 0>;
> +               samsung,power-domain = <&pd_mfc>;
>         };
>
>         rtc {
> @@ -578,28 +579,42 @@
>                 };
>         };
>
> +       pd_gsc: gsc-power-domain at 0x10044000 {
> +               compatible = "samsung,exynos4210-pd";
> +               reg = <0x10044000 0x20>;
> +       };
> +
> +       pd_mfc: mfc-power-domain at 0x10044040 {
> +               compatible = "samsung,exynos4210-pd";
> +               reg = <0x10044040 0x20>;
> +       };
> +
>         gsc_0:  gsc at 0x13e00000 {
>                 compatible = "samsung,exynos5-gsc";
>                 reg = <0x13e00000 0x1000>;
>                 interrupts = <0 85 0>;
> +               samsung,power-domain = <&pd_gsc>;
>         };
>
>         gsc_1:  gsc at 0x13e10000 {
>                 compatible = "samsung,exynos5-gsc";
>                 reg = <0x13e10000 0x1000>;
>                 interrupts = <0 86 0>;
> +               samsung,power-domain = <&pd_gsc>;
>         };
>
>         gsc_2:  gsc at 0x13e20000 {
>                 compatible = "samsung,exynos5-gsc";
>                 reg = <0x13e20000 0x1000>;
>                 interrupts = <0 87 0>;
> +               samsung,power-domain = <&pd_gsc>;
>         };
>
>         gsc_3:  gsc at 0x13e30000 {
>                 compatible = "samsung,exynos5-gsc";
>                 reg = <0x13e30000 0x1000>;
>                 interrupts = <0 88 0>;
> +               samsung,power-domain = <&pd_gsc>;
>         };
>
>         hdmi {
> --
> 1.7.0.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
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[PATCH 2/3] arm: exynos5: Enable PM generic domain support in Kconfig

[Thomas Abraham]

On 27 November 2012 17:52, Prasanna Kumar <prasanna.ps@samsung.com> wrote:
> From: Prasanna Kumar <prasanna.ps@samsung.com>
>
> This patch adds support to enable PM generic domains
> under Exynos5 family
>
> Signed-off-by: Prasanna Kumar <prasanna.ps@samsung.com>

Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>

> ---
>  arch/arm/mach-exynos/Kconfig |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index 945ce49..c07a29c 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -63,6 +63,7 @@ config SOC_EXYNOS5250
>         depends on ARCH_EXYNOS5
>         select S5P_PM if PM
>         select S5P_SLEEP if PM
> +       select PM_GENERIC_DOMAINS if PM
>         select S5P_DEV_MFC
>         select SAMSUNG_DMADEV
>         help
> --
> 1.7.0.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

[Prasanna Kumar]

Hi Thomas,

Thanks for the comments.Please find my reply inline.

On Tue, Dec 4, 2012 at 2:29 PM, Thomas Abraham
<thomas.abraham@linaro.org> wrote:
>
> On 27 November 2012 17:52, Prasanna Kumar <prasanna.ps@samsung.com> wrote:
> > From: Prasanna Kumar <prasanna.ps@samsung.com>
> >
> > This patch adds a software workaround to the hardware
> > problem found in exynos5 while powergating.
> >
> > It is observed that CLK_TOP_SRC3 register gets modified if
> > the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
> > set to XXTI which results in the device running very slow .
> > A big drop in performance is noticed whilerunning the video.
> > This issue also occurs while powergating MFC.
> >
> > The value of clock source register is restored once the powergating
> > operation is completed.
> >
> > Signed-off-by: Prasanna Kumar <prasanna.ps@samsung.com>
> > ---
> >  arch/arm/mach-exynos/pm_domains.c |   27 +++++++++++++++++++++++++++
> >  1 files changed, 27 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos/pm_domains.c
> > b/arch/arm/mach-exynos/pm_domains.c
> > index 9f1351d..955cbe3 100644
> > --- a/arch/arm/mach-exynos/pm_domains.c
> > +++ b/arch/arm/mach-exynos/pm_domains.c
> > @@ -48,6 +51,23 @@ static int exynos_pd_power(struct generic_pm_domain
> > *domain, bool power_on)
> >         pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0;
> >         __raw_writel(pwr, base);
> >
> > +       /*
> > +        *It is found that the CLK SRC register in exynos5
> > +        *gets modified when power domain of gsc/mfc/isp/disp1
> > +        *is powered off.This happens only after the system is
> > +        *suspended and resumed and not before that.
> > +        *The following fix adresses this hardware issue.
> > +        *It saves the value of clock source register and
> > +        *resores it later
> > +        */
> > +
> > +       if (soc_is_exynos5250()) {
> > +               if (!power_on) {
> > +                       /* save clock source register */
> > +                       tmp = __raw_readl(EXYNOS5_CLKSRC_TOP3);
> > +               }
> > +       }
>
> Does the value of EXYNOS5_CLKSRC_TOP3 register change as soon as the
> G-Scaler/MFC devices are power gated?
>
> - If yes, the value of CLKSRC register should be saved before the
> power domain register is programmed.
>
> - If not, as mentioned in the comment, if this issue occurs during a
> suspend-resume cycle, the value of this register can be saved and
> restored in the clock driver code itself.
>
During a normal power gating sequence, this problem is not seen
But Once the suspend-resume cycle is done,  if we try to turn on or
turn off domain,
this issue occurs.

I agree that CLKSRC register should be saved
before the power domain register is programmed.

Saving of CLKSRC_TOP3 register is already being done in clock driver
code.i.e in exynos5_clock_save[]. But the problem remains. So i feel
an exclusive saving of the register in pm_domain driver is required.

Kindly let me know your opinion

> The other thing that needs to be relooked into here is the use of
> EXYNOS5_CLKSRC_TOP3 register address. Currently, the clock registers
> are statically io-remapped. With the upcoming migration to common
> clock for Exynos5, the clock registers will not be statically
> io-remapped but instead remapped during clock initialization. So the
> use of EXYNOS5_CLKSRC_TOP3 will not hold and so we need to relook into
> this.

Yes , we can look into this, once the clock migration happens for Exynos5
Until then, can it be used as statically io-remapped ?


> > @@ -61,6 +81,13 @@ static int exynos_pd_power(struct generic_pm_domain
> > *domain, bool power_on)
> >                 cpu_relax();
> >                 usleep_range(80, 100);
> >         }
> > +
> > +       if (soc_is_exynos5250()) {
>
> We could use the of_machine_is_compatible api here instead of
> soc_is_exynos5250() macro.
>

Yes, of_machine_is_compatible function will be used
instead of soc_is_exynos5250()


> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel




--
Thanks
Prasanna Kumar

[PATCH v2 0/3] ARM: Exynos5 : Add Power domain device tree support and fix for hardware issue

[Prasanna Kumar]

Hello,
This patch set is for "for-next" branch.

Changes since v1:
[exynos5250.dtsi]
Added power domain support for MAU and ISP power domains in exynos5 dts
[pm_domains.c]
CLKSRC register is saved before PMU register is programmed
Replaced soc_is_exynos5250 with  of_machine_is_compatible 

Prasanna Kumar (3):
  ARM: dts: exynos5: Set up power domain for MFC,G-scaler,MAU and ISP
  arm: exynos5: Enable PM generic domain support in Kconfig
  ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

 arch/arm/boot/dts/exynos5250.dtsi |   25 +++++++++++++++++++++++++
 arch/arm/mach-exynos/Kconfig      |    1 +
 arch/arm/mach-exynos/pm_domains.c |   27 +++++++++++++++++++++++++++
 3 files changed, 53 insertions(+), 0 deletions(-)

[PATCH v2 1/3] ARM: dts: exynos5: Set up power domain for MFC,G-scaler,MAU and ISP

[Prasanna Kumar]

This patch adds device tree nodes for MFC,G-scaler,MAU and ISP power domains
of exynos5.It binds these power-domain nodes to repsective device tree nodes.

Signed-off-by: Prasanna Kumar <prasanna.ps@samsung.com>
---
 arch/arm/boot/dts/exynos5250.dtsi |   25 +++++++++++++++++++++++++
 1 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 581e57a..71a37bd 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -83,6 +83,7 @@
 		compatible = "samsung,mfc-v6";
 		reg = <0x11000000 0x10000>;
 		interrupts = <0 96 0>;
+		samsung,power-domain = <&pd_mfc>;
 	};
 
 	rtc {
@@ -283,6 +284,7 @@
 		samsung,supports-rstclr;
 		samsung,supports-secdai;
 		samsung,idma-addr = <0x03000000>;
+		samsung,power-domain = <&pd_mau>;
 	};
 
 	i2s_1: i2s at 12D60000 {
@@ -578,28 +580,51 @@
 		};
 	};
 
+	pd_gsc: gsc-power-domain at 0x10044000 {
+		compatible = "samsung,exynos4210-pd";
+		reg = <0x10044000 0x20>;
+	};
+
+	pd_isp: isp-power-domain at 0x10044020 {
+		compatible = "samsung,exynos4210-pd";
+		reg = <0x10044020 0x20>;
+		};
+
+	pd_mfc: mfc-power-domain at 0x10044040 {
+		compatible = "samsung,exynos4210-pd";
+		reg = <0x10044040 0x20>;
+	};
+
+	pd_mau: mau-power-domain at 0x100440C0 {
+		compatible = "samsung,exynos4210-pd";
+		reg = <0x100440C0 0x20>;
+	};
 	gsc_0:  gsc at 0x13e00000 {
 		compatible = "samsung,exynos5-gsc";
 		reg = <0x13e00000 0x1000>;
 		interrupts = <0 85 0>;
+		samsung,power-domain = <&pd_gsc>;
 	};
 
 	gsc_1:  gsc at 0x13e10000 {
 		compatible = "samsung,exynos5-gsc";
 		reg = <0x13e10000 0x1000>;
 		interrupts = <0 86 0>;
+		samsung,power-domain = <&pd_gsc>;
 	};
 
 	gsc_2:  gsc at 0x13e20000 {
 		compatible = "samsung,exynos5-gsc";
 		reg = <0x13e20000 0x1000>;
 		interrupts = <0 87 0>;
+		samsung,power-domain = <&pd_gsc>;
 	};
 
 	gsc_3:  gsc at 0x13e30000 {
 		compatible = "samsung,exynos5-gsc";
 		reg = <0x13e30000 0x1000>;
 		interrupts = <0 88 0>;
+		samsung,power-domain = <&pd_gsc>;
 	};
 
 	hdmi {
-- 
1.7.0.4

[PATCH v2 2/3] arm: exynos5: Enable PM generic domain support in Kconfig

[Prasanna Kumar]

This patch adds support to enable PM generic domains
under Exynos5 family

Signed-off-by: Prasanna Kumar <prasanna.ps@samsung.com>
---
 This patch is same as v1
 arch/arm/mach-exynos/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 91d5b6f..1c77f17 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -63,6 +63,7 @@ config SOC_EXYNOS5250
 	depends on ARCH_EXYNOS5
 	select S5P_PM if PM
 	select S5P_SLEEP if PM
+	select PM_GENERIC_DOMAINS if PM
 	select S5P_DEV_MFC
 	select SAMSUNG_DMADEV
 	help
-- 
1.7.0.4

[PATCH v2 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

[Prasanna Kumar]

This patch adds a software workaround to the hardware
problem found in exynos5 while powergating.

It is observed that CLK_TOP_SRC3 register gets modified if
the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
set to XXTI which results in the device running very slow .
A big drop in performance is noticed whilerunning the video.
This issue also occurs while powergating MFC.

The value of clock source register is restored once the powergating
operation is completed.

Signed-off-by: Prasanna Kumar <prasanna.ps@samsung.com>
---
 arch/arm/mach-exynos/pm_domains.c |   27 +++++++++++++++++++++++++++
 1 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 9f1351d..bd8a41e 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -24,6 +24,8 @@
 
 #include <mach/regs-pmu.h>
 #include <plat/devs.h>
+#include <mach/regs-clock.h>
+#include <plat/cpu.h>
 
 /*
  * Exynos specific wrapper around the generic power domain
@@ -41,6 +43,24 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
 	void __iomem *base;
 	u32 timeout, pwr;
 	char *op;
+	u32 tmp = 0;
+
+	/*
+	 *It is found that the CLK SRC register in exynos5
+	 *gets modified when power domain of gsc/mfc/isp/disp1
+	 *is powered off.This happens only after the system is
+	 *suspended and resumed and not before that.
+	 *The following fix adresses this hardware issue.
+	 *It saves the value of clock source register and
+	 *resores it later
+	 */
+
+	if (of_machine_is_compatible("samsung,exynos5250")) {
+		if (!power_on) {
+			/* save clock source register */
+			tmp = __raw_readl(EXYNOS5_CLKSRC_TOP3);
+		}
+	}
 
 	pd = container_of(domain, struct exynos_pm_domain, pd);
 	base = pd->base;
@@ -61,6 +81,13 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
 		cpu_relax();
 		usleep_range(80, 100);
 	}
+
+	if (of_machine_is_compatible("samsung,exynos5250")) {
+		if (!power_on) {
+			/* restore clock source register */
+			__raw_writel(tmp, EXYNOS5_CLKSRC_TOP3);
+		}
+	}
 	return 0;
 }
 
-- 
1.7.0.4

[PATCH v2 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

[tomasz.figa at gmail.com]

Hi Prasanna,

On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote:
> This patch adds a software workaround to the hardware
> problem found in exynos5 while powergating.
> 
> It is observed that CLK_TOP_SRC3 register gets modified if
> the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
> set to XXTI which results in the device running very slow .
> A big drop in performance is noticed whilerunning the video.
> This issue also occurs while powergating MFC.
> 
> The value of clock source register is restored once the powergating
> operation is completed.

Is the problem really related to power gating at all? From what you 
described in comment in the code, it seems like it's a problem with 
suspend/resume, not power gating, so it should be rather saved on suspend 
and restored on resume. Please recheck clock save/restore part of power 
management code.

Altering clock configuration registers from power domain code looks really 
ugly...

Best regards,
Tomasz Figa

[PATCH v2 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

[jonghwan Choi]

Hi~

This code should be changed.

I insert  this code (save/restore clock source register - CLK_SRC_TOP3)
temporary.

But we removed this code. And we use another  method to fix it.

I think this is not right way.

Thanks.



On Fri, Dec 21, 2012 at 6:06 AM, <tomasz.figa@gmail.com> wrote:

> Hi Prasanna,
>
> On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote:
> > This patch adds a software workaround to the hardware
> > problem found in exynos5 while powergating.
> >
> > It is observed that CLK_TOP_SRC3 register gets modified if
> > the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
> > set to XXTI which results in the device running very slow .
> > A big drop in performance is noticed whilerunning the video.
> > This issue also occurs while powergating MFC.
> >
> > The value of clock source register is restored once the powergating
> > operation is completed.
>
> Is the problem really related to power gating at all? From what you
> described in comment in the code, it seems like it's a problem with
> suspend/resume, not power gating, so it should be rather saved on suspend
> and restored on resume. Please recheck clock save/restore part of power
> management code.
>
> Altering clock configuration registers from power domain code looks really
> ugly...
>
> Best regards,
> Tomasz Figa
>
> --
> To unsubscribe from this list: send the line "unsubscribe
> linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
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[PATCH v2 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

[Prasanna Kumar]

Hi tomasz,

On Fri, Dec 21, 2012 at 2:36 AM,  <tomasz.figa@gmail.com> wrote:
> Hi Prasanna,
>
> On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote:
>> This patch adds a software workaround to the hardware
>> problem found in exynos5 while powergating.
>>
>> It is observed that CLK_TOP_SRC3 register gets modified if
>> the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
>> set to XXTI which results in the device running very slow .
>> A big drop in performance is noticed whilerunning the video.
>> This issue also occurs while powergating MFC.
>>
>> The value of clock source register is restored once the powergating
>> operation is completed.
>
> Is the problem really related to power gating at all? From what you
> described in comment in the code, it seems like it's a problem with
> suspend/resume, not power gating, so it should be rather saved on suspend
> and restored on resume. Please recheck clock save/restore part of power
> management code.

The problem is only seen in following sequence.
1. Suspend and then Resume the system
2. Power Gating ( On-> Off ) of the associated power domain ( Gscaler , MFC ...)

I rechecked clock save/restore part of power
management code.The register is already being saved clock save/restore
part of power
management code. ( exynos5_clock_save. in clock-exynos5.c).

I hope you have understood the situation here.

> Best regards,
> Tomasz Figa
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



-- 
Thanks
Prasanna Kumar

[PATCH v2 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

[Prasanna Kumar]

Hi Choi,

The method "Save/restore clock source register - CLK_SRC_TOP3" was
suggested as well as preferred by our hardware team.

Would it be possible to give more information on this  alternate method ?


On Fri, Dec 21, 2012 at 7:07 AM, jonghwan Choi <jhbird.choi@gmail.com> wrote:
> Hi~
>
> This code should be changed.
>
> I insert  this code (save/restore clock source register - CLK_SRC_TOP3)
> temporary.
>
> But we removed this code. And we use another  method to fix it.
>
> I think this is not right way.
>
> Thanks.
>
>
>
> On Fri, Dec 21, 2012 at 6:06 AM, <tomasz.figa@gmail.com> wrote:
>>
>> Hi Prasanna,
>>
>> On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote:
>> > This patch adds a software workaround to the hardware
>> > problem found in exynos5 while powergating.
>> >
>> > It is observed that CLK_TOP_SRC3 register gets modified if
>> > the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
>> > set to XXTI which results in the device running very slow .
>> > A big drop in performance is noticed whilerunning the video.
>> > This issue also occurs while powergating MFC.
>> >
>> > The value of clock source register is restored once the powergating
>> > operation is completed.
>>
>> Is the problem really related to power gating at all? From what you
>> described in comment in the code, it seems like it's a problem with
>> suspend/resume, not power gating, so it should be rather saved on suspend
>> and restored on resume. Please recheck clock save/restore part of power
>> management code.
>>
>> Altering clock configuration registers from power domain code looks really
>> ugly...
>>
>> Best regards,
>> Tomasz Figa
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe
>> linux-samsung-soc" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



-- 
Thanks
Prasanna Kumar

[PATCH v2 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

[Prasanna Kumar]

Hi Choi,

On Mon, Dec 24, 2012 at 9:56 AM, Prasanna Kumar
<prasannapadubidri@gmail.com> wrote:
> Hi Choi,
>
> The method "Save/restore clock source register - CLK_SRC_TOP3" was
> suggested as well as preferred by our hardware team.
>
> Would it be possible to give more information on this  alternate method ?
>
   I just wanted to be more clear on the last sentence of my previous email.
   Here alternate method means, the method you have used to fix the issue.
   Kindly share information on that.
   --
Thanks

>
> On Fri, Dec 21, 2012 at 7:07 AM, jonghwan Choi <jhbird.choi@gmail.com> wrote:
>> Hi~
>>
>> This code should be changed.
>>
>> I insert  this code (save/restore clock source register - CLK_SRC_TOP3)
>> temporary.
>>
>> But we removed this code. And we use another  method to fix it.
>>
>> I think this is not right way.
>>
>> Thanks.
>>
>>
>>
>> On Fri, Dec 21, 2012 at 6:06 AM, <tomasz.figa@gmail.com> wrote:
>>>
>>> Hi Prasanna,
>>>
>>> On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote:
>>> > This patch adds a software workaround to the hardware
>>> > problem found in exynos5 while powergating.
>>> >
>>> > It is observed that CLK_TOP_SRC3 register gets modified if
>>> > the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
>>> > set to XXTI which results in the device running very slow .
>>> > A big drop in performance is noticed whilerunning the video.
>>> > This issue also occurs while powergating MFC.
>>> >
>>> > The value of clock source register is restored once the powergating
>>> > operation is completed.
>>>
>>> Is the problem really related to power gating at all? From what you
>>> described in comment in the code, it seems like it's a problem with
>>> suspend/resume, not power gating, so it should be rather saved on suspend
>>> and restored on resume. Please recheck clock save/restore part of power
>>> management code.
>>>
>>> Altering clock configuration registers from power domain code looks really
>>> ugly...
>>>
>>> Best regards,
>>> Tomasz Figa
>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe
>>> linux-samsung-soc" in
>>> the body of a message to majordomo at vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>
>
>
> --
> Thanks
> Prasanna Kumar

[PATCH v2 1/3] ARM: dts: exynos5: Set up power domain for MFC,G-scaler,MAU and ISP

[Prasanna Kumar]

Hi all,

Any comments on this patch ?

Thanks,
Prasanna

On Thu, Dec 20, 2012 at 5:56 PM, Prasanna Kumar <prasanna.ps@samsung.com> wrote:
> This patch adds device tree nodes for MFC,G-scaler,MAU and ISP power domains
> of exynos5.It binds these power-domain nodes to repsective device tree nodes.
>
> Signed-off-by: Prasanna Kumar <prasanna.ps@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5250.dtsi |   25 +++++++++++++++++++++++++
>  1 files changed, 25 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index 581e57a..71a37bd 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -83,6 +83,7 @@
>                 compatible = "samsung,mfc-v6";
>                 reg = <0x11000000 0x10000>;
>                 interrupts = <0 96 0>;
> +               samsung,power-domain = <&pd_mfc>;
>         };
>
>         rtc {
> @@ -283,6 +284,7 @@
>                 samsung,supports-rstclr;
>                 samsung,supports-secdai;
>                 samsung,idma-addr = <0x03000000>;
> +               samsung,power-domain = <&pd_mau>;
>         };
>
>         i2s_1: i2s at 12D60000 {
> @@ -578,28 +580,51 @@
>                 };
>         };
>
> +       pd_gsc: gsc-power-domain at 0x10044000 {
> +               compatible = "samsung,exynos4210-pd";
> +               reg = <0x10044000 0x20>;
> +       };
> +
> +       pd_isp: isp-power-domain at 0x10044020 {
> +               compatible = "samsung,exynos4210-pd";
> +               reg = <0x10044020 0x20>;
> +               };
> +
> +       pd_mfc: mfc-power-domain at 0x10044040 {
> +               compatible = "samsung,exynos4210-pd";
> +               reg = <0x10044040 0x20>;
> +       };
> +
> +       pd_mau: mau-power-domain at 0x100440C0 {
> +               compatible = "samsung,exynos4210-pd";
> +               reg = <0x100440C0 0x20>;
> +       };
>         gsc_0:  gsc at 0x13e00000 {
>                 compatible = "samsung,exynos5-gsc";
>                 reg = <0x13e00000 0x1000>;
>                 interrupts = <0 85 0>;
> +               samsung,power-domain = <&pd_gsc>;
>         };
>
>         gsc_1:  gsc at 0x13e10000 {
>                 compatible = "samsung,exynos5-gsc";
>                 reg = <0x13e10000 0x1000>;
>                 interrupts = <0 86 0>;
> +               samsung,power-domain = <&pd_gsc>;
>         };
>
>         gsc_2:  gsc at 0x13e20000 {
>                 compatible = "samsung,exynos5-gsc";
>                 reg = <0x13e20000 0x1000>;
>                 interrupts = <0 87 0>;
> +               samsung,power-domain = <&pd_gsc>;
>         };
>
>         gsc_3:  gsc at 0x13e30000 {
>                 compatible = "samsung,exynos5-gsc";
>                 reg = <0x13e30000 0x1000>;
>                 interrupts = <0 88 0>;
> +               samsung,power-domain = <&pd_gsc>;
>         };
>
>         hdmi {
> --
> 1.7.0.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



-- 
Thanks
Prasanna Kumar

[PATCH 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

[Tomasz Figa]

Hi Thomas,

On Tuesday 04 of December 2012 14:29:24 Thomas Abraham wrote:
> On 27 November 2012 17:52, Prasanna Kumar <prasanna.ps@samsung.com> 
wrote:
> > From: Prasanna Kumar <prasanna.ps@samsung.com>
> > 
> > This patch adds a software workaround to the hardware
> > problem found in exynos5 while powergating.
> > 
> > It is observed that CLK_TOP_SRC3 register gets modified if
> > the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
> > set to XXTI which results in the device running very slow .
> > A big drop in performance is noticed whilerunning the video.
> > This issue also occurs while powergating MFC.
> > 
> > The value of clock source register is restored once the powergating
> > operation is completed.
> > 
> > Signed-off-by: Prasanna Kumar <prasanna.ps@samsung.com>
> > ---
> > 
> >  arch/arm/mach-exynos/pm_domains.c |   27 +++++++++++++++++++++++++++
> >  1 files changed, 27 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/mach-exynos/pm_domains.c
> > b/arch/arm/mach-exynos/pm_domains.c index 9f1351d..955cbe3 100644
> > --- a/arch/arm/mach-exynos/pm_domains.c
> > +++ b/arch/arm/mach-exynos/pm_domains.c
> > @@ -24,6 +24,8 @@
> > 
> >  #include <mach/regs-pmu.h>
> >  #include <plat/devs.h>
> > 
> > +#include <mach/regs-clock.h>
> > +#include <plat/cpu.h>
> > 
> >  /*
> >  
> >   * Exynos specific wrapper around the generic power domain
> > 
> > @@ -41,6 +43,7 @@ static int exynos_pd_power(struct generic_pm_domain
> > *domain, bool power_on)> 
> >         void __iomem *base;
> >         u32 timeout, pwr;
> >         char *op;
> > 
> > +       u32 tmp = 0;
> > 
> >         pd = container_of(domain, struct exynos_pm_domain, pd);
> >         base = pd->base;
> > 
> > @@ -48,6 +51,23 @@ static int exynos_pd_power(struct generic_pm_domain
> > *domain, bool power_on)> 
> >         pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0;
> >         __raw_writel(pwr, base);
> > 
> > +       /*
> > +        *It is found that the CLK SRC register in exynos5
> > +        *gets modified when power domain of gsc/mfc/isp/disp1
> > +        *is powered off.This happens only after the system is
> > +        *suspended and resumed and not before that.
> > +        *The following fix adresses this hardware issue.
> > +        *It saves the value of clock source register and
> > +        *resores it later
> > +        */
> > +
> > +       if (soc_is_exynos5250()) {
> > +               if (!power_on) {
> > +                       /* save clock source register */
> > +                       tmp = __raw_readl(EXYNOS5_CLKSRC_TOP3);
> > +               }
> > +       }
> 
> Does the value of EXYNOS5_CLKSRC_TOP3 register change as soon as the
> G-Scaler/MFC devices are power gated?
> 
> - If yes, the value of CLKSRC register should be saved before the
> power domain register is programmed.
> 
> - If not, as mentioned in the comment, if this issue occurs during a
> suspend-resume cycle, the value of this register can be saved and
> restored in the clock driver code itself.
> 
> The other thing that needs to be relooked into here is the use of
> EXYNOS5_CLKSRC_TOP3 register address. Currently, the clock registers
> are statically io-remapped. With the upcoming migration to common
> clock for Exynos5, the clock registers will not be statically
> io-remapped but instead remapped during clock initialization. So the
> use of EXYNOS5_CLKSRC_TOP3 will not hold and so we need to relook into
> this.
> 
> > +
> > 
> >         /* Wait max 1ms */
> >         timeout = 10;
> > 
> > @@ -61,6 +81,13 @@ static int exynos_pd_power(struct generic_pm_domain
> > *domain, bool power_on)> 
> >                 cpu_relax();
> >                 usleep_range(80, 100);
> >         
> >         }
> > 
> > +
> > +       if (soc_is_exynos5250()) {
> 
> We could use the of_machine_is_compatible api here instead of
> soc_is_exynos5250() macro.

I don't think that of_machine_is_compatible() is preferred over 
soc_is_xxx(). The former has dependencies on OF support and requires
a string comparison, while the latter is just a single integer check.

Best regards,
-- 
Tomasz Figa
Samsung Poland R&D Center
SW Solution Development, Linux Platform

[PATCH v2 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

[Tomasz Figa]

Hi Prasanna,

On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote:
> This patch adds a software workaround to the hardware
> problem found in exynos5 while powergating.
> 
> It is observed that CLK_TOP_SRC3 register gets modified if
> the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
> set to XXTI which results in the device running very slow .
> A big drop in performance is noticed whilerunning the video.
> This issue also occurs while powergating MFC.
> 
> The value of clock source register is restored once the powergating
> operation is completed.
> 
> Signed-off-by: Prasanna Kumar <prasanna.ps@samsung.com>
> ---
>  arch/arm/mach-exynos/pm_domains.c |   27 +++++++++++++++++++++++++++
>  1 files changed, 27 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/pm_domains.c
> b/arch/arm/mach-exynos/pm_domains.c index 9f1351d..bd8a41e 100644
> --- a/arch/arm/mach-exynos/pm_domains.c
> +++ b/arch/arm/mach-exynos/pm_domains.c
> @@ -24,6 +24,8 @@
> 
>  #include <mach/regs-pmu.h>
>  #include <plat/devs.h>
> +#include <mach/regs-clock.h>
> +#include <plat/cpu.h>
> 
>  /*
>   * Exynos specific wrapper around the generic power domain
> @@ -41,6 +43,24 @@ static int exynos_pd_power(struct generic_pm_domain
> *domain, bool power_on) void __iomem *base;
>  	u32 timeout, pwr;
>  	char *op;
> +	u32 tmp = 0;
> +
> +	/*
> +	 *It is found that the CLK SRC register in exynos5
> +	 *gets modified when power domain of gsc/mfc/isp/disp1
> +	 *is powered off.This happens only after the system is
> +	 *suspended and resumed and not before that.
> +	 *The following fix adresses this hardware issue.
> +	 *It saves the value of clock source register and
> +	 *resores it later
> +	 */
> +
> +	if (of_machine_is_compatible("samsung,exynos5250")) {
> +		if (!power_on) {
> +			/* save clock source register */
> +			tmp = __raw_readl(EXYNOS5_CLKSRC_TOP3);

I really think this problem needs more investigation, but if gating
a power domain can really change a clock source register and save/restore 
when gating is really required, then the code must be reworked so it does 
not access clock registers directly.

At the moment it is not a problem, but we are going to have Exynos support 
for Common Clock Framework merged in near future and it will remove static 
mapping of clock registers.

Best regards,
-- 
Tomasz Figa
Samsung Poland R&D Center
SW Solution Development, Linux Platform