[PATCH 1/3] clk: exynos5250: save/restore EPLL0 configuration

[PATCH 1/3] clk: exynos5250: save/restore EPLL0 configuration

[Sachin Kamat]

From: Andrew Bresticker <abrestic@chromium.org>

The EPLL configuration register needs to be saved across
suspend/resume.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
---
 drivers/clk/samsung/clk-exynos5250.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index ee866e377c80..6767635dc895 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -143,6 +143,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
 	SRC_CPU,
 	DIV_CPU0,
 	SRC_CORE1,
+	EPLL_CON0,
 	SRC_TOP0,
 	SRC_TOP2,
 	SRC_TOP3,
-- 
1.7.9.5

[PATCH 2/3] clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks

[Sachin Kamat]

From: Andrew Bresticker <abrestic@chromium.org>

The gate clocks for the MFC sysmmus appear to be flipped, i.e.
GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.
Fix this so that the MFC will start up.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
---
 drivers/clk/samsung/clk-exynos5250.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 6767635dc895..986464c2339a 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -562,8 +562,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
 	GATE(hdmi, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0, 0),
 
 	GATE(mfc, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0),
-	GATE(smmu_mfcl, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 1, 0, 0),
-	GATE(smmu_mfcr, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 2, 0, 0),
+	GATE(smmu_mfcl, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0, 0),
+	GATE(smmu_mfcr, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0, 0),
 
 	GATE(rotator, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),
 	GATE(jpeg, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),
-- 
1.7.9.5

[PATCH 3/3] clk: exynos5250: register APLL rate table

[Sachin Kamat]

From: Andrew Bresticker <abrestic@chromium.org>

Register the APLL rate table so that we can set the APLL rate from
the cpufreq driver.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
---
 drivers/clk/samsung/clk-exynos5250.c |   25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 986464c2339a..80f652053cb5 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -667,6 +667,27 @@ static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = {
 	{ },
 };
 
+static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = {
+	/* sorted in descending order */
+	/* PLL_35XX_RATE(rate, m, p, s) */
+	PLL_35XX_RATE(1700000000, 425, 6, 0),
+	PLL_35XX_RATE(1600000000, 200, 3, 0),
+	PLL_35XX_RATE(1500000000, 250, 4, 0),
+	PLL_35XX_RATE(1400000000, 175, 3, 0),
+	PLL_35XX_RATE(1300000000, 325, 6, 0),
+	PLL_35XX_RATE(1200000000, 200, 4, 0),
+	PLL_35XX_RATE(1100000000, 275, 6, 0),
+	PLL_35XX_RATE(1000000000, 125, 3, 0),
+	PLL_35XX_RATE(900000000, 150, 4, 0),
+	PLL_35XX_RATE(800000000, 100, 3, 0),
+	PLL_35XX_RATE(700000000, 175, 3, 1),
+	PLL_35XX_RATE(600000000, 200, 4, 1),
+	PLL_35XX_RATE(500000000, 125, 3, 1),
+	PLL_35XX_RATE(400000000, 100, 3, 1),
+	PLL_35XX_RATE(300000000, 200, 4, 2),
+	PLL_35XX_RATE(200000000, 100, 3, 2),
+};
+
 static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
 	[apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
 		APLL_CON0, "fout_apll", NULL),
@@ -707,8 +728,10 @@ static void __init exynos5250_clk_init(struct device_node *np)
 	samsung_clk_register_mux(exynos5250_pll_pmux_clks,
 				ARRAY_SIZE(exynos5250_pll_pmux_clks));
 
-	if (_get_rate("fin_pll") == 24 * MHZ)
+	if (_get_rate("fin_pll") == 24 * MHZ) {
 		exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
+		exynos5250_plls[apll].rate_table = apll_24mhz_tbl;
+	}
 
 	if (_get_rate("mout_vpllsrc") == 24 * MHZ)
 		exynos5250_plls[vpll].rate_table =  vpll_24mhz_tbl;
-- 
1.7.9.5

[PATCH 1/3] clk: exynos5250: save/restore EPLL0 configuration

[Sachin Kamat]

On 8 November 2013 15:44, Sachin Kamat <sachin.kamat@linaro.org> wrote:
> From: Andrew Bresticker <abrestic@chromium.org>
>
> The EPLL configuration register needs to be saved across
> suspend/resume.
>
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> ---
>  drivers/clk/samsung/clk-exynos5250.c |    1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index ee866e377c80..6767635dc895 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -143,6 +143,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
>         SRC_CPU,
>         DIV_CPU0,
>         SRC_CORE1,
> +       EPLL_CON0,
>         SRC_TOP0,
>         SRC_TOP2,
>         SRC_TOP3,
> --
> 1.7.9.5
>

Forgot to mention that this series is based on top of Tomasz Figa's
Exynos5250 cleanup series.
http://www.spinics.net/lists/arm-kernel/msg280039.html

-- 
With warm regards,
Sachin

[PATCH 1/3] clk: exynos5250: save/restore EPLL0 configuration

[Tomasz Figa]

Hi Sachin, Andrew,

On Friday 08 of November 2013 15:44:06 Sachin Kamat wrote:
> From: Andrew Bresticker <abrestic@chromium.org>
> 
> The EPLL configuration register needs to be saved across
> suspend/resume.
> 
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> ---
>  drivers/clk/samsung/clk-exynos5250.c |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index ee866e377c80..6767635dc895 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -143,6 +143,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
>  	SRC_CPU,
>  	DIV_CPU0,
>  	SRC_CORE1,
> +	EPLL_CON0,

What about EPLL_CON1 and EPLL_CON2? Also, have you considered register
restoration order?

Anyway, I believe it's not the correct way to restore PLL configuration.
See my Samsung PM consolidation series, especially patch [1] to see my
proposed way of handling this. (Beware of a bug that snuck into this patch
 - samsung_clk_save() is not being called for PLL registers.)

[1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/24078/focus=24087

Best regards,
Tomasz

[PATCH 2/3] clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks

[Tomasz Figa]

Hi Sachin, Andrew,

On Friday 08 of November 2013 15:44:07 Sachin Kamat wrote:
> From: Andrew Bresticker <abrestic@chromium.org>
> 
> The gate clocks for the MFC sysmmus appear to be flipped, i.e.
> GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.
> Fix this so that the MFC will start up.

Wow, this means that there is a mistake in the documentation. Not that
I'm surprised, though.

I guess you are sure about this, so:

Reviewed-by: Tomasz Figa <t.figa@samsung.com>

Best regards,
Tomasz

[PATCH 3/3] clk: exynos5250: register APLL rate table

[Tomasz Figa]

Hi Sachin, Andrew,

On Friday 08 of November 2013 15:44:08 Sachin Kamat wrote:
> From: Andrew Bresticker <abrestic@chromium.org>
> 
> Register the APLL rate table so that we can set the APLL rate from
> the cpufreq driver.
> 
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> ---
>  drivers/clk/samsung/clk-exynos5250.c |   25 ++++++++++++++++++++++++-
>  1 file changed, 24 insertions(+), 1 deletion(-)

You know that you still need to fix the cpufreq driver to use these,
don't you? Anyway:

Reviewed-by: Tomasz Figa <t.figa@samsung.com>

Best regards,
Tomasz

[PATCH 2/3] clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks

[Sachin Kamat]

Hi Tomasz,

On 10 November 2013 22:38, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Hi Sachin, Andrew,
>
> On Friday 08 of November 2013 15:44:07 Sachin Kamat wrote:
>> From: Andrew Bresticker <abrestic@chromium.org>
>>
>> The gate clocks for the MFC sysmmus appear to be flipped, i.e.
>> GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.
>> Fix this so that the MFC will start up.
>
> Wow, this means that there is a mistake in the documentation. Not that
> I'm surprised, though.

Yes, there is a mistake in the TRM in this case.

>
> I guess you are sure about this, so:
>
> Reviewed-by: Tomasz Figa <t.figa@samsung.com>

Thanks.

-- 
With warm regards,
Sachin

[PATCH 2/3] clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks

[Sachin Kamat]

Hi Tomasz,

On 10 November 2013 22:38, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Hi Sachin, Andrew,
>
> On Friday 08 of November 2013 15:44:07 Sachin Kamat wrote:
>> From: Andrew Bresticker <abrestic@chromium.org>
>>
>> The gate clocks for the MFC sysmmus appear to be flipped, i.e.
>> GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.
>> Fix this so that the MFC will start up.
>
> Wow, this means that there is a mistake in the documentation. Not that
> I'm surprised, though.
>
> I guess you are sure about this, so:
>
> Reviewed-by: Tomasz Figa <t.figa@samsung.com>

I believe you are going to take this through your tree along with a
few others which you have already reviewed?

-- 
With warm regards,
Sachin

[PATCH 2/3] clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks

[Tomasz Figa]

Hi Sachin,

2013/12/18 Sachin Kamat <sachin.kamat@linaro.org>:
> Hi Tomasz,
>
> On 10 November 2013 22:38, Tomasz Figa <tomasz.figa@gmail.com> wrote:
>> Hi Sachin, Andrew,
>>
>> On Friday 08 of November 2013 15:44:07 Sachin Kamat wrote:
>>> From: Andrew Bresticker <abrestic@chromium.org>
>>>
>>> The gate clocks for the MFC sysmmus appear to be flipped, i.e.
>>> GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.
>>> Fix this so that the MFC will start up.
>>
>> Wow, this means that there is a mistake in the documentation. Not that
>> I'm surprised, though.
>>
>> I guess you are sure about this, so:
>>
>> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
>
> I believe you are going to take this through your tree along with a
> few others which you have already reviewed?

Thanks for reminding me about this patch. It's been quite a while
since it was posted
to the list.

Yes, I will apply it to samsung-clk tree.

Best regards,
Tomasz

[PATCH 2/3] clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks

[Mike Turquette]

Quoting Tomasz Figa (2013-12-18 10:28:57)
> Hi Sachin,
> 
> 2013/12/18 Sachin Kamat <sachin.kamat@linaro.org>:
> > Hi Tomasz,
> >
> > On 10 November 2013 22:38, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> >> Hi Sachin, Andrew,
> >>
> >> On Friday 08 of November 2013 15:44:07 Sachin Kamat wrote:
> >>> From: Andrew Bresticker <abrestic@chromium.org>
> >>>
> >>> The gate clocks for the MFC sysmmus appear to be flipped, i.e.
> >>> GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.
> >>> Fix this so that the MFC will start up.
> >>
> >> Wow, this means that there is a mistake in the documentation. Not that
> >> I'm surprised, though.
> >>
> >> I guess you are sure about this, so:
> >>
> >> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
> >
> > I believe you are going to take this through your tree along with a
> > few others which you have already reviewed?
> 
> Thanks for reminding me about this patch. It's been quite a while
> since it was posted
> to the list.
> 
> Yes, I will apply it to samsung-clk tree.

Feel free to add my Ack when you apply it. Will these be sent later as a
pull request for the clk tree?

Regards,
Mike

> 
> Best regards,
> Tomasz

[PATCH 2/3] clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks

[Tomasz Figa]

On Wednesday 18 of December 2013 11:24:30 Mike Turquette wrote:
> Quoting Tomasz Figa (2013-12-18 10:28:57)
> > Hi Sachin,
> > 
> > 2013/12/18 Sachin Kamat <sachin.kamat@linaro.org>:
> > > Hi Tomasz,
> > >
> > > On 10 November 2013 22:38, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> > >> Hi Sachin, Andrew,
> > >>
> > >> On Friday 08 of November 2013 15:44:07 Sachin Kamat wrote:
> > >>> From: Andrew Bresticker <abrestic@chromium.org>
> > >>>
> > >>> The gate clocks for the MFC sysmmus appear to be flipped, i.e.
> > >>> GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.
> > >>> Fix this so that the MFC will start up.
> > >>
> > >> Wow, this means that there is a mistake in the documentation. Not that
> > >> I'm surprised, though.
> > >>
> > >> I guess you are sure about this, so:
> > >>
> > >> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
> > >
> > > I believe you are going to take this through your tree along with a
> > > few others which you have already reviewed?
> > 
> > Thanks for reminding me about this patch. It's been quite a while
> > since it was posted
> > to the list.
> > 
> > Yes, I will apply it to samsung-clk tree.
> 
> Feel free to add my Ack when you apply it. Will these be sent later as a
> pull request for the clk tree?

Yes. That's the plan. :)

Best regards,
Tomasz

[PATCH 3/3] clk: exynos5250: register APLL rate table

[Sachin Kamat]

Hi Tomasz,

On 10 November 2013 22:44, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Hi Sachin, Andrew,
>
> On Friday 08 of November 2013 15:44:08 Sachin Kamat wrote:
>> From: Andrew Bresticker <abrestic@chromium.org>
>>
>> Register the APLL rate table so that we can set the APLL rate from
>> the cpufreq driver.
>>
>> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
>> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
>> ---
>>  drivers/clk/samsung/clk-exynos5250.c |   25 ++++++++++++++++++++++++-
>>  1 file changed, 24 insertions(+), 1 deletion(-)
>
> You know that you still need to fix the cpufreq driver to use these,
> don't you? Anyway:
>
> Reviewed-by: Tomasz Figa <t.figa@samsung.com>

This one too needs to be applied to your tree.

-- 
With warm regards,
Sachin

[PATCH 2/3] clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks

[Tomasz Figa]

Hi Sachin, Andrew,

On Wednesday 18 of December 2013 23:39:58 Sachin Kamat wrote:
> Hi Tomasz,
> 
> On 10 November 2013 22:38, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> > Hi Sachin, Andrew,
> >
> > On Friday 08 of November 2013 15:44:07 Sachin Kamat wrote:
> >> From: Andrew Bresticker <abrestic@chromium.org>
> >>
> >> The gate clocks for the MFC sysmmus appear to be flipped, i.e.
> >> GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.
> >> Fix this so that the MFC will start up.
> >
> > Wow, this means that there is a mistake in the documentation. Not that
> > I'm surprised, though.
> >
> > I guess you are sure about this, so:
> >
> > Reviewed-by: Tomasz Figa <t.figa@samsung.com>
> 
> I believe you are going to take this through your tree along with a
> few others which you have already reviewed?

This patch seems to depend on my Exynos 5250 clock clean-up series, which
will be merged for 3.14. Are you okay with this patch being merged for
3.14 as well or this fix is needed for earlier kernel versions too?
(It is not a regression introduced in 3.13, though.)

Best regards,
Tomasz

[PATCH 2/3] clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks

[Sachin Kamat]

Hi Tomasz,

On 19 December 2013 19:40, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Sachin, Andrew,
>
> On Wednesday 18 of December 2013 23:39:58 Sachin Kamat wrote:
>> Hi Tomasz,
>>
>> On 10 November 2013 22:38, Tomasz Figa <tomasz.figa@gmail.com> wrote:
>> > Hi Sachin, Andrew,
>> >
>> > On Friday 08 of November 2013 15:44:07 Sachin Kamat wrote:
>> >> From: Andrew Bresticker <abrestic@chromium.org>
>> >>
>> >> The gate clocks for the MFC sysmmus appear to be flipped, i.e.
>> >> GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.
>> >> Fix this so that the MFC will start up.
>> >
>> > Wow, this means that there is a mistake in the documentation. Not that
>> > I'm surprised, though.
>> >
>> > I guess you are sure about this, so:
>> >
>> > Reviewed-by: Tomasz Figa <t.figa@samsung.com>
>>
>> I believe you are going to take this through your tree along with a
>> few others which you have already reviewed?
>
> This patch seems to depend on my Exynos 5250 clock clean-up series, which
> will be merged for 3.14. Are you okay with this patch being merged for
> 3.14 as well or this fix is needed for earlier kernel versions too?
> (It is not a regression introduced in 3.13, though.)

Yes, I did rebase it on top of your series along with other patches.
Though not a regression introduced in 3.13, I think it makes sense to have this
sent as a fix during this release (3.13) itself. Let me know if you
want me to base it
on top of 3.13-rc4 and re-send.


-- 
With warm regards,
Sachin

[PATCH 3/3] clk: exynos5250: register APLL rate table

[Sachin Kamat]

On 19 December 2013 09:14, Sachin Kamat <sachin.kamat@linaro.org> wrote:
> Hi Tomasz,
>
> On 10 November 2013 22:44, Tomasz Figa <tomasz.figa@gmail.com> wrote:
>> Hi Sachin, Andrew,
>>
>> On Friday 08 of November 2013 15:44:08 Sachin Kamat wrote:
>>> From: Andrew Bresticker <abrestic@chromium.org>
>>>
>>> Register the APLL rate table so that we can set the APLL rate from
>>> the cpufreq driver.
>>>
>>> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
>>> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
>>> ---
>>>  drivers/clk/samsung/clk-exynos5250.c |   25 ++++++++++++++++++++++++-
>>>  1 file changed, 24 insertions(+), 1 deletion(-)
>>
>> You know that you still need to fix the cpufreq driver to use these,
>> don't you? Anyway:
>>
>> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
>
> This one too needs to be applied to your tree.

Ping Tomasz.



-- 
With warm regards,
Sachin

[PATCH 3/3] clk: exynos5250: register APLL rate table

[Tomasz Figa]

On Tuesday 31 of December 2013 08:46:14 Sachin Kamat wrote:
> On 19 December 2013 09:14, Sachin Kamat <sachin.kamat@linaro.org> wrote:
> > Hi Tomasz,
> >
> > On 10 November 2013 22:44, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> >> Hi Sachin, Andrew,
> >>
> >> On Friday 08 of November 2013 15:44:08 Sachin Kamat wrote:
> >>> From: Andrew Bresticker <abrestic@chromium.org>
> >>>
> >>> Register the APLL rate table so that we can set the APLL rate from
> >>> the cpufreq driver.
> >>>
> >>> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> >>> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> >>> ---
> >>>  drivers/clk/samsung/clk-exynos5250.c |   25 ++++++++++++++++++++++++-
> >>>  1 file changed, 24 insertions(+), 1 deletion(-)
> >>
> >> You know that you still need to fix the cpufreq driver to use these,
> >> don't you? Anyway:
> >>
> >> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
> >
> > This one too needs to be applied to your tree.
> 
> Ping Tomasz.

Applied.

Best regards,
Tomasz