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Tue, 02 Apr 2019 21:26:46 -0700 (PDT) X-Gm-Message-State: APjAAAX0eKD3Cg59dCil9va1rD2EUkG+nDGG2M4O0XslLgkORYaUweca 72bSNp5Gav8x9Q1176fH0Yh3jokCkPPBKAtf+A== X-Google-Smtp-Source: APXvYqx0kC8CrDmDtHIJHeCX3D9HiBvCpBlJuxrUwS+/0q4h+yN7jGcgGkjrvgpo97rZARChx3TVe4May3Y0Mid9Pt0= X-Received: by 2002:a37:9e0d:: with SMTP id h13mr58034293qke.135.1554265605359; Tue, 02 Apr 2019 21:26:45 -0700 (PDT) MIME-Version: 1.0 References: <20190325074523.26456-1-josephl@nvidia.com> <20190325074523.26456-2-josephl@nvidia.com> <5ca06133.1c69fb81.11ebf.91ce@mx.google.com> <7d680700-d2f2-7b6c-a8bf-dca6d54dbf2c@nvidia.com> In-Reply-To: <7d680700-d2f2-7b6c-a8bf-dca6d54dbf2c@nvidia.com> From: Rob Herring Date: Tue, 2 Apr 2019 23:26:33 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 1/8] dt-bindings: memory: tegra: Add Tegra210 EMC bindings To: Joseph Lo X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190402_212647_608391_73F5345C X-CRM114-Status: GOOD ( 22.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Stephen Boyd , Peter De Schrijver , Jonathan Hunter , Thierry Reding , linux-tegra@vger.kernel.org, linux-clk , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Apr 1, 2019 at 2:58 AM Joseph Lo wrote: > > On 3/31/19 2:41 PM, Rob Herring wrote: > > On Mon, Mar 25, 2019 at 03:45:16PM +0800, Joseph Lo wrote: > >> Add the binding document for the external memory controller (EMC) which > >> communicates with external LPDDR4 devices. It includes the bindings of > >> the EMC node and the EMC table of different rates. > >> > >> To support high rates for LPDDR4, the EMC table must be trained before > >> it can be used for runtime clock switching. It has been done by firmware > >> and merged to the table that Linux kernel uses. For backward > >> compatibility with the devices that had been launched on the market, like > >> Shield and Jetson platforms, the bindings in the EMC table should remain > >> the same. So the firmware can recognize them and merge the trained EMC > >> table for the kernel. > > Hi Rob, > > Thanks for reviewing. > > > > > Overall seems pretty bloated. How much of this really varies by board > > vs. just being a dump of all the register values to stuff? > > Most of them are register values. And by different SDRAM devices that > could be used on the same platform (use ram code to identify them), the > value could be different. > > > > > Primarily, I'm leary of getting a similar binding for every vendor's DDR > > setup. > > > > Some mostly trivial comments follow. > > Really sorry about that. I understand these basic rules for DT bindings, > but the case here is that these un-reviewed bindings have been used in > the firmware on the shipped products. To support the same with the > upstream kernel and consider the firmware blob may not be updated, we > have no choice to just use the same bindings in the upstream kernel. > > How can we deal with this case? Simply, we do not accept bindings as-is. If we did, then there would be no point in documenting and reviewing bindings. NVidia chose this path and now gets to live with it. Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel