[PATCH v6 0/5] MCPM backend for Exynos5420

[PATCH v6 0/5] MCPM backend for Exynos5420

[Abhilash Kesavan]

This is v6 of the series adding MCPM backend support for SMP secondary boot
and core switching on Samsung's Exynos5420. The patches are based on the mcpm
support added for Exynos5420 in the Chromium kernel repository here:
https://chromium.googlesource.com/chromiumos/third_party/kernel-next/+/chromeos-3.8

The patches have been prepared on Kukjin Kim's for-next branch and tested on
SMDK5420 EVT1 as well as an exynos5420 based chromebook (peach-pit) using the
"/dev/b.L_switcher" user interface. Secondary core boot-up has also been tested
on both the boards.

Changes since v5:
Addressed the following comments from Kukjin Kim:
	- The recently merged sysram dt patch has a slightly modified compatible
	  string (exynos4210-sysram-ns). Made the appropriate change in the mcpm
	  back-end to handle this.
	- Changed the naming of generic cpu/cluster control functions.
	  Correspondingly changed the usage in the mcpm back-end.
	- Modified hotplug.c to use the generic cpu power down function.
	- Cleaned up unused S5P_ARM_CORE1_CONFIGURATION and S5P_ARM_CORE1_STATUS
	  macros.
	- Added a macro for cpu boot address offset and changed debug statement
	  from pr_warn to pr_debug.
	- Added missing signed-off-by's to the generic cpu/cluster control
	  patches.

Changes since v4:
Addressed the following comments from Nicolas Pitre:
	- Fixed the location of L2 prefetching disable code.
	- Fixed the location of the "TODO" comment.
	- Fixed a possible race in mcpm cluster state check in
	  exynos_power_up().
	
Changes since v3:
	- Rebased on top of the latest SYSRAM DT patchset from Sachin Kamat.

Addressed the following comments from Lorenzo Pieralisi and Nicolas Pitre:
	- Dropped the patch "arm: exynos: Add /dev/bL_status user interface on
	  Exynos5420".
	- Fixed the header ordering and removed unnecessary header inclusions.
	- Made the code symmetric in exynos_cluster_power_control().
	- Fixed the error path in exynos_power_up.
	- Got rid of "cnt" variable used for last man checking.
	- Removed stale comments.
	- Replaced "soc_is" with "of_find_compatible_node" check for exynos5420.
	- Added L2 prefetching disable code needed during A15 power down.

Changes since v2:
Addressed the following comments from Nicolas Pitre and Daniel Lezcano:
	- Added generic common (cluster) configuration functions to pm.c
	  which may be used by other subsystems.
	- Removed unused "cpumask" variable in mcpm code.
	- Re-worked exynos_power_down_finish() referencing the tc2_pm code.
	- Removed the status checks in core and cluster power functions. We
	  just set the power control bit and do not check the previous state
	  anymore.
	- Removed incorrect jiffies timeout usage in path where IRQs are
	  disabled.

Changes since v1:
Addressed the following comments from Dave Martin and Nicolas Pitre:
	- Fixed help text for EXYNOS5420_MCPM symbol.
	- Removed mcpm-exynos-setup.S file and added similar code from tc2_pm.c.
	- Changed the spinlock name from "bl_lock" to "exynos_mcpm_lock".
	- Removed snoop enable/disable calls due to possible cpuidle issue and
	  not having numbers proving a significant power savings. Dropped the
	  "drivers/bus: arm-cci: Add common control interface for ACE ports"
	  patch from v1 as it was no longer needed.
	- Created a macro for exynos-specific v7_exit_coherency_flush which
	  handles an erratum. This was done to prevent duplication of code.
	- Removed "outer_flush_all" call.
	- Removed redundant dsb in power_down function.
	- Removed unnecessary initialization of global variables to zero.
	- Split the /dev/bL_status debug interface into another patch.
	- Fixed error handling in exynos_mcpm_init().
	- Called mcpm_smp_set_ops directly from exynos_mcpm_init().
	- Added a TODO for supporting cluster down on exynos5420.

NOTE:
- Have added Leela Krishna's generic cpu power control function series
  as part of this patchset.
- I have tested with and without the erratum 799270 workaround and both
  work fine. I have kept the erratum fix for the time being.

Abhilash Kesavan (2):
  arm: exynos: Add generic cluster power control functions
  arm: exynos: Add MCPM call-back functions

Andrew Bresticker (1):
  ARM: dts: exynos5420: add CCI node

Leela Krishna Amudala (2):
  ARM: EXYNOS: Add generic cpu power control functions for all exynos
    based SoCs
  ARM: EXYNOS: use generic exynos cpu power control functions

 arch/arm/boot/dts/exynos5420.dtsi  |   27 +++
 arch/arm/mach-exynos/Kconfig       |    8 +
 arch/arm/mach-exynos/Makefile      |    2 +
 arch/arm/mach-exynos/common.h      |    6 +
 arch/arm/mach-exynos/hotplug.c     |    2 +-
 arch/arm/mach-exynos/mcpm-exynos.c |  346 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/platsmp.c     |    9 +-
 arch/arm/mach-exynos/pm.c          |   66 +++++++
 arch/arm/mach-exynos/regs-pmu.h    |   16 +-
 9 files changed, 473 insertions(+), 9 deletions(-)
 create mode 100644 arch/arm/mach-exynos/mcpm-exynos.c

-- 
1.7.9.5

[PATCH v6 1/5] ARM: EXYNOS: Add generic cpu power control functions for all exynos based SoCs

[Abhilash Kesavan]

From: Leela Krishna Amudala <leela.krishna@linaro.org>

Add generic cpu power control functions for exynos based SoCS
for cpu power up/down and to know the cpu status.

Signed-off-by: Leela Krishna Amudala <leela.krishna@linaro.org>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 arch/arm/mach-exynos/common.h   |    3 +++
 arch/arm/mach-exynos/pm.c       |   36 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/regs-pmu.h |    6 ++++++
 3 files changed, 45 insertions(+)

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 278b573..20adc2c 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -132,6 +132,9 @@ struct exynos_pmu_conf {
 };
 
 extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
+extern void exynos_cpu_power_down(int cpu);
+extern void exynos_cpu_power_up(int cpu);
+extern int  exynos_cpu_power_state(int cpu);
 
 extern void s5p_init_cpu(void __iomem *cpuid_addr);
 extern unsigned int samsung_rev(void);
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index ca672e2..60c3356 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -99,6 +99,42 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
 	return -ENOENT;
 }
 
+/**
+ * exynos_core_power_down : power down the specified cpu
+ * @cpu : the cpu to power down
+ *
+ * Power down the specified cpu. The sequence must be finished by a
+ * call to cpu_do_idle()
+ *
+ */
+void exynos_cpu_power_down(int cpu)
+{
+	__raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+}
+
+/**
+ * exynos_cpu_power_up : power up the specified cpu
+ * @cpu : the cpu to power up
+ *
+ * Power up the specified cpu
+ */
+void exynos_cpu_power_up(int cpu)
+{
+	__raw_writel(S5P_CORE_LOCAL_PWR_EN,
+		     EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+}
+
+/**
+ * exynos_cpu_power_state : returns the power state of the cpu
+ * @cpu : the cpu to retrieve the power state from
+ *
+ */
+int exynos_cpu_power_state(int cpu)
+{
+	return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
+			S5P_CORE_LOCAL_PWR_EN);
+}
+
 /* For Cortex-A9 Diagnostic and Power control register */
 static unsigned int save_arm_register[2];
 
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4f6a256..84634ac 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -105,6 +105,12 @@
 #define S5P_GPS_LOWPWR				S5P_PMUREG(0x139C)
 #define S5P_GPS_ALIVE_LOWPWR			S5P_PMUREG(0x13A0)
 
+#define EXYNOS_ARM_CORE0_CONFIGURATION		S5P_PMUREG(0x2000)
+#define EXYNOS_ARM_CORE_CONFIGURATION(_nr)	\
+			(EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
+#define EXYNOS_ARM_CORE_STATUS(_nr)		\
+			(EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
+
 #define S5P_ARM_CORE1_CONFIGURATION		S5P_PMUREG(0x2080)
 #define S5P_ARM_CORE1_STATUS			S5P_PMUREG(0x2084)
 
-- 
1.7.9.5

[PATCH v6 2/5] ARM: EXYNOS: use generic exynos cpu power control functions

[Abhilash Kesavan]

From: Leela Krishna Amudala <leela.krishna@linaro.org>

Use generic exynos cpu power control functions to power up/down
and to know the status of the cpu in platsmp and hotplug code.

Signed-off-by: Leela Krishna Amudala <leela.krishna@linaro.org>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 arch/arm/mach-exynos/hotplug.c  |    2 +-
 arch/arm/mach-exynos/platsmp.c  |    9 +++------
 arch/arm/mach-exynos/regs-pmu.h |    3 ---
 3 files changed, 4 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 3cab3f5..69fa483 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -44,7 +44,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 
 		/* make cpu1 to be turned off at next WFI command */
 		if (cpu == 1)
-			__raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+			exynos_cpu_power_down(cpu);
 
 		/*
 		 * here's the WFI
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 51cdabe..9c16da2 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -131,15 +131,12 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
 	 */
 	write_pen_release(phys_cpu);
 
-	if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
-		__raw_writel(S5P_CORE_LOCAL_PWR_EN,
-			     S5P_ARM_CORE1_CONFIGURATION);
-
+	if (!exynos_cpu_power_state(cpu)) {
+		exynos_cpu_power_up(cpu);
 		timeout = 10;
 
 		/* wait max 10 ms until cpu1 is on */
-		while ((__raw_readl(S5P_ARM_CORE1_STATUS)
-			& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
+		while (exynos_cpu_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN) {
 			if (timeout-- == 0)
 				break;
 
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 84634ac..98fb8d8 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -111,9 +111,6 @@
 #define EXYNOS_ARM_CORE_STATUS(_nr)		\
 			(EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
 
-#define S5P_ARM_CORE1_CONFIGURATION		S5P_PMUREG(0x2080)
-#define S5P_ARM_CORE1_STATUS			S5P_PMUREG(0x2084)
-
 #define S5P_PAD_RET_MAUDIO_OPTION		S5P_PMUREG(0x3028)
 #define S5P_PAD_RET_GPIO_OPTION			S5P_PMUREG(0x3108)
 #define S5P_PAD_RET_UART_OPTION			S5P_PMUREG(0x3128)
-- 
1.7.9.5

[PATCH v6 3/5] arm: exynos: Add generic cluster power control functions

[Abhilash Kesavan]

Add generic cluster power control functions for exynos based SoCS
for cluster power up/down and to know the cluster status.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 arch/arm/mach-exynos/common.h   |    3 +++
 arch/arm/mach-exynos/pm.c       |   30 ++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/regs-pmu.h |    6 ++++++
 3 files changed, 39 insertions(+)

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 20adc2c..ae5f648 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -135,6 +135,9 @@ extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
 extern void exynos_cpu_power_down(int cpu);
 extern void exynos_cpu_power_up(int cpu);
 extern int  exynos_cpu_power_state(int cpu);
+extern void exynos_cluster_power_down(int cluster);
+extern void exynos_cluster_power_up(int cluster);
+extern int  exynos_cluster_power_state(int cluster);
 
 extern void s5p_init_cpu(void __iomem *cpuid_addr);
 extern unsigned int samsung_rev(void);
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 60c3356..aba2ff6 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -135,6 +135,36 @@ int exynos_cpu_power_state(int cpu)
 			S5P_CORE_LOCAL_PWR_EN);
 }
 
+/**
+ * exynos_cluster_power_down : power down the specified cluster
+ * @cluster : the cluster to power down
+ */
+void exynos_cluster_power_down(int cluster)
+{
+	__raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
+}
+
+/**
+ * exynos_cluster_power_up : power up the specified cluster
+ * @cluster : the cluster to power up
+ */
+void exynos_cluster_power_up(int cluster)
+{
+	__raw_writel(S5P_CORE_LOCAL_PWR_EN,
+		     EXYNOS_COMMON_CONFIGURATION(cluster));
+}
+
+/**
+ * exynos_cluster_power_state : returns the power state of the cluster
+ * @cluster : the cluster to retrieve the power state from
+ *
+ */
+int exynos_cluster_power_state(int cluster)
+{
+	return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
+			S5P_CORE_LOCAL_PWR_EN);
+}
+
 /* For Cortex-A9 Diagnostic and Power control register */
 static unsigned int save_arm_register[2];
 
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 98fb8d8..f6b68a3 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -111,6 +111,12 @@
 #define EXYNOS_ARM_CORE_STATUS(_nr)		\
 			(EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
 
+#define EXYNOS_ARM_COMMON_CONFIGURATION		S5P_PMUREG(0x2500)
+#define EXYNOS_COMMON_CONFIGURATION(_nr)	\
+			(EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr)))
+#define EXYNOS_COMMON_STATUS(_nr)		\
+			(EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4)
+
 #define S5P_PAD_RET_MAUDIO_OPTION		S5P_PMUREG(0x3028)
 #define S5P_PAD_RET_GPIO_OPTION			S5P_PMUREG(0x3108)
 #define S5P_PAD_RET_UART_OPTION			S5P_PMUREG(0x3128)
-- 
1.7.9.5

[PATCH v6 4/5] ARM: dts: exynos5420: add CCI node

[Abhilash Kesavan]

From: Andrew Bresticker <abrestic@chromium.org>

Add device-tree bindings for the ARM CCI-400 on Exynos5420.  There
are two slave interfaces: one for the A15 cluster and one for the
A7 cluster.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi |   27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 0cd65a7..e170c3c 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -58,6 +58,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <0x0>;
 			clock-frequency = <1800000000>;
+			cci-control-port = <&cci_control1>;
 		};
 
 		cpu1: cpu at 1 {
@@ -65,6 +66,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <0x1>;
 			clock-frequency = <1800000000>;
+			cci-control-port = <&cci_control1>;
 		};
 
 		cpu2: cpu at 2 {
@@ -72,6 +74,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <0x2>;
 			clock-frequency = <1800000000>;
+			cci-control-port = <&cci_control1>;
 		};
 
 		cpu3: cpu at 3 {
@@ -79,6 +82,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <0x3>;
 			clock-frequency = <1800000000>;
+			cci-control-port = <&cci_control1>;
 		};
 
 		cpu4: cpu at 100 {
@@ -86,6 +90,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x100>;
 			clock-frequency = <1000000000>;
+			cci-control-port = <&cci_control0>;
 		};
 
 		cpu5: cpu at 101 {
@@ -93,6 +98,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x101>;
 			clock-frequency = <1000000000>;
+			cci-control-port = <&cci_control0>;
 		};
 
 		cpu6: cpu at 102 {
@@ -100,6 +106,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x102>;
 			clock-frequency = <1000000000>;
+			cci-control-port = <&cci_control0>;
 		};
 
 		cpu7: cpu at 103 {
@@ -107,6 +114,26 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x103>;
 			clock-frequency = <1000000000>;
+			cci-control-port = <&cci_control0>;
+		};
+	};
+
+	cci at 10d20000 {
+		compatible = "arm,cci-400";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x10d20000 0x1000>;
+		ranges = <0x0 0x10d20000 0x6000>;
+
+		cci_control0: slave-if at 4000 {
+			compatible = "arm,cci-400-ctrl-if";
+			interface-type = "ace";
+			reg = <0x4000 0x1000>;
+		};
+		cci_control1: slave-if at 5000 {
+			compatible = "arm,cci-400-ctrl-if";
+			interface-type = "ace";
+			reg = <0x5000 0x1000>;
 		};
 	};
 
-- 
1.7.9.5

[PATCH v6 5/5] arm: exynos: Add MCPM call-back functions

[Abhilash Kesavan]

Add machine-dependent MCPM call-backs for Exynos5420. These are used
to power up/down the secondary CPUs during boot, shutdown, s2r and
switching.

Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Inderpal Singh <inderpal.s@samsung.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org>
---
 arch/arm/mach-exynos/Kconfig       |    8 +
 arch/arm/mach-exynos/Makefile      |    2 +
 arch/arm/mach-exynos/mcpm-exynos.c |  346 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/regs-pmu.h    |    3 +
 4 files changed, 359 insertions(+)
 create mode 100644 arch/arm/mach-exynos/mcpm-exynos.c

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index fc8bf18..1602abc 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -110,4 +110,12 @@ config SOC_EXYNOS5440
 
 endmenu
 
+config EXYNOS5420_MCPM
+	bool "Exynos5420 Multi-Cluster PM support"
+	depends on MCPM && SOC_EXYNOS5420
+	select ARM_CCI
+	help
+	  This is needed to provide CPU and cluster power management
+	  on Exynos5420 implementing big.LITTLE.
+
 endif
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index f6dcc25..2e0666d 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -24,3 +24,5 @@ obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_exynos-smc.o		:=-Wa,-march=armv7-a$(plus_sec)
+
+obj-$(CONFIG_EXYNOS5420_MCPM)	+= mcpm-exynos.o
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
new file mode 100644
index 0000000..ec4ae00
--- /dev/null
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -0,0 +1,346 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * arch/arm/mach-exynos/mcpm-exynos.c
+ *
+ * Based on arch/arm/mach-vexpress/dcscb.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/arm-cci.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+#include <asm/mcpm.h>
+
+#include "regs-pmu.h"
+#include "common.h"
+
+#define EXYNOS5420_CPUS_PER_CLUSTER	4
+#define EXYNOS5420_NR_CLUSTERS		2
+#define MCPM_BOOT_ADDR_OFFSET		0x1c
+
+/* Non-secure iRAM base address */
+static void __iomem *ns_sram_base_addr;
+
+/*
+ * The common v7_exit_coherency_flush API could not be used because of the
+ * Erratum 799270 workaround. This macro is the same as the common one (in
+ * arch/arm/include/asm/cacheflush.h) except for the erratum handling.
+ */
+#define exynos_v7_exit_coherency_flush(level) \
+	asm volatile( \
+	"stmfd	sp!, {fp, ip}\n\t"\
+	"mrc	p15, 0, r0, c1, c0, 0	@ get SCTLR\n\t" \
+	"bic	r0, r0, #"__stringify(CR_C)"\n\t" \
+	"mcr	p15, 0, r0, c1, c0, 0	@ set SCTLR\n\t" \
+	"isb\n\t"\
+	"bl	v7_flush_dcache_"__stringify(level)"\n\t" \
+	"clrex\n\t"\
+	"mrc	p15, 0, r0, c1, c0, 1	@ get ACTLR\n\t" \
+	"bic	r0, r0, #(1 << 6)	@ disable local coherency\n\t" \
+	/* Dummy Load of a device register to avoid Erratum 799270 */ \
+	"ldr	r4, [%0]\n\t" \
+	"and	r4, r4, #0\n\t" \
+	"orr	r0, r0, r4\n\t" \
+	"mcr	p15, 0, r0, c1, c0, 1	@ set ACTLR\n\t" \
+	"isb\n\t" \
+	"dsb\n\t" \
+	"ldmfd	sp!, {fp, ip}" \
+	: \
+	: "Ir" (S5P_INFORM0) \
+	: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
+	  "r9", "r10", "lr", "memory")
+
+/*
+ * We can't use regular spinlocks. In the switcher case, it is possible
+ * for an outbound CPU to call power_down() after its inbound counterpart
+ * is already live using the same logical CPU number which trips lockdep
+ * debugging.
+ */
+static arch_spinlock_t exynos_mcpm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+static int
+cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS];
+
+#define exynos_cluster_usecnt(cluster) \
+	(cpu_use_count[0][cluster] +   \
+	 cpu_use_count[1][cluster] +   \
+	 cpu_use_count[2][cluster] +   \
+	 cpu_use_count[3][cluster])
+
+#define exynos_cluster_unused(cluster) !exynos_cluster_usecnt(cluster)
+
+static int exynos_cluster_power_control(unsigned int cluster, int enable)
+{
+	unsigned int tries = 100;
+	unsigned int val;
+
+	if (enable) {
+		exynos_cluster_power_up(cluster);
+		val = S5P_CORE_LOCAL_PWR_EN;
+	} else {
+		exynos_cluster_power_down(cluster);
+		val = 0;
+	}
+
+	/* Wait until cluster power control is applied */
+	while (tries--) {
+		if (exynos_cluster_power_state(cluster) == val)
+			return 0;
+
+		cpu_relax();
+	}
+	pr_debug("timed out waiting for cluster %u to power %s\n", cluster,
+		enable ? "on" : "off");
+
+	return -ETIMEDOUT;
+}
+
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+	unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+	int err = 0;
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+		cluster >= EXYNOS5420_NR_CLUSTERS)
+		return -EINVAL;
+
+	/*
+	 * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+	 * variant exists, we need to disable IRQs manually here.
+	 */
+	local_irq_disable();
+	arch_spin_lock(&exynos_mcpm_lock);
+
+	cpu_use_count[cpu][cluster]++;
+	if (cpu_use_count[cpu][cluster] == 1) {
+		bool was_cluster_down =
+			(exynos_cluster_usecnt(cluster) == 1);
+
+		/*
+		 * Turn on the cluster (L2/COMMON) and then power on the
+		 * cores.
+		 */
+		if (was_cluster_down)
+			err = exynos_cluster_power_control(cluster, 1);
+
+		if (!err)
+			exynos_cpu_power_up(cpunr);
+		else
+			exynos_cluster_power_control(cluster, 0);
+	} else if (cpu_use_count[cpu][cluster] != 2) {
+		/*
+		 * The only possible values are:
+		 * 0 = CPU down
+		 * 1 = CPU (still) up
+		 * 2 = CPU requested to be up before it had a chance
+		 *     to actually make itself down.
+		 * Any other value is a bug.
+		 */
+		BUG();
+	}
+
+	arch_spin_unlock(&exynos_mcpm_lock);
+	local_irq_enable();
+
+	return err;
+}
+
+static void exynos_power_down(void)
+{
+	unsigned int mpidr, cpu, cluster;
+	bool last_man = false, skip_wfi = false;
+	unsigned int cpunr;
+
+	mpidr = read_cpuid_mpidr();
+	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+	cpunr =  cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+			cluster >= EXYNOS5420_NR_CLUSTERS);
+
+	__mcpm_cpu_going_down(cpu, cluster);
+
+	arch_spin_lock(&exynos_mcpm_lock);
+	BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+	cpu_use_count[cpu][cluster]--;
+	if (cpu_use_count[cpu][cluster] == 0) {
+		exynos_cpu_power_down(cpunr);
+
+		if (exynos_cluster_unused(cluster))
+			/* TODO: Turn off the cluster here to save power. */
+			last_man = true;
+	} else if (cpu_use_count[cpu][cluster] == 1) {
+		/*
+		 * A power_up request went ahead of us.
+		 * Even if we do not want to shut this CPU down,
+		 * the caller expects a certain state as if the WFI
+		 * was aborted.  So let's continue with cache cleaning.
+		 */
+		skip_wfi = true;
+	} else {
+		BUG();
+	}
+
+	if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+		arch_spin_unlock(&exynos_mcpm_lock);
+
+		if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
+			/*
+			 * On the Cortex-A15 we need to disable
+			 * L2 prefetching before flushing the cache.
+			 */
+			asm volatile(
+			"mcr	p15, 1, %0, c15, c0, 3\n\t"
+			"isb\n\t"
+			"dsb"
+			: : "r" (0x400));
+		}
+
+		/* Flush all cache levels for this cluster. */
+		exynos_v7_exit_coherency_flush(all);
+
+		/*
+		 * Disable cluster-level coherency by masking
+		 * incoming snoops and DVM messages:
+		 */
+		cci_disable_port_by_cpu(mpidr);
+
+		__mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+	} else {
+		arch_spin_unlock(&exynos_mcpm_lock);
+
+		/* Disable and flush the local CPU cache. */
+		exynos_v7_exit_coherency_flush(louis);
+	}
+
+	__mcpm_cpu_down(cpu, cluster);
+
+	/* Now we are prepared for power-down, do it: */
+	if (!skip_wfi)
+		wfi();
+
+	/* Not dead at this point?  Let our caller cope. */
+}
+
+static int exynos_power_down_finish(unsigned int cpu, unsigned int cluster)
+{
+	unsigned int tries = 100;
+	unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+			cluster >= EXYNOS5420_NR_CLUSTERS);
+
+	/* Wait for the core state to be OFF */
+	while (tries--) {
+		if (ACCESS_ONCE(cpu_use_count[cpu][cluster]) == 0) {
+			if ((exynos_cpu_power_state(cpunr) == 0))
+				return 0; /* success: the CPU is halted */
+		}
+
+		/* Otherwise, wait and retry: */
+		msleep(1);
+	}
+
+	return -ETIMEDOUT; /* timeout */
+}
+
+static const struct mcpm_platform_ops exynos_power_ops = {
+	.power_up		= exynos_power_up,
+	.power_down		= exynos_power_down,
+	.power_down_finish	= exynos_power_down_finish,
+};
+
+static void __init exynos_mcpm_usage_count_init(void)
+{
+	unsigned int mpidr, cpu, cluster;
+
+	mpidr = read_cpuid_mpidr();
+	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER  ||
+			cluster >= EXYNOS5420_NR_CLUSTERS);
+
+	cpu_use_count[cpu][cluster] = 1;
+}
+
+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ */
+static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
+{
+	asm volatile ("\n"
+	"cmp	r0, #1\n"
+	"bxne	lr\n"
+	"b	cci_enable_port_for_self");
+}
+
+static int __init exynos_mcpm_init(void)
+{
+	struct device_node *node;
+	int ret = 0;
+
+	node = of_find_compatible_node(NULL, NULL, "samsung,exynos5420");
+	if (!node)
+		return -ENODEV;
+	of_node_put(node);
+
+	if (!cci_probed())
+		return -ENODEV;
+
+	node = of_find_compatible_node(NULL, NULL,
+			"samsung,exynos4210-sysram-ns");
+	if (!node)
+		return -ENODEV;
+
+	ns_sram_base_addr = of_iomap(node, 0);
+	of_node_put(node);
+	if (!ns_sram_base_addr) {
+		pr_err("failed to map non-secure iRAM base address\n");
+		return -ENOMEM;
+	}
+
+	/*
+	 * To increase the stability of KFC reset we need to program
+	 * the PMU SPARE3 register
+	 */
+	__raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
+
+	exynos_mcpm_usage_count_init();
+
+	ret = mcpm_platform_register(&exynos_power_ops);
+	if (!ret)
+		ret = mcpm_sync_init(exynos_pm_power_up_setup);
+	if (ret) {
+		iounmap(ns_sram_base_addr);
+		return ret;
+	}
+
+	mcpm_smp_set_ops();
+
+	pr_info("Exynos MCPM support installed\n");
+
+	/*
+	 * Future entries into the kernel can now go
+	 * through the cluster entry vectors.
+	 */
+	__raw_writel(virt_to_phys(mcpm_entry_point),
+			ns_sram_base_addr + MCPM_BOOT_ADDR_OFFSET);
+
+	return ret;
+}
+
+early_initcall(exynos_mcpm_init);
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index f6b68a3..4179f6a 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -38,6 +38,7 @@
 #define S5P_INFORM5				S5P_PMUREG(0x0814)
 #define S5P_INFORM6				S5P_PMUREG(0x0818)
 #define S5P_INFORM7				S5P_PMUREG(0x081C)
+#define S5P_PMU_SPARE3				S5P_PMUREG(0x090C)
 
 #define S5P_ARM_CORE0_LOWPWR			S5P_PMUREG(0x1000)
 #define S5P_DIS_IRQ_CORE0			S5P_PMUREG(0x1004)
@@ -322,4 +323,6 @@
 
 #define EXYNOS5_OPTION_USE_RETENTION				(1 << 4)
 
+#define EXYNOS5420_SWRESET_KFC_SEL				0x3
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
-- 
1.7.9.5

[PATCH v6 5/5] arm: exynos: Add MCPM call-back functions

[Lorenzo Pieralisi]

On Tue, May 13, 2014 at 12:58:44PM +0100, Abhilash Kesavan wrote:

[...]

> +static int __init exynos_mcpm_init(void)
> +{
> +       struct device_node *node;
> +       int ret = 0;

There is no point in initializing it to 0.

> +
> +       node = of_find_compatible_node(NULL, NULL, "samsung,exynos5420");
> +       if (!node)
> +               return -ENODEV;
> +       of_node_put(node);
> +
> +       if (!cci_probed())
> +               return -ENODEV;
> +
> +       node = of_find_compatible_node(NULL, NULL,
> +                       "samsung,exynos4210-sysram-ns");
> +       if (!node)
> +               return -ENODEV;
> +
> +       ns_sram_base_addr = of_iomap(node, 0);
> +       of_node_put(node);
> +       if (!ns_sram_base_addr) {
> +               pr_err("failed to map non-secure iRAM base address\n");
> +               return -ENOMEM;
> +       }
> +
> +       /*
> +        * To increase the stability of KFC reset we need to program
> +        * the PMU SPARE3 register
> +        */
> +       __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
> +
> +       exynos_mcpm_usage_count_init();
> +
> +       ret = mcpm_platform_register(&exynos_power_ops);
> +       if (!ret)
> +               ret = mcpm_sync_init(exynos_pm_power_up_setup);
> +       if (ret) {
> +               iounmap(ns_sram_base_addr);
> +               return ret;
> +       }
> +
> +       mcpm_smp_set_ops();
> +
> +       pr_info("Exynos MCPM support installed\n");
> +
> +       /*
> +        * Future entries into the kernel can now go
> +        * through the cluster entry vectors.
> +        */
> +       __raw_writel(virt_to_phys(mcpm_entry_point),
> +                       ns_sram_base_addr + MCPM_BOOT_ADDR_OFFSET);
> +

ns_sram_base_addr must be unmapped, since it is unused after the write.

Lorenzo

> +       return ret;
> +}
> +
> +early_initcall(exynos_mcpm_init);
> diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
> index f6b68a3..4179f6a 100644
> --- a/arch/arm/mach-exynos/regs-pmu.h
> +++ b/arch/arm/mach-exynos/regs-pmu.h
> @@ -38,6 +38,7 @@
>  #define S5P_INFORM5                            S5P_PMUREG(0x0814)
>  #define S5P_INFORM6                            S5P_PMUREG(0x0818)
>  #define S5P_INFORM7                            S5P_PMUREG(0x081C)
> +#define S5P_PMU_SPARE3                         S5P_PMUREG(0x090C)
> 
>  #define S5P_ARM_CORE0_LOWPWR                   S5P_PMUREG(0x1000)
>  #define S5P_DIS_IRQ_CORE0                      S5P_PMUREG(0x1004)
> @@ -322,4 +323,6 @@
> 
>  #define EXYNOS5_OPTION_USE_RETENTION                           (1 << 4)
> 
> +#define EXYNOS5420_SWRESET_KFC_SEL                             0x3
> +
>  #endif /* __ASM_ARCH_REGS_PMU_H */
> --
> 1.7.9.5
> 
> 

[PATCH v6 5/5] arm: exynos: Add MCPM call-back functions

[Abhilash Kesavan]

Hi Lorenzo,

On Tue, May 13, 2014 at 10:18 PM, Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
> On Tue, May 13, 2014 at 12:58:44PM +0100, Abhilash Kesavan wrote:
>
> [...]
>
>> +static int __init exynos_mcpm_init(void)
>> +{
>> +       struct device_node *node;
>> +       int ret = 0;
>
> There is no point in initializing it to 0.
OK.
>
>> +
>> +       node = of_find_compatible_node(NULL, NULL, "samsung,exynos5420");
>> +       if (!node)
>> +               return -ENODEV;
>> +       of_node_put(node);
>> +
>> +       if (!cci_probed())
>> +               return -ENODEV;
>> +
>> +       node = of_find_compatible_node(NULL, NULL,
>> +                       "samsung,exynos4210-sysram-ns");
>> +       if (!node)
>> +               return -ENODEV;
>> +
>> +       ns_sram_base_addr = of_iomap(node, 0);
>> +       of_node_put(node);
>> +       if (!ns_sram_base_addr) {
>> +               pr_err("failed to map non-secure iRAM base address\n");
>> +               return -ENOMEM;
>> +       }
>> +
>> +       /*
>> +        * To increase the stability of KFC reset we need to program
>> +        * the PMU SPARE3 register
>> +        */
>> +       __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
>> +
>> +       exynos_mcpm_usage_count_init();
>> +
>> +       ret = mcpm_platform_register(&exynos_power_ops);
>> +       if (!ret)
>> +               ret = mcpm_sync_init(exynos_pm_power_up_setup);
>> +       if (ret) {
>> +               iounmap(ns_sram_base_addr);
>> +               return ret;
>> +       }
>> +
>> +       mcpm_smp_set_ops();
>> +
>> +       pr_info("Exynos MCPM support installed\n");
>> +
>> +       /*
>> +        * Future entries into the kernel can now go
>> +        * through the cluster entry vectors.
>> +        */
>> +       __raw_writel(virt_to_phys(mcpm_entry_point),
>> +                       ns_sram_base_addr + MCPM_BOOT_ADDR_OFFSET);
>> +
>
> ns_sram_base_addr must be unmapped, since it is unused after the write.
Will unmap.

Regards,
Abhilash

[PATCH v6 5/5] arm: exynos: Add MCPM call-back functions

[Chander Kashyap]

On 14 May 2014 08:14, Abhilash Kesavan <kesavan.abhilash@gmail.com> wrote:
> Hi Lorenzo,
>
> On Tue, May 13, 2014 at 10:18 PM, Lorenzo Pieralisi
> <lorenzo.pieralisi@arm.com> wrote:
>> On Tue, May 13, 2014 at 12:58:44PM +0100, Abhilash Kesavan wrote:
>>
>> [...]
>>
>>> +static int __init exynos_mcpm_init(void)
>>> +{
>>> +       struct device_node *node;
>>> +       int ret = 0;
>>
>> There is no point in initializing it to 0.
> OK.
>>
>>> +
>>> +       node = of_find_compatible_node(NULL, NULL, "samsung,exynos5420");
>>> +       if (!node)
>>> +               return -ENODEV;
>>> +       of_node_put(node);
>>> +
>>> +       if (!cci_probed())
>>> +               return -ENODEV;
>>> +
>>> +       node = of_find_compatible_node(NULL, NULL,
>>> +                       "samsung,exynos4210-sysram-ns");
>>> +       if (!node)
>>> +               return -ENODEV;
>>> +
>>> +       ns_sram_base_addr = of_iomap(node, 0);
>>> +       of_node_put(node);
>>> +       if (!ns_sram_base_addr) {
>>> +               pr_err("failed to map non-secure iRAM base address\n");
>>> +               return -ENOMEM;
>>> +       }
>>> +
>>> +       /*
>>> +        * To increase the stability of KFC reset we need to program
>>> +        * the PMU SPARE3 register
>>> +        */
>>> +       __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
>>> +
>>> +       exynos_mcpm_usage_count_init();
>>> +
>>> +       ret = mcpm_platform_register(&exynos_power_ops);
>>> +       if (!ret)
>>> +               ret = mcpm_sync_init(exynos_pm_power_up_setup);
>>> +       if (ret) {
>>> +               iounmap(ns_sram_base_addr);
>>> +               return ret;
>>> +       }
>>> +
>>> +       mcpm_smp_set_ops();
>>> +
>>> +       pr_info("Exynos MCPM support installed\n");
>>> +
>>> +       /*
>>> +        * Future entries into the kernel can now go
>>> +        * through the cluster entry vectors.
>>> +        */
>>> +       __raw_writel(virt_to_phys(mcpm_entry_point),
>>> +                       ns_sram_base_addr + MCPM_BOOT_ADDR_OFFSET);
>>> +
>>
>> ns_sram_base_addr must be unmapped, since it is unused after the write.
> Will unmap.

This mapping is required in for cpuilde (suspend) to program
mcpm_entry before going to suspend.

>
> Regards,
> Abhilash
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
with warm regards,
Chander Kashyap

[PATCH v6 5/5] arm: exynos: Add MCPM call-back functions

[Abhilash Kesavan]

Hi Chander,

On Wed, May 14, 2014 at 8:24 AM, Chander Kashyap
<chander.kashyap@linaro.org> wrote:
> On 14 May 2014 08:14, Abhilash Kesavan <kesavan.abhilash@gmail.com> wrote:
>> Hi Lorenzo,
>>
>> On Tue, May 13, 2014 at 10:18 PM, Lorenzo Pieralisi
>> <lorenzo.pieralisi@arm.com> wrote:
>>> On Tue, May 13, 2014 at 12:58:44PM +0100, Abhilash Kesavan wrote:
>>>
>>> [...]
>>>
>>>> +static int __init exynos_mcpm_init(void)
>>>> +{
>>>> +       struct device_node *node;
>>>> +       int ret = 0;
>>>
>>> There is no point in initializing it to 0.
>> OK.
>>>
>>>> +
>>>> +       node = of_find_compatible_node(NULL, NULL, "samsung,exynos5420");
>>>> +       if (!node)
>>>> +               return -ENODEV;
>>>> +       of_node_put(node);
>>>> +
>>>> +       if (!cci_probed())
>>>> +               return -ENODEV;
>>>> +
>>>> +       node = of_find_compatible_node(NULL, NULL,
>>>> +                       "samsung,exynos4210-sysram-ns");
>>>> +       if (!node)
>>>> +               return -ENODEV;
>>>> +
>>>> +       ns_sram_base_addr = of_iomap(node, 0);
>>>> +       of_node_put(node);
>>>> +       if (!ns_sram_base_addr) {
>>>> +               pr_err("failed to map non-secure iRAM base address\n");
>>>> +               return -ENOMEM;
>>>> +       }
>>>> +
>>>> +       /*
>>>> +        * To increase the stability of KFC reset we need to program
>>>> +        * the PMU SPARE3 register
>>>> +        */
>>>> +       __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
>>>> +
>>>> +       exynos_mcpm_usage_count_init();
>>>> +
>>>> +       ret = mcpm_platform_register(&exynos_power_ops);
>>>> +       if (!ret)
>>>> +               ret = mcpm_sync_init(exynos_pm_power_up_setup);
>>>> +       if (ret) {
>>>> +               iounmap(ns_sram_base_addr);
>>>> +               return ret;
>>>> +       }
>>>> +
>>>> +       mcpm_smp_set_ops();
>>>> +
>>>> +       pr_info("Exynos MCPM support installed\n");
>>>> +
>>>> +       /*
>>>> +        * Future entries into the kernel can now go
>>>> +        * through the cluster entry vectors.
>>>> +        */
>>>> +       __raw_writel(virt_to_phys(mcpm_entry_point),
>>>> +                       ns_sram_base_addr + MCPM_BOOT_ADDR_OFFSET);
>>>> +
>>>
>>> ns_sram_base_addr must be unmapped, since it is unused after the write.
>> Will unmap.
>
> This mapping is required in for cpuilde (suspend) to program
> mcpm_entry before going to suspend.

I forgot about your cpuidle patches. I need to retain the mapping then.

Abhilash
>
>>
>> Regards,
>> Abhilash
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>
>
> --
> with warm regards,
> Chander Kashyap

[PATCH v6 5/5] arm: exynos: Add MCPM call-back functions

[Nicolas Pitre]

On Wed, 14 May 2014, Chander Kashyap wrote:

> On 14 May 2014 08:14, Abhilash Kesavan <kesavan.abhilash@gmail.com> wrote:
> > Hi Lorenzo,
> >
> > On Tue, May 13, 2014 at 10:18 PM, Lorenzo Pieralisi
> > <lorenzo.pieralisi@arm.com> wrote:
> >> On Tue, May 13, 2014 at 12:58:44PM +0100, Abhilash Kesavan wrote:
> >>
> >> [...]
> >>
> >>> +static int __init exynos_mcpm_init(void)
> >>> +{
> >>> +       struct device_node *node;
> >>> +       int ret = 0;
> >>
> >> There is no point in initializing it to 0.
> > OK.
> >>
> >>> +
> >>> +       node = of_find_compatible_node(NULL, NULL, "samsung,exynos5420");
> >>> +       if (!node)
> >>> +               return -ENODEV;
> >>> +       of_node_put(node);
> >>> +
> >>> +       if (!cci_probed())
> >>> +               return -ENODEV;
> >>> +
> >>> +       node = of_find_compatible_node(NULL, NULL,
> >>> +                       "samsung,exynos4210-sysram-ns");
> >>> +       if (!node)
> >>> +               return -ENODEV;
> >>> +
> >>> +       ns_sram_base_addr = of_iomap(node, 0);
> >>> +       of_node_put(node);
> >>> +       if (!ns_sram_base_addr) {
> >>> +               pr_err("failed to map non-secure iRAM base address\n");
> >>> +               return -ENOMEM;
> >>> +       }
> >>> +
> >>> +       /*
> >>> +        * To increase the stability of KFC reset we need to program
> >>> +        * the PMU SPARE3 register
> >>> +        */
> >>> +       __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
> >>> +
> >>> +       exynos_mcpm_usage_count_init();
> >>> +
> >>> +       ret = mcpm_platform_register(&exynos_power_ops);
> >>> +       if (!ret)
> >>> +               ret = mcpm_sync_init(exynos_pm_power_up_setup);
> >>> +       if (ret) {
> >>> +               iounmap(ns_sram_base_addr);
> >>> +               return ret;
> >>> +       }
> >>> +
> >>> +       mcpm_smp_set_ops();
> >>> +
> >>> +       pr_info("Exynos MCPM support installed\n");
> >>> +
> >>> +       /*
> >>> +        * Future entries into the kernel can now go
> >>> +        * through the cluster entry vectors.
> >>> +        */
> >>> +       __raw_writel(virt_to_phys(mcpm_entry_point),
> >>> +                       ns_sram_base_addr + MCPM_BOOT_ADDR_OFFSET);
> >>> +
> >>
> >> ns_sram_base_addr must be unmapped, since it is unused after the write.
> > Will unmap.
> 
> This mapping is required in for cpuilde (suspend) to program
> mcpm_entry before going to suspend.

Why?


Nicolas

[PATCH v6 5/5] arm: exynos: Add MCPM call-back functions

[Chander Kashyap]

On 14 May 2014 08:32, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> On Wed, 14 May 2014, Chander Kashyap wrote:
>
>> On 14 May 2014 08:14, Abhilash Kesavan <kesavan.abhilash@gmail.com> wrote:
>> > Hi Lorenzo,
>> >
>> > On Tue, May 13, 2014 at 10:18 PM, Lorenzo Pieralisi
>> > <lorenzo.pieralisi@arm.com> wrote:
>> >> On Tue, May 13, 2014 at 12:58:44PM +0100, Abhilash Kesavan wrote:
>> >>
>> >> [...]
>> >>
>> >>> +static int __init exynos_mcpm_init(void)
>> >>> +{
>> >>> +       struct device_node *node;
>> >>> +       int ret = 0;
>> >>
>> >> There is no point in initializing it to 0.
>> > OK.
>> >>
>> >>> +
>> >>> +       node = of_find_compatible_node(NULL, NULL, "samsung,exynos5420");
>> >>> +       if (!node)
>> >>> +               return -ENODEV;
>> >>> +       of_node_put(node);
>> >>> +
>> >>> +       if (!cci_probed())
>> >>> +               return -ENODEV;
>> >>> +
>> >>> +       node = of_find_compatible_node(NULL, NULL,
>> >>> +                       "samsung,exynos4210-sysram-ns");
>> >>> +       if (!node)
>> >>> +               return -ENODEV;
>> >>> +
>> >>> +       ns_sram_base_addr = of_iomap(node, 0);
>> >>> +       of_node_put(node);
>> >>> +       if (!ns_sram_base_addr) {
>> >>> +               pr_err("failed to map non-secure iRAM base address\n");
>> >>> +               return -ENOMEM;
>> >>> +       }
>> >>> +
>> >>> +       /*
>> >>> +        * To increase the stability of KFC reset we need to program
>> >>> +        * the PMU SPARE3 register
>> >>> +        */
>> >>> +       __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
>> >>> +
>> >>> +       exynos_mcpm_usage_count_init();
>> >>> +
>> >>> +       ret = mcpm_platform_register(&exynos_power_ops);
>> >>> +       if (!ret)
>> >>> +               ret = mcpm_sync_init(exynos_pm_power_up_setup);
>> >>> +       if (ret) {
>> >>> +               iounmap(ns_sram_base_addr);
>> >>> +               return ret;
>> >>> +       }
>> >>> +
>> >>> +       mcpm_smp_set_ops();
>> >>> +
>> >>> +       pr_info("Exynos MCPM support installed\n");
>> >>> +
>> >>> +       /*
>> >>> +        * Future entries into the kernel can now go
>> >>> +        * through the cluster entry vectors.
>> >>> +        */
>> >>> +       __raw_writel(virt_to_phys(mcpm_entry_point),
>> >>> +                       ns_sram_base_addr + MCPM_BOOT_ADDR_OFFSET);
>> >>> +
>> >>
>> >> ns_sram_base_addr must be unmapped, since it is unused after the write.
>> > Will unmap.
>>
>> This mapping is required in for cpuilde (suspend) to program
>> mcpm_entry before going to suspend.
>
> Why?

This is required to program the mcpm_entry point address (resume
address) after cpuidle exit/fail.

Abhilash, as i am not clearing it, it can be unmapped.

Thanks Nicolas.


>
>
> Nicolas
>



-- 
with warm regards,
Chander Kashyap

[PATCH v6 5/5] arm: exynos: Add MCPM call-back functions

[Nicolas Pitre]

On Wed, 14 May 2014, Chander Kashyap wrote:
> On 14 May 2014 08:32, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> > On Wed, 14 May 2014, Chander Kashyap wrote:
> >> On 14 May 2014 08:14, Abhilash Kesavan <kesavan.abhilash@gmail.com> wrote:
> >> > On Tue, May 13, 2014 at 10:18 PM, Lorenzo Pieralisi
> >> > <lorenzo.pieralisi@arm.com> wrote:
> >> >> On Tue, May 13, 2014 at 12:58:44PM +0100, Abhilash Kesavan wrote:
> >> >>
> >> >>> +       /*
> >> >>> +        * Future entries into the kernel can now go
> >> >>> +        * through the cluster entry vectors.
> >> >>> +        */
> >> >>> +       __raw_writel(virt_to_phys(mcpm_entry_point),
> >> >>> +                       ns_sram_base_addr + MCPM_BOOT_ADDR_OFFSET);
> >> >>> +
> >> >>
> >> >> ns_sram_base_addr must be unmapped, since it is unused after the write.
> >> > Will unmap.
> >>
> >> This mapping is required in for cpuilde (suspend) to program
> >> mcpm_entry before going to suspend.
> >
> > Why?
> 
> This is required to program the mcpm_entry point address (resume
> address) after cpuidle exit/fail.

You should be using mcpm_set_entry_vector() for that.  Once 
mcpm_entry_point is set, it shouldn't need to be changed.


Nicolas

[PATCH v7 5/5] arm: exynos: Add MCPM call-back functions

[Abhilash Kesavan]

Add machine-dependent MCPM call-backs for Exynos5420. These are used
to power up/down the secondary CPUs during boot, shutdown, s2r and
switching.

Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Inderpal Singh <inderpal.s@samsung.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org>
---
Changes since v6:
Addressed the following comments from Lorenzo Pieralisi:
  - Added a comment for the power down function suggested by Lorenzo.
  - Unmapped the non-secure sram region after use.
  - Removed unnecessary variable initialization.

 arch/arm/mach-exynos/Kconfig       |    8 +
 arch/arm/mach-exynos/Makefile      |    2 +
 arch/arm/mach-exynos/mcpm-exynos.c |  351 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/regs-pmu.h    |    3 +
 4 files changed, 364 insertions(+)
 create mode 100644 arch/arm/mach-exynos/mcpm-exynos.c

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index fc8bf18..1602abc 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -110,4 +110,12 @@ config SOC_EXYNOS5440
 
 endmenu
 
+config EXYNOS5420_MCPM
+	bool "Exynos5420 Multi-Cluster PM support"
+	depends on MCPM && SOC_EXYNOS5420
+	select ARM_CCI
+	help
+	  This is needed to provide CPU and cluster power management
+	  on Exynos5420 implementing big.LITTLE.
+
 endif
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index f6dcc25..2e0666d 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -24,3 +24,5 @@ obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_exynos-smc.o		:=-Wa,-march=armv7-a$(plus_sec)
+
+obj-$(CONFIG_EXYNOS5420_MCPM)	+= mcpm-exynos.o
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
new file mode 100644
index 0000000..7d271e7
--- /dev/null
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -0,0 +1,351 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * arch/arm/mach-exynos/mcpm-exynos.c
+ *
+ * Based on arch/arm/mach-vexpress/dcscb.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/arm-cci.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+#include <asm/mcpm.h>
+
+#include "regs-pmu.h"
+#include "common.h"
+
+#define EXYNOS5420_CPUS_PER_CLUSTER	4
+#define EXYNOS5420_NR_CLUSTERS		2
+#define MCPM_BOOT_ADDR_OFFSET		0x1c
+
+/*
+ * The common v7_exit_coherency_flush API could not be used because of the
+ * Erratum 799270 workaround. This macro is the same as the common one (in
+ * arch/arm/include/asm/cacheflush.h) except for the erratum handling.
+ */
+#define exynos_v7_exit_coherency_flush(level) \
+	asm volatile( \
+	"stmfd	sp!, {fp, ip}\n\t"\
+	"mrc	p15, 0, r0, c1, c0, 0	@ get SCTLR\n\t" \
+	"bic	r0, r0, #"__stringify(CR_C)"\n\t" \
+	"mcr	p15, 0, r0, c1, c0, 0	@ set SCTLR\n\t" \
+	"isb\n\t"\
+	"bl	v7_flush_dcache_"__stringify(level)"\n\t" \
+	"clrex\n\t"\
+	"mrc	p15, 0, r0, c1, c0, 1	@ get ACTLR\n\t" \
+	"bic	r0, r0, #(1 << 6)	@ disable local coherency\n\t" \
+	/* Dummy Load of a device register to avoid Erratum 799270 */ \
+	"ldr	r4, [%0]\n\t" \
+	"and	r4, r4, #0\n\t" \
+	"orr	r0, r0, r4\n\t" \
+	"mcr	p15, 0, r0, c1, c0, 1	@ set ACTLR\n\t" \
+	"isb\n\t" \
+	"dsb\n\t" \
+	"ldmfd	sp!, {fp, ip}" \
+	: \
+	: "Ir" (S5P_INFORM0) \
+	: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
+	  "r9", "r10", "lr", "memory")
+
+/*
+ * We can't use regular spinlocks. In the switcher case, it is possible
+ * for an outbound CPU to call power_down() after its inbound counterpart
+ * is already live using the same logical CPU number which trips lockdep
+ * debugging.
+ */
+static arch_spinlock_t exynos_mcpm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+static int
+cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS];
+
+#define exynos_cluster_usecnt(cluster) \
+	(cpu_use_count[0][cluster] +   \
+	 cpu_use_count[1][cluster] +   \
+	 cpu_use_count[2][cluster] +   \
+	 cpu_use_count[3][cluster])
+
+#define exynos_cluster_unused(cluster) !exynos_cluster_usecnt(cluster)
+
+static int exynos_cluster_power_control(unsigned int cluster, int enable)
+{
+	unsigned int tries = 100;
+	unsigned int val;
+
+	if (enable) {
+		exynos_cluster_power_up(cluster);
+		val = S5P_CORE_LOCAL_PWR_EN;
+	} else {
+		exynos_cluster_power_down(cluster);
+		val = 0;
+	}
+
+	/* Wait until cluster power control is applied */
+	while (tries--) {
+		if (exynos_cluster_power_state(cluster) == val)
+			return 0;
+
+		cpu_relax();
+	}
+	pr_debug("timed out waiting for cluster %u to power %s\n", cluster,
+		enable ? "on" : "off");
+
+	return -ETIMEDOUT;
+}
+
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+	unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+	int err = 0;
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+		cluster >= EXYNOS5420_NR_CLUSTERS)
+		return -EINVAL;
+
+	/*
+	 * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+	 * variant exists, we need to disable IRQs manually here.
+	 */
+	local_irq_disable();
+	arch_spin_lock(&exynos_mcpm_lock);
+
+	cpu_use_count[cpu][cluster]++;
+	if (cpu_use_count[cpu][cluster] == 1) {
+		bool was_cluster_down =
+			(exynos_cluster_usecnt(cluster) == 1);
+
+		/*
+		 * Turn on the cluster (L2/COMMON) and then power on the
+		 * cores.
+		 */
+		if (was_cluster_down)
+			err = exynos_cluster_power_control(cluster, 1);
+
+		if (!err)
+			exynos_cpu_power_up(cpunr);
+		else
+			exynos_cluster_power_control(cluster, 0);
+	} else if (cpu_use_count[cpu][cluster] != 2) {
+		/*
+		 * The only possible values are:
+		 * 0 = CPU down
+		 * 1 = CPU (still) up
+		 * 2 = CPU requested to be up before it had a chance
+		 *     to actually make itself down.
+		 * Any other value is a bug.
+		 */
+		BUG();
+	}
+
+	arch_spin_unlock(&exynos_mcpm_lock);
+	local_irq_enable();
+
+	return err;
+}
+
+/*
+ * NOTE: This function requires the stack data to be visible through power down
+ * and can only be executed on processors like A15 and A7 that hit the cache
+ * with the C bit clear in the SCTLR register.
+ */
+static void exynos_power_down(void)
+{
+	unsigned int mpidr, cpu, cluster;
+	bool last_man = false, skip_wfi = false;
+	unsigned int cpunr;
+
+	mpidr = read_cpuid_mpidr();
+	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+	cpunr =  cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+			cluster >= EXYNOS5420_NR_CLUSTERS);
+
+	__mcpm_cpu_going_down(cpu, cluster);
+
+	arch_spin_lock(&exynos_mcpm_lock);
+	BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+	cpu_use_count[cpu][cluster]--;
+	if (cpu_use_count[cpu][cluster] == 0) {
+		exynos_cpu_power_down(cpunr);
+
+		if (exynos_cluster_unused(cluster))
+			/* TODO: Turn off the cluster here to save power. */
+			last_man = true;
+	} else if (cpu_use_count[cpu][cluster] == 1) {
+		/*
+		 * A power_up request went ahead of us.
+		 * Even if we do not want to shut this CPU down,
+		 * the caller expects a certain state as if the WFI
+		 * was aborted.  So let's continue with cache cleaning.
+		 */
+		skip_wfi = true;
+	} else {
+		BUG();
+	}
+
+	if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+		arch_spin_unlock(&exynos_mcpm_lock);
+
+		if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
+			/*
+			 * On the Cortex-A15 we need to disable
+			 * L2 prefetching before flushing the cache.
+			 */
+			asm volatile(
+			"mcr	p15, 1, %0, c15, c0, 3\n\t"
+			"isb\n\t"
+			"dsb"
+			: : "r" (0x400));
+		}
+
+		/* Flush all cache levels for this cluster. */
+		exynos_v7_exit_coherency_flush(all);
+
+		/*
+		 * Disable cluster-level coherency by masking
+		 * incoming snoops and DVM messages:
+		 */
+		cci_disable_port_by_cpu(mpidr);
+
+		__mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+	} else {
+		arch_spin_unlock(&exynos_mcpm_lock);
+
+		/* Disable and flush the local CPU cache. */
+		exynos_v7_exit_coherency_flush(louis);
+	}
+
+	__mcpm_cpu_down(cpu, cluster);
+
+	/* Now we are prepared for power-down, do it: */
+	if (!skip_wfi)
+		wfi();
+
+	/* Not dead at this point?  Let our caller cope. */
+}
+
+static int exynos_power_down_finish(unsigned int cpu, unsigned int cluster)
+{
+	unsigned int tries = 100;
+	unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+			cluster >= EXYNOS5420_NR_CLUSTERS);
+
+	/* Wait for the core state to be OFF */
+	while (tries--) {
+		if (ACCESS_ONCE(cpu_use_count[cpu][cluster]) == 0) {
+			if ((exynos_cpu_power_state(cpunr) == 0))
+				return 0; /* success: the CPU is halted */
+		}
+
+		/* Otherwise, wait and retry: */
+		msleep(1);
+	}
+
+	return -ETIMEDOUT; /* timeout */
+}
+
+static const struct mcpm_platform_ops exynos_power_ops = {
+	.power_up		= exynos_power_up,
+	.power_down		= exynos_power_down,
+	.power_down_finish	= exynos_power_down_finish,
+};
+
+static void __init exynos_mcpm_usage_count_init(void)
+{
+	unsigned int mpidr, cpu, cluster;
+
+	mpidr = read_cpuid_mpidr();
+	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER  ||
+			cluster >= EXYNOS5420_NR_CLUSTERS);
+
+	cpu_use_count[cpu][cluster] = 1;
+}
+
+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ */
+static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
+{
+	asm volatile ("\n"
+	"cmp	r0, #1\n"
+	"bxne	lr\n"
+	"b	cci_enable_port_for_self");
+}
+
+static int __init exynos_mcpm_init(void)
+{
+	struct device_node *node;
+	void __iomem *ns_sram_base_addr;
+	int ret;
+
+	node = of_find_compatible_node(NULL, NULL, "samsung,exynos5420");
+	if (!node)
+		return -ENODEV;
+	of_node_put(node);
+
+	if (!cci_probed())
+		return -ENODEV;
+
+	node = of_find_compatible_node(NULL, NULL,
+			"samsung,exynos4210-sysram-ns");
+	if (!node)
+		return -ENODEV;
+
+	ns_sram_base_addr = of_iomap(node, 0);
+	of_node_put(node);
+	if (!ns_sram_base_addr) {
+		pr_err("failed to map non-secure iRAM base address\n");
+		return -ENOMEM;
+	}
+
+	/*
+	 * To increase the stability of KFC reset we need to program
+	 * the PMU SPARE3 register
+	 */
+	__raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
+
+	exynos_mcpm_usage_count_init();
+
+	ret = mcpm_platform_register(&exynos_power_ops);
+	if (!ret)
+		ret = mcpm_sync_init(exynos_pm_power_up_setup);
+	if (ret) {
+		iounmap(ns_sram_base_addr);
+		return ret;
+	}
+
+	mcpm_smp_set_ops();
+
+	pr_info("Exynos MCPM support installed\n");
+
+	/*
+	 * Future entries into the kernel can now go
+	 * through the cluster entry vectors.
+	 */
+	__raw_writel(virt_to_phys(mcpm_entry_point),
+			ns_sram_base_addr + MCPM_BOOT_ADDR_OFFSET);
+
+	iounmap(ns_sram_base_addr);
+
+	return ret;
+}
+
+early_initcall(exynos_mcpm_init);
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index f6b68a3..4179f6a 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -38,6 +38,7 @@
 #define S5P_INFORM5				S5P_PMUREG(0x0814)
 #define S5P_INFORM6				S5P_PMUREG(0x0818)
 #define S5P_INFORM7				S5P_PMUREG(0x081C)
+#define S5P_PMU_SPARE3				S5P_PMUREG(0x090C)
 
 #define S5P_ARM_CORE0_LOWPWR			S5P_PMUREG(0x1000)
 #define S5P_DIS_IRQ_CORE0			S5P_PMUREG(0x1004)
@@ -322,4 +323,6 @@
 
 #define EXYNOS5_OPTION_USE_RETENTION				(1 << 4)
 
+#define EXYNOS5420_SWRESET_KFC_SEL				0x3
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
-- 
1.7.9.5

[PATCH v6 0/5] MCPM backend for Exynos5420

[Nicolas Pitre]

On Tue, 13 May 2014, Abhilash Kesavan wrote:

> This is v6 of the series adding MCPM backend support for SMP secondary boot
> and core switching on Samsung's Exynos5420. The patches are based on the mcpm
> support added for Exynos5420 in the Chromium kernel repository here:
> https://chromium.googlesource.com/chromiumos/third_party/kernel-next/+/chromeos-3.8
> 
> The patches have been prepared on Kukjin Kim's for-next branch and tested on
> SMDK5420 EVT1 as well as an exynos5420 based chromebook (peach-pit) using the
> "/dev/b.L_switcher" user interface. Secondary core boot-up has also been tested
> on both the boards.

OK... Now it is time for real testing.  :-)

The /dev/b.L_switcher interface tests the switcher.  Here you really 
want to hammer the MCPM functionalities and especially your backend code 
as hard as possible.  I therefore recommend the following test script:

---------- >8
#!/bin/bash

echo 0 >/sys/kernel/bL_switcher/active
sleep 1

pids=
for cpu in /sys/devices/system/cpu/cpu?/online; do
  { cpu_nr=${cpu:27:1}
    while true; do
      echo 1 > $cpu 2> /dev/null
      sleep .00$RANDOM
      val1=$(cat $cpu)
      echo 0 > $cpu 2> /dev/null
      sleep .00$RANDOM
      val0=$(cat $cpu)
      [ "$val1" = "1" -a "$val0" = "0" ] && echo -n $cpu_nr
    done
  } &
  pids="$pids $!"
done

trap "kill $pids; echo" 0 15
wait $pids
---------- >8

Leave this running for a couple hours making sure you see all CPU 
numbers being printed.  The printing order will be random, but each CPU 
number should continuously appear.


Nicolas

[PATCH v6 0/5] MCPM backend for Exynos5420

[Abhilash Kesavan]

Hi Nicolas,

On Tue, May 13, 2014 at 11:25 PM, Nicolas Pitre
<nicolas.pitre@linaro.org> wrote:
> On Tue, 13 May 2014, Abhilash Kesavan wrote:
>
>> This is v6 of the series adding MCPM backend support for SMP secondary boot
>> and core switching on Samsung's Exynos5420. The patches are based on the mcpm
>> support added for Exynos5420 in the Chromium kernel repository here:
>> https://chromium.googlesource.com/chromiumos/third_party/kernel-next/+/chromeos-3.8
>>
>> The patches have been prepared on Kukjin Kim's for-next branch and tested on
>> SMDK5420 EVT1 as well as an exynos5420 based chromebook (peach-pit) using the
>> "/dev/b.L_switcher" user interface. Secondary core boot-up has also been tested
>> on both the boards.
>
> OK... Now it is time for real testing.  :-)
>
> The /dev/b.L_switcher interface tests the switcher.  Here you really
> want to hammer the MCPM functionalities and especially your backend code
> as hard as possible.  I therefore recommend the following test script:
>
> ---------- >8
> #!/bin/bash
>
> echo 0 >/sys/kernel/bL_switcher/active
> sleep 1
>
> pids=
> for cpu in /sys/devices/system/cpu/cpu?/online; do
>   { cpu_nr=${cpu:27:1}
>     while true; do
>       echo 1 > $cpu 2> /dev/null
>       sleep .00$RANDOM
>       val1=$(cat $cpu)
>       echo 0 > $cpu 2> /dev/null
>       sleep .00$RANDOM
>       val0=$(cat $cpu)
>       [ "$val1" = "1" -a "$val0" = "0" ] && echo -n $cpu_nr
>     done
>   } &
>   pids="$pids $!"
> done
>
> trap "kill $pids; echo" 0 15
> wait $pids
> ---------- >8
>
> Leave this running for a couple hours making sure you see all CPU
> numbers being printed.  The printing order will be random, but each CPU
> number should continuously appear.
I tried this script and I get two errors:

1) can't create /sys/devices/system/cpu/cpu//online: nonexistent directory
2) sleep: invalid number '.0026736'


For 1) the cpu number is not being appended. if I give a particular
cpu in the script then hotplug in/out works fine.
For 2) a constant msleep 10 works.

Is it OK for me to modify the script to hotplug in/off a randomly chosed core ?

Regards,
Abhilash
>
>
> Nicolas

[PATCH v6 0/5] MCPM backend for Exynos5420

[Nicolas Pitre]

On Wed, 14 May 2014, Abhilash Kesavan wrote:

> Hi Nicolas,
> 
> On Tue, May 13, 2014 at 11:25 PM, Nicolas Pitre
> <nicolas.pitre@linaro.org> wrote:
> > On Tue, 13 May 2014, Abhilash Kesavan wrote:
> >
> >> This is v6 of the series adding MCPM backend support for SMP secondary boot
> >> and core switching on Samsung's Exynos5420. The patches are based on the mcpm
> >> support added for Exynos5420 in the Chromium kernel repository here:
> >> https://chromium.googlesource.com/chromiumos/third_party/kernel-next/+/chromeos-3.8
> >>
> >> The patches have been prepared on Kukjin Kim's for-next branch and tested on
> >> SMDK5420 EVT1 as well as an exynos5420 based chromebook (peach-pit) using the
> >> "/dev/b.L_switcher" user interface. Secondary core boot-up has also been tested
> >> on both the boards.
> >
> > OK... Now it is time for real testing.  :-)
> >
> > The /dev/b.L_switcher interface tests the switcher.  Here you really
> > want to hammer the MCPM functionalities and especially your backend code
> > as hard as possible.  I therefore recommend the following test script:
> >
> > ---------- >8
> > #!/bin/bash
> >
> > echo 0 >/sys/kernel/bL_switcher/active
> > sleep 1
> >
> > pids=
> > for cpu in /sys/devices/system/cpu/cpu?/online; do
> >   { cpu_nr=${cpu:27:1}
> >     while true; do
> >       echo 1 > $cpu 2> /dev/null
> >       sleep .00$RANDOM
> >       val1=$(cat $cpu)
> >       echo 0 > $cpu 2> /dev/null
> >       sleep .00$RANDOM
> >       val0=$(cat $cpu)
> >       [ "$val1" = "1" -a "$val0" = "0" ] && echo -n $cpu_nr
> >     done
> >   } &
> >   pids="$pids $!"
> > done
> >
> > trap "kill $pids; echo" 0 15
> > wait $pids
> > ---------- >8
> >
> > Leave this running for a couple hours making sure you see all CPU
> > numbers being printed.  The printing order will be random, but each CPU
> > number should continuously appear.
> I tried this script and I get two errors:
> 
> 1) can't create /sys/devices/system/cpu/cpu//online: nonexistent directory

What do you get if you do:

$ ls -d /sys/devices/system/cpu/cpu?/online

?

> 2) sleep: invalid number '.0026736'

A sufficiently recent coreutils package should have a sleep command that 
accepts fractional values.  Alternatively you may replace it with 
usleep:

	usleep $RANDOM

> For 1) the cpu number is not being appended. if I give a particular
> cpu in the script then hotplug in/out works fine.
> For 2) a constant msleep 10 works.

If you have msleep but not usleep then try:

		msleep $(($RANDOM / 1000))

> Is it OK for me to modify the script to hotplug in/off a randomly chosed core ?

No.  They must *all* be hotplugged simultaneously with some random 
timing.


Nicolas

[PATCH v6 0/5] MCPM backend for Exynos5420

[Abhilash Kesavan]

Hi Nicolas,

[...]
>>
>> 1) can't create /sys/devices/system/cpu/cpu//online: nonexistent directory
>
> What do you get if you do:
>
> $ ls -d /sys/devices/system/cpu/cpu?/online
ls: /sys/devices/system/cpu/cpu//online: No such file or directory
>
> ?
>
>> 2) sleep: invalid number '.0026736'
>
> A sufficiently recent coreutils package should have a sleep command that
> accepts fractional values.  Alternatively you may replace it with
> usleep:
>
>         usleep $RANDOM
Looks like my cramfs needs an update, it seems to have old packages.
>
>> For 1) the cpu number is not being appended. if I give a particular
>> cpu in the script then hotplug in/out works fine.
>> For 2) a constant msleep 10 works.
>
> If you have msleep but not usleep then try:
>
>                 msleep $(($RANDOM / 1000))
I have msleep present.
>
>> Is it OK for me to modify the script to hotplug in/off a randomly chosed core ?
>
> No.  They must *all* be hotplugged simultaneously with some random
> timing.
OK.

Regards,
Abhilash

[PATCH v6 0/5] MCPM backend for Exynos5420

[Nicolas Pitre]

On Wed, 14 May 2014, Abhilash Kesavan wrote:

> Hi Nicolas,
> 
> [...]
> >>
> >> 1) can't create /sys/devices/system/cpu/cpu//online: nonexistent directory
> >
> > What do you get if you do:
> >
> > $ ls -d /sys/devices/system/cpu/cpu?/online
> ls: /sys/devices/system/cpu/cpu//online: No such file or directory

Somehow, you or your shell replaced the ? character into a / character.
You could try with a * instead.


Nicolas

[PATCH v6 0/5] MCPM backend for Exynos5420

[Abhilash Kesavan]

Hi Nicolas,

On Wed, May 14, 2014 at 7:03 PM, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> On Wed, 14 May 2014, Abhilash Kesavan wrote:
>
>> Hi Nicolas,
>>
>> [...]
>> >>
>> >> 1) can't create /sys/devices/system/cpu/cpu//online: nonexistent directory
>> >
>> > What do you get if you do:
>> >
>> > $ ls -d /sys/devices/system/cpu/cpu?/online
>> ls: /sys/devices/system/cpu/cpu//online: No such file or directory
>
> Somehow, you or your shell replaced the ? character into a / character.
> You could try with a * instead.
With a different RFS your script runs fine without any change. Will
update with results once testing is done.

Abhilash
>
>
> Nicolas

[PATCH v6 0/5] MCPM backend for Exynos5420

[Abhilash Kesavan]

Hi Nicolas,

On Wed, May 14, 2014 at 7:09 PM, Abhilash Kesavan
<kesavan.abhilash@gmail.com> wrote:
> Hi Nicolas,
>
> On Wed, May 14, 2014 at 7:03 PM, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
>> On Wed, 14 May 2014, Abhilash Kesavan wrote:
>>
>>> Hi Nicolas,
>>>
>>> [...]
>>> >>
>>> >> 1) can't create /sys/devices/system/cpu/cpu//online: nonexistent directory
>>> >
>>> > What do you get if you do:
>>> >
>>> > $ ls -d /sys/devices/system/cpu/cpu?/online
>>> ls: /sys/devices/system/cpu/cpu//online: No such file or directory
>>
>> Somehow, you or your shell replaced the ? character into a / character.
>> You could try with a * instead.
> With a different RFS your script runs fine without any change. Will
> update with results once testing is done.
The script has been running for a few hours on my 5420 based
chromebook. I can see all the cores being hotplugged in/out. A snippet
of the prints, that I get on running the test, follows:

===========================================
[ 2408.454198] CPU4: Booted secondary processor
[ 2408.461468] CPU6: Booted secondary processor
[ 2408.466306] CPU2: Booted secondary processor
[ 2408.527229] CPU7: shutdown
[ 2408.571822] CPU3: shutdown
[ 2408.611762] CPU1: shutdown
[ 2408.647230] CPU6: shutdown
027316[ 2408.686885] CPU2: shutdown
[ 2408.691756] CPU3: Booted secondary processor
[ 2408.696468] CPU0: Booted secondary processor
2[ 2408.705123] CPU2: Booted secondary processor
[ 2408.747231] CPU4: shutdown
4[ 2408.776798] CPU3: shutdown
[ 2408.786452] CPU4: Booted secondary processor
[ 2408.796497] CPU1: Booted secondary processor
3[ 2408.852188] CPU4: shutdown
[ 2408.856478] CPU7: Booted secondary processor
[ 2408.861457] CPU5: Booted secondary processor
4[ 2408.865536] CPU4: Booted secondary processor
[ 2408.921844] CPU1: shutdown
[ 2408.926486] CPU6: Booted secondary processor
[ 2408.931539] CPU3: Booted secondary processor
1[ 2408.967235] CPU7: shutdown
7[ 2409.011792] CPU3: shutdown
[ 2409.016529] CPU1: Booted secondary processor
3[ 2409.082196] CPU6: shutdown
6[ 2409.126847] CPU0: shutdown
[ 2409.172204] CPU4: shutdown
[ 2409.176441] CPU7: Booted secondary processor
04[ 2409.226786] CPU2: shutdown
[ 2409.229347] CPU4: Booted secondary processor
2[ 2409.272214] CPU7: shutdown
[ 2409.276462] CPU0: Booted secondary processor
7[ 2409.317145] CPU5: shutdown
[ 2409.321589] CPU3: Booted secondary processor
[ 2409.326465] CPU7: Booted secondary processor
[ 2409.331456] CPU2: Booted secondary processor
5[ 2409.335634] CPU5: Booted secondary processor
[ 2409.382202] CPU4: shutdown
4[ 2409.421861] CPU1: shutdown
[ 2409.461784] CPU2: shutdown
[ 2409.466485] CPU6: Booted secondary processor
1[ 2409.471381] CPU1: Booted secondary processor
2[ 2409.522210] CPU5: shutdown
5[ 2409.582098] CPU7: shutdown
[ 2409.586421] CPU2: Booted secondary processor
7[ 2409.642135] CPU6: shutdown
6[ 2409.681787] CPU1: shutdown
1[ 2409.716719] CPU0: shutdown
[ 2409.721476] CPU7: Booted secondary processor
[ 2409.726454] CPU5: Booted secondary processor
0[ 2409.731046] CPU0: Booted secondary processor
[ 2409.736473] CPU1: Booted secondary processor
[ 2409.772226] CPU7: shutdown
7[ 2409.816833] CPU3: shutdown
[ 2409.821472] CPU4: Booted secondary processor
3[ 2409.871810] CPU0: shutdown
[ 2409.912194] CPU4: shutdown
[ 2409.957127] CPU5: shutdown
[ 2409.961456] CPU6: Booted secondary processor
[ 2409.966447] CPU3: Booted secondary processor
[ 2409.970816] CPU5: Booted secondary processor
[ 2410.011828] CPU2: shutdown
[ 2410.041787] CPU1: shutdown
[ 2410.044138] CPU2: Booted secondary processor
0452[ 2410.047629] CPU0: Booted secondary processor
[ 2410.056582] CPU4: Booted secondary processor
[ 2410.060400] CPU1: Booted secondary processor
1[ 2410.116858] CPU2: shutdown
[ 2410.121472] CPU7: Booted secondary processor
2[ 2410.176838] CPU1: shutdown
[ 2410.181614] CPU2: Booted secondary processor
1[ 2410.237224] CPU4: shutdown
4[ 2410.286853] CPU2: shutdown
[ 2410.291472] CPU4: Booted secondary processor
2[ 2410.341767] CPU3: shutdown
[ 2410.346579] CPU1: Booted secondary processor
[ 2410.351585] CPU2: Booted secondary processor
3[ 2410.387251] CPU7: shutdown
7[ 2410.426854] CPU1: shutdown
1[ 2410.477217] CPU5: shutdown
5[ 2410.526810] CPU0: shutdown
[ 2410.529108] CPU7: Booted secondary processor
[ 2410.536432] CPU1: Booted secondary processor
[ 2410.592173] CPU7: shutdown
[ 2410.637141] CPU4: shutdown
[ 2410.641459] CPU7: Booted secondary processor
07[ 2410.646392] CPU0: Booted secondary processor
4[ 2410.652206] CPU4: Booted secondary processor
[ 2410.701872] CPU1: shutdown
1[ 2410.746764] CPU0: shutdown
[ 2410.751481] CPU5: Booted secondary processor
[ 2410.756512] CPU1: Booted secondary processor
[ 2410.761505] CPU3: Booted secondary processor
[ 2410.812331] CPU7: shutdown
[ 2410.851841] CPU3: shutdown
[ 2410.854089] CPU7: Booted secondary processor
[ 2410.902210] CPU6: shutdown
[ 2410.906476] CPU3: Booted secondary processor
[ 2410.961858] CPU2: shutdown
07362[ 2411.011814] CPU3: shutdown
[ 2411.016561] CPU2: Booted secondary processor
3[ 2411.057255] CPU4: shutdown
[ 2411.061626] CPU6: Booted secondary processor
4[ 2411.111898] CPU2: shutdown
[ 2411.116443] CPU4: Booted secondary processor
2[ 2411.166769] CPU1: shutdown
[ 2411.170693] CPU3: Booted secondary processor
[ 2411.222264] CPU7: shutdown
[ 2411.262199] CPU5: shutdown
17[ 2411.266511] CPU1: Booted secondary processor
[ 2411.271614] CPU2: Booted secondary processor
5[ 2411.327240] CPU4: shutdown
[ 2411.331394] CPU0: Booted secondary processor
4[ 2411.381868] CPU1: shutdown
1[ 2411.426780] CPU3: shutdown
[ 2411.431477] CPU5: Booted secondary processor
3[ 2411.441362] CPU3: Booted secondary processor
[ 2411.492221] CPU5: shutdown
[ 2411.501452] CPU1: Booted secondary processor
[ 2411.505211] CPU5: Booted secondary processor
5[ 2411.511488] CPU4: Booted secondary processor
[ 2411.566926] CPU0: shutdown
[ 2411.612216] CPU5: shutdown
0[ 2411.616661] CPU0: Booted secondary processor
[ 2411.621520] CPU7: Booted secondary processor
5[ 2411.628604] CPU5: Booted secondary processor
===========================================

Is there anything else that needs to be checked to ensure that the
script is running as expected ?

Regards,
Abhilash

[PATCH v6 0/5] MCPM backend for Exynos5420

[Nicolas Pitre]

On Thu, 15 May 2014, Abhilash Kesavan wrote:

> Hi Nicolas,
> 
> On Wed, May 14, 2014 at 7:09 PM, Abhilash Kesavan
> <kesavan.abhilash@gmail.com> wrote:
> > Hi Nicolas,
> >
> > On Wed, May 14, 2014 at 7:03 PM, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> >> On Wed, 14 May 2014, Abhilash Kesavan wrote:
> >>
> >>> Hi Nicolas,
> >>>
> >>> [...]
> >>> >>
> >>> >> 1) can't create /sys/devices/system/cpu/cpu//online: nonexistent directory
> >>> >
> >>> > What do you get if you do:
> >>> >
> >>> > $ ls -d /sys/devices/system/cpu/cpu?/online
> >>> ls: /sys/devices/system/cpu/cpu//online: No such file or directory
> >>
> >> Somehow, you or your shell replaced the ? character into a / character.
> >> You could try with a * instead.
> > With a different RFS your script runs fine without any change. Will
> > update with results once testing is done.
> The script has been running for a few hours on my 5420 based
> chromebook. I can see all the cores being hotplugged in/out. A snippet
> of the prints, that I get on running the test, follows:
> 
[...]

Good, that looks pretty good.

Once you implement full cluster shutdown I can provide you with another 
script stressing that part.


Nicolas

[PATCH v6 0/5] MCPM backend for Exynos5420

[Kukjin Kim]

On 05/16/14 01:52, Nicolas Pitre wrote:
> On Thu, 15 May 2014, Abhilash Kesavan wrote:
>
>> Hi Nicolas,

Hi all,

> [...]
>
> Good, that looks pretty good.
>
Thanks for you guys effort and time.

Applied this whole series.

> Once you implement full cluster shutdown I can provide you with another
> script stressing that part.

Sounds great.

- Kukjin

[PATCH v6 0/5] MCPM backend for Exynos5420

[Abhilash Kesavan]

Hi Kukjin,

On Sat, May 17, 2014 at 5:25 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> On 05/16/14 01:52, Nicolas Pitre wrote:
>>
>> On Thu, 15 May 2014, Abhilash Kesavan wrote:
>>
>>> Hi Nicolas,
>
>
> Hi all,
>
>
>> [...]
>>
>> Good, that looks pretty good.
>>
> Thanks for you guys effort and time.
>
> Applied this whole series.
Thanks!

Abhilash
>
>
>> Once you implement full cluster shutdown I can provide you with another
>> script stressing that part.
>
>
> Sounds great.
>
> - Kukjin

[PATCH v6 0/5] MCPM backend for Exynos5420

[Abhilash Kesavan]

Hi Nicolas,

On Thu, May 15, 2014 at 10:22 PM, Nicolas Pitre
<nicolas.pitre@linaro.org> wrote:
> On Thu, 15 May 2014, Abhilash Kesavan wrote:
>
>> Hi Nicolas,
>>
>> On Wed, May 14, 2014 at 7:09 PM, Abhilash Kesavan
>> <kesavan.abhilash@gmail.com> wrote:
>> > Hi Nicolas,
>> >
>> > On Wed, May 14, 2014 at 7:03 PM, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
>> >> On Wed, 14 May 2014, Abhilash Kesavan wrote:
>> >>
>> >>> Hi Nicolas,
>> >>>
>> >>> [...]
>> >>> >>
>> >>> >> 1) can't create /sys/devices/system/cpu/cpu//online: nonexistent directory
>> >>> >
>> >>> > What do you get if you do:
>> >>> >
>> >>> > $ ls -d /sys/devices/system/cpu/cpu?/online
>> >>> ls: /sys/devices/system/cpu/cpu//online: No such file or directory
>> >>
>> >> Somehow, you or your shell replaced the ? character into a / character.
>> >> You could try with a * instead.
>> > With a different RFS your script runs fine without any change. Will
>> > update with results once testing is done.
>> The script has been running for a few hours on my 5420 based
>> chromebook. I can see all the cores being hotplugged in/out. A snippet
>> of the prints, that I get on running the test, follows:
>>
> [...]
>
> Good, that looks pretty good.
>
> Once you implement full cluster shutdown I can provide you with another
> script stressing that part.
I am done with the cluster power on/off code and it seems to work fine
with bL_switcher. Can you please provide me with your stress script.

Regards,
Abhilash
>
>
> Nicolas

[PATCH v6 0/5] MCPM backend for Exynos5420

[Nicolas Pitre]

On Mon, 19 May 2014, Abhilash Kesavan wrote:

> Hi Nicolas,
> 
> On Thu, May 15, 2014 at 10:22 PM, Nicolas Pitre
> <nicolas.pitre@linaro.org> wrote:
> > Once you implement full cluster shutdown I can provide you with another
> > script stressing that part.
> I am done with the cluster power on/off code and it seems to work fine
> with bL_switcher. Can you please provide me with your stress script.

Here's the script.  Credits go to Dave Martin for this one.

The script assumes that cluster 0 comprises cpus 0 to 3 and cluster 1 
comprises cpus 4 to 7.  You need to edit it otherwise.

----- >8
#!/bin/bash

echo 0 >/sys/kernel/bL_switcher/active
sleep 1

pids=

for x in \
	"cluster=cluster0; cpus='cpu0 cpu1 cpu2 cpu3'" \
	"cluster=cluster1; cpus='cpu4 cpu5 cpu6 cpu7'"
do
	eval "$x"
	eval "\
$cluster () {
	pids=
		`for cpu in $cpus; do cat <<EOF; done
	(sleep .00\\$RANDOM; echo \\$1 >/sys/devices/system/cpu/$cpu/online)&
	echo \\$1 >/sys/devices/system/cpu/$cpu/online&
	pids=\\$pids\ \\$!
EOF`
	wait \$pids
	if [ \$1 = 0 ]; then
		echo \"\$n: $cluster off\"
	else
		echo \"\$n: $cluster on\"
	fi
}"
done

n=0
while :; do
	: $((++n))
	cluster1 1; cluster0 0
	cluster0 1; cluster1 0
done
----- >8


Nicolas

[PATCH v6 0/5] MCPM backend for Exynos5420

[Abhilash Kesavan]

On Tue, May 20, 2014 at 9:00 AM, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> On Mon, 19 May 2014, Abhilash Kesavan wrote:
>
>> Hi Nicolas,
>>
>> On Thu, May 15, 2014 at 10:22 PM, Nicolas Pitre
>> <nicolas.pitre@linaro.org> wrote:
>> > Once you implement full cluster shutdown I can provide you with another
>> > script stressing that part.
>> I am done with the cluster power on/off code and it seems to work fine
>> with bL_switcher. Can you please provide me with your stress script.
>
> Here's the script.  Credits go to Dave Martin for this one.
>
> The script assumes that cluster 0 comprises cpus 0 to 3 and cluster 1
> comprises cpus 4 to 7.  You need to edit it otherwise.
>
> ----- >8
> #!/bin/bash
>
> echo 0 >/sys/kernel/bL_switcher/active
> sleep 1
>
> pids=
>
> for x in \
>         "cluster=cluster0; cpus='cpu0 cpu1 cpu2 cpu3'" \
>         "cluster=cluster1; cpus='cpu4 cpu5 cpu6 cpu7'"
> do
>         eval "$x"
>         eval "\
> $cluster () {
>         pids=
>                 `for cpu in $cpus; do cat <<EOF; done
>         (sleep .00\\$RANDOM; echo \\$1 >/sys/devices/system/cpu/$cpu/online)&
>         echo \\$1 >/sys/devices/system/cpu/$cpu/online&
>         pids=\\$pids\ \\$!
> EOF`
>         wait \$pids
>         if [ \$1 = 0 ]; then
>                 echo \"\$n: $cluster off\"
>         else
>                 echo \"\$n: $cluster on\"
>         fi
> }"
> done
>
> n=0
> while :; do
>         : $((++n))
>         cluster1 1; cluster0 0
>         cluster0 1; cluster1 0
> done
> ----- >8
Thanks Nicolas. Will test with the script and post the patch if it works.

Regards,
Abhilash