[GIT PULL] arm/arm64: KVM: Fix unaligned access bug on gicv2 access

[christoffer.dall@linaro.org (Christoffer Dall)]

On Tue, Sep 23, 2014 at 4:01 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 23 September 2014 14:52, Christoffer Dall
> <christoffer.dall@linaro.org> wrote:
>> If anyone feels like reviewing my patch and giving it a quick test on a
>> BE system with a version of QEMU with the pl011 level-triggered patch,
>
> FWIW, any old version of QEMU running the vexpress-a15 model
> will also use level-triggered interrupts for pl011, because
> the upstream DTB which we use for that board has always
> correctly marked the pl011 and all the other motherboard
> devices as being level-triggered.
>
> I'm still not 100% convinced we shouldn't mark the
> virtio-mmio devices as level-triggered, incidentally.
> I *think* that (a) the spec pretty heavily implies that
> the lines behave as level triggered but (b) the
> specific text in the spec about required guest code
> to avoid races (s.2.4.2 of the 0.9.5 spec) means that
> even if the interrupt controller treats them as edge
> triggered it's OK.
>
I think we should really sit down and figure out the right thing to do
during KVM Forum if we can allocate a slot for that.  Marc seems to
also have some input he would like to share on this subject.

For the record, I'm fine with changing the virtio-mmio devices, but
it's probably worth quickly measuring the performance impact first.

Thanks,
-Christoffer