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s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=RpIp+c9QrsYwq5t2u00EYWH3/GWTwCAmRYU2Yu8v6o8=; b=SzbDytQPWAWzNQDjtE6esC8czt4UkQoe1Jv2pB3cqDyc6eDuqSH5xLHYpeJ/bnJEUi QQVdwV9mT54qep0PtPWd7Ie+Cz5WI1G4RRDre45sIOO6O+iNTc4rqwTgyYRa1gz8s9qK x9TnDdTPqqxYhrk/YmidegKYM/Xo+A0nT/YBlUcpO+1rLDQjIY4uYqkhTOFlFm24pa60 TmezfAkjzbybhoHAbPuaEtXe6QSNv0lOCrftM6MBMX07TcXV3wB+oSseADnIWiVsDVwo QibrT/08qDIyJdSU1nObWSqeFPJGTQytCAOX9AKTJNA7exHThUuW9KGwpnA+jWwDKFmF ANUQ== X-Gm-Message-State: AOAM533M4YdmNt6+MhkMSDcAzZBRV85Mv/BNNftnGZe2qvYTYbTCrErY 5BDdd9466z9oZ0r/1u30hFu/wCXuwx9NR6FSyHUsQA== X-Google-Smtp-Source: ABdhPJzBqeQkZ9fgUtEqZcqzCV7C3q4QbkF7xJ/oWAQ4fzULk6b0FeWiwd6s5H5ZsXJHVAwkD+spce+JwEj+Hmrs4/o= X-Received: by 2002:a05:6e02:c2e:: with SMTP id q14mr4614826ilg.2.1626216742967; Tue, 13 Jul 2021 15:52:22 -0700 (PDT) MIME-Version: 1.0 References: <20210702194110.2045282-1-pcc@google.com> <20210702194110.2045282-3-pcc@google.com> <20210707111054.GA21926@willie-the-truck> <20210713172748.GB30304@willie-the-truck> In-Reply-To: <20210713172748.GB30304@willie-the-truck> From: Peter Collingbourne Date: Tue, 13 Jul 2021 15:52:12 -0700 Message-ID: Subject: Re: [PATCH v9 2/4] arm64: mte: change ASYNC and SYNC TCF settings into bitfields To: Will Deacon Cc: Catalin Marinas , Vincenzo Frascino , Evgenii Stepanov , Szabolcs Nagy , Tejas Belagod , linux-arm-kernel@lists.infradead.org, Greg Kroah-Hartman X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210713_155224_972125_725355EB X-CRM114-Status: GOOD ( 27.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jul 13, 2021 at 10:27 AM Will Deacon wrote: > > On Mon, Jul 12, 2021 at 12:04:39PM -0700, Peter Collingbourne wrote: > > On Wed, Jul 7, 2021 at 4:11 AM Will Deacon wrote: > > > On Fri, Jul 02, 2021 at 12:41:08PM -0700, Peter Collingbourne wrote: > > > > long set_mte_ctrl(struct task_struct *task, unsigned long arg) > > > > { > > > > - u64 sctlr = task->thread.sctlr_user & ~SCTLR_EL1_TCF0_MASK; > > > > u64 mte_ctrl = (~((arg & PR_MTE_TAG_MASK) >> PR_MTE_TAG_SHIFT) & > > > > SYS_GCR_EL1_EXCL_MASK) << MTE_CTRL_GCR_USER_EXCL_SHIFT; > > > > > > > > if (!system_supports_mte()) > > > > return 0; > > > > > > > > - switch (arg & PR_MTE_TCF_MASK) { > > > > - case PR_MTE_TCF_NONE: > > > > - sctlr |= SCTLR_EL1_TCF0_NONE; > > > > - break; > > > > - case PR_MTE_TCF_SYNC: > > > > - sctlr |= SCTLR_EL1_TCF0_SYNC; > > > > - break; > > > > - case PR_MTE_TCF_ASYNC: > > > > - sctlr |= SCTLR_EL1_TCF0_ASYNC; > > > > - break; > > > > - default: > > > > - return -EINVAL; > > > > - } > > > > + if (arg & PR_MTE_TCF_ASYNC) > > > > + mte_ctrl |= MTE_CTRL_TCF_ASYNC; > > > > + if (arg & PR_MTE_TCF_SYNC) > > > > + mte_ctrl |= MTE_CTRL_TCF_SYNC; > > > > > > > > - if (task != current) { > > > > - task->thread.sctlr_user = sctlr; > > > > - task->thread.mte_ctrl = mte_ctrl; > > > > - } else { > > > > - set_task_sctlr_el1(sctlr); > > > > - set_gcr_el1_excl(mte_ctrl); > > > > + task->thread.mte_ctrl = mte_ctrl; > > > > + if (task == current) { > > > > + mte_update_sctlr_user(task); > > > > > > In conjunction with the next patch, what happens if we migrate at this > > > point? I worry that we can install a stale sctlr_user value. > > > > > > > + set_task_sctlr_el1(task->thread.sctlr_user); > > > > In this case, we will call mte_update_sctlr_user when scheduled onto > > the new CPU as a result of the change to mte_thread_switch, and both > > the scheduler and prctl will set SCTLR_EL1 to the new (correct) value > > for the current CPU. > > Doesn't that rely on task->thread.sctlr_user being explicitly read on the > new CPU? For example, the following rough sequence is what I'm worried > about: > > > CPU x (prefer ASYNC) > set_mte_ctrl(ASYNC | SYNC) > current->thread.mte_ctrl = ASYNC | SYNC; > mte_update_sctlr_user > current->thread.sctlr_user = ASYNC; > Register Xn = current->thread.sctlr_user; // ASYNC > > > CPU y (prefer SYNC) > mte_thread_switch > mte_update_sctlr_user > next->thread.sctlr_user = SYNC; > update_sctlr_el1 > SCTLR_EL1 = SYNC; > > > set_task_sctlr_el1(Xn); // ASYNC > current->thread.sctlr_user = Xn; // ASYNC XXX: also superfluous? > SCTLR_EL1 = ASYNC; > > > Does that make sense? > > I'm thinking set_mte_ctrl() should be using update_sctlr_el1() and disabling > preemption around the whole thing, which would make it a lot closer to the > context-switch path. Okay, I see what you mean. I also noticed that prctl(PR_PAC_SET_ENABLED_KEYS) would now have the same problem. In v10 I've addressed this issue by inserting a patch after this one that disables preemption in both prctl implementations. Peter _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel