[PATCH 00/13] Add R8A7794/SILK board eMMC DT support

[PATCH 00/13] Add R8A7794/SILK board eMMC DT support

[Sergei Shtylyov]

Hello.

   Here's the set of 13 patches against Simon Horman's 'renesas.git' repo,
'renesas-devel-20160530-v4.7-rc1' tag. We add the device tree support for
the R8A7792-based Blanche board. The R-Car 'clk' driver patch was posted last
week separately...

[01/13] ARM: shmobile: r8a7792: add clock index macros
[02/13] ARM: shmobile: r8a7792: add power domain index macros
[03/13] soc: renesas: rcar-sysc: add R8A7792 support
[04/13] ARM: shmobile: r8a7792: basic SoC support
[05/13] DT: clock: rcar-gen2-cpg-clocks: document R8A7792 support
[06/13] DT: clock: cpg-mstp-clocks: document-R8A7792-support
[07/13] ARM: dts: r8a7792: initial SoC device tree
[08/13] ARM: dts: r8a7792: add SYS-DMAC support
[09/13] ARM: dts: r8a7792: add [H]SCIF support
[10/13] ARM dts: r8a7792: add IRQC support
[11/13] DT: arm: shmobile: document Blanche board
[12/13] ARM: dts: blanche: initial device tree
[13/13] ARM: dts: blanche: add Ethernet support

WBR, Sergei

[PATCH 04/13] ARM: shmobile: r8a7792: basic SoC support

[Sergei Shtylyov]

Add minimal support for the R-Car V2H (R8A7792) SoC.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
 arch/arm/mach-shmobile/Kconfig         |    5 ++++
 arch/arm/mach-shmobile/Makefile        |    1 
 arch/arm/mach-shmobile/setup-r8a7792.c |   34 +++++++++++++++++++++++++++++++++
 3 files changed, 40 insertions(+)

Index: renesas/arch/arm/mach-shmobile/Kconfig
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/Kconfig
+++ renesas/arch/arm/mach-shmobile/Kconfig
@@ -86,6 +86,11 @@ config ARCH_R8A7791
 	select ARCH_RCAR_GEN2
 	select I2C
 
+config ARCH_R8A7792
+	bool "R-Car V2H (R8A77920)"
+	select ARCH_RCAR_GEN2
+	select I2C
+
 config ARCH_R8A7793
 	bool "R-Car M2-N (R8A7793)"
 	select ARCH_RCAR_GEN2
Index: renesas/arch/arm/mach-shmobile/Makefile
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/Makefile
+++ renesas/arch/arm/mach-shmobile/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_ARCH_R8A7778)	+= setup-r8a7
 obj-$(CONFIG_ARCH_R8A7779)	+= setup-r8a7779.o pm-r8a7779.o
 obj-$(CONFIG_ARCH_R8A7790)	+= setup-r8a7790.o
 obj-$(CONFIG_ARCH_R8A7791)	+= setup-r8a7791.o
+obj-$(CONFIG_ARCH_R8A7792)	+= setup-r8a7792.o
 obj-$(CONFIG_ARCH_R8A7793)	+= setup-r8a7793.o
 obj-$(CONFIG_ARCH_R8A7794)	+= setup-r8a7794.o
 obj-$(CONFIG_ARCH_EMEV2)	+= setup-emev2.o
Index: renesas/arch/arm/mach-shmobile/setup-r8a7792.c
===================================================================
--- /dev/null
+++ renesas/arch/arm/mach-shmobile/setup-r8a7792.c
@@ -0,0 +1,34 @@
+/*
+ * r8a7792 processor support
+ *
+ * Copyright (C) 2014  Renesas Electronics Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/of_platform.h>
+
+#include <asm/mach/arch.h>
+
+#include "common.h"
+#include "rcar-gen2.h"
+
+static const char * const r8a7792_boards_compat_dt[] __initconst = {
+	"renesas,r8a7792",
+	NULL,
+};
+
+DT_MACHINE_START(R8A7792_DT, "Generic R8A7792 (Flattened Device Tree)")
+	.init_early	= shmobile_init_delay,
+	.init_late	= shmobile_init_late,
+	.init_time	= rcar_gen2_timer_init,
+	.reserve	= rcar_gen2_reserve,
+	.dt_compat	= r8a7792_boards_compat_dt,
+MACHINE_END

[PATCH 04/13] ARM: shmobile: r8a7792: basic SoC support

[Simon Horman]

On Wed, Jun 01, 2016 at 01:18:22AM +0300, Sergei Shtylyov wrote:
> Add minimal support for the R-Car V2H (R8A7792) SoC.
> 
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Acked-by: Simon Horman <horms+renesas@verge.net.au>

[PATCH 04/13] ARM: shmobile: r8a7792: basic SoC support

[Geert Uytterhoeven]

Hi Sergei,

On Wed, Jun 1, 2016 at 12:18 AM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> --- renesas.orig/arch/arm/mach-shmobile/Kconfig
> +++ renesas/arch/arm/mach-shmobile/Kconfig
> @@ -86,6 +86,11 @@ config ARCH_R8A7791
>         select ARCH_RCAR_GEN2
>         select I2C
>
> +config ARCH_R8A7792
> +       bool "R-Car V2H (R8A77920)"
> +       select ARCH_RCAR_GEN2
> +       select I2C

I2c is selected for the other SoCs because of regulator-quirk-rcar-gen2.
I do not have schematics for Blanche, so I don't know if it has DA9063 and
DA9210 regulators sharing the same interrupt.
If yes, you should make sure regulator-quirk-rcar-gen2 is updated for Blanche,
and built.
If no, you should drop the select.

If the above is clarified:

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 04/13] ARM: shmobile: r8a7792: basic SoC support

[Sergei Shtylyov]

On 06/01/2016 10:47 AM, Geert Uytterhoeven wrote:

>> --- renesas.orig/arch/arm/mach-shmobile/Kconfig
>> +++ renesas/arch/arm/mach-shmobile/Kconfig
>> @@ -86,6 +86,11 @@ config ARCH_R8A7791
>>         select ARCH_RCAR_GEN2
>>         select I2C
>>
>> +config ARCH_R8A7792
>> +       bool "R-Car V2H (R8A77920)"
>> +       select ARCH_RCAR_GEN2
>> +       select I2C
>
> I2c is selected for the other SoCs because of regulator-quirk-rcar-gen2.
> I do not have schematics for Blanche, so I don't know if it has DA9063 and
> DA9210 regulators sharing the same interrupt.

    No, it only has DA9063.

> If yes, you should make sure regulator-quirk-rcar-gen2 is updated for Blanche,
> and built.
> If no, you should drop the select.

    Thanks for noticing!

> If the above is clarified:

> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

    Thank you, adding...

> Gr{oetje,eeting}s,
>
>                         Geert

MBR, Sergei

[PATCH 04/13] ARM: shmobile: r8a7792: basic SoC support

[Sergei Shtylyov]

Hello.

On 06/01/2016 01:18 AM, Sergei Shtylyov wrote:

> Add minimal support for the R-Car V2H (R8A7792) SoC.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
[...]

> Index: renesas/arch/arm/mach-shmobile/setup-r8a7792.c
> ===================================================================
> --- /dev/null
> +++ renesas/arch/arm/mach-shmobile/setup-r8a7792.c
> @@ -0,0 +1,34 @@
> +/*
> + * r8a7792 processor support
> + *
> + * Copyright (C) 2014  Renesas Electronics Corporation

    Hm, I thought I'd stamped Cogent's copyright here... Please hold on with 
merging this patch.

[...]

MBR, Sergei

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Sergei Shtylyov]

The initial R8A7792 SoC device tree including 2 CPU cores, GIC, timer, SYSC,
and the required  clock descriptions.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
 arch/arm/boot/dts/r8a7792.dtsi |  423 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 423 insertions(+)

Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
===================================================================
--- /dev/null
+++ renesas/arch/arm/boot/dts/r8a7792.dtsi
@@ -0,0 +1,423 @@
+/*
+ * Device Tree Source for the r8a7792 SoC
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/clock/r8a7792-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a7792-sysc.h>
+
+/ {
+	compatible = "renesas,r8a7792";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0>;
+			clock-frequency = <1000000000>;
+			clocks = <&cpg_clocks R8A7792_CLK_Z>;
+			power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
+			next-level-cache = <&L2_CA15>;
+		};
+
+		cpu1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <1>;
+			clock-frequency = <1000000000>;
+			power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
+			next-level-cache = <&L2_CA15>;
+		};
+
+		L2_CA15: cache-controller at 0 {
+			compatible = "cache";
+			reg = <0>;
+			cache-unified;
+			cache-level = <2>;
+			power-domains = <&sysc R8A7792_PD_CA15_SCU>;
+		};
+	};
+
+	gic: interrupt-controller at f1001000 {
+		compatible = "arm,gic-400";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0 0xf1001000 0 0x1000>,
+		      <0 0xf1002000 0 0x1000>,
+		      <0 0xf1004000 0 0x2000>,
+		      <0 0xf1006000 0 0x2000>;
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+			      IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13
+			      (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+			      (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+			      (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+			      (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	sysc: system-controller at e6180000 {
+		compatible = "renesas,r8a7792-sysc";
+		reg = <0 0xe6180000 0 0x0200>;
+		#power-domain-cells = <1>;
+	};
+
+	clocks {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* External root clock */
+		extal_clk: extal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			/* This value must be overridden by the board. */
+			clock-frequency = <0>;
+		};
+
+		/* External PCIe clock - can be overridden by the board */
+		pcie_bus_clk: pcie_bus {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+
+		/* External SCIF clock */
+		scif_clk: scif {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			/* This value must be overridden by the board. */
+			clock-frequency = <0>;
+		};
+
+		/*
+		 * The external audio clocks are configured as 0 Hz fixed
+		 * frequency clocks by default.  Boards that provide audio
+		 * clocks should override them.
+		 */
+		audio_clka: audio_clka {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+		audio_clkb: audio_clkb {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+		audio_clkc: audio_clkc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+
+		/* Special CPG clocks */
+		cpg_clocks: cpg_clocks at e6150000 {
+			compatible = "renesas,r8a7792-cpg-clocks",
+				     "renesas,rcar-gen2-cpg-clocks";
+			reg = <0 0xe6150000 0 0x1000>;
+			clocks = <&extal_clk>;
+			#clock-cells = <1>;
+			clock-output-names = "main", "pll0", "pll1", "pll3",
+					     "lb", "qspi", "sdh", "sd0", "sd1",
+					     "z";
+			#power-domain-cells = <0>;
+		};
+
+		/* Fixed factor clocks */
+		pll1_div2_clk: pll1_div2 {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <2>;
+			clock-mult = <1>;
+		};
+		z2_clk: z2 {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <2>;
+			clock-mult = <1>;
+		};
+		zg_clk: zg {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <3>;
+			clock-mult = <1>;
+		};
+		zx_clk: zx {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <3>;
+			clock-mult = <1>;
+		};
+		zs_clk: zs {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <6>;
+			clock-mult = <1>;
+		};
+		hp_clk: hp {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <12>;
+			clock-mult = <1>;
+		};
+		i_clk: i {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <2>;
+			clock-mult = <1>;
+		};
+		b_clk: b {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <12>;
+			clock-mult = <1>;
+		};
+		p_clk: p {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <24>;
+			clock-mult = <1>;
+		};
+		cl_clk: cl {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <48>;
+			clock-mult = <1>;
+		};
+		m2_clk: m2 {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <8>;
+			clock-mult = <1>;
+		};
+		rclk_clk: rclk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <(48 * 1024)>;
+			clock-mult = <1>;
+		};
+		oscclk_clk: oscclk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <(12 * 1024)>;
+			clock-mult = <1>;
+		};
+		zb3_clk: zb3 {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7792_CLK_PLL3>;
+			#clock-cells = <0>;
+			clock-div = <4>;
+			clock-mult = <1>;
+		};
+		zb3d2_clk: zb3d2 {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7792_CLK_PLL3>;
+			#clock-cells = <0>;
+			clock-div = <8>;
+			clock-mult = <1>;
+		};
+		ddr_clk: ddr {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7792_CLK_PLL3>;
+			#clock-cells = <0>;
+			clock-div = <8>;
+			clock-mult = <1>;
+		};
+		mp_clk: mp {
+			compatible = "fixed-factor-clock";
+			clocks = <&pll1_div2_clk>;
+			#clock-cells = <0>;
+			clock-div = <15>;
+			clock-mult = <1>;
+		};
+		cp_clk: cp {
+			compatible = "fixed-factor-clock";
+			clocks = <&extal_clk>;
+			#clock-cells = <0>;
+			clock-div = <2>;
+			clock-mult = <1>;
+		};
+
+		/* Gate clocks */
+		mstp0_clks: mstp0_clks at e6150130 {
+			compatible = "renesas,r8a7792-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+			clocks = <&mp_clk>;
+			#clock-cells = <1>;
+			clock-indices = <R8A7792_CLK_MSIOF0>;
+			clock-output-names = "msiof0";
+		};
+		mstp1_clks: mstp1_clks at e6150134 {
+			compatible = "renesas,r8a7792-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+			clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
+				 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7792_CLK_TMU1 R8A7792_CLK_TMU3
+				R8A7792_CLK_TMU2 R8A7792_CLK_CMT0
+				R8A7792_CLK_TMU0 R8A7792_CLK_VSP1DU1
+				R8A7792_CLK_VSP1DU0 R8A7792_CLK_VSP1_SY
+			>;
+			clock-output-names = "tmu1", "tmu3", "tmu2", "cmt0",
+					     "tmu0", "vsp1du1", "vsp1du0",
+					     "vsp1-sy";
+		};
+		mstp2_clks: mstp2_clks at e6150138 {
+			compatible = "renesas,r8a7792-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+			clocks = <&mp_clk>, <&zs_clk>, <&zs_clk>;
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7792_CLK_MSIOF1
+				R8A7792_CLK_SYS_DMAC0 R8A7792_CLK_SYS_DMAC1
+			>;
+			clock-output-names = "msiof1", "sys-dmac0", "sys-dmac1";
+		};
+		mstp3_clks: mstp3_clks at e615013c {
+			compatible = "renesas,r8a7792-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+			clocks = <&cp_clk>, <&cpg_clocks R8A7792_CLK_SD0>,
+				 <&rclk_clk>;
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7792_CLK_TPU0 R8A7792_CLK_SDHI0
+				R8A7792_CLK_CMT1
+			>;
+			clock-output-names = "tpu0", "sdhi0", "cmt1";
+		};
+		mstp4_clks: mstp4_clks at e6150140 {
+			compatible = "renesas,r8a7792-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
+			clocks = <&cp_clk>;
+			#clock-cells = <1>;
+			clock-indices = <R8A7792_CLK_IRQC>;
+			clock-output-names = "irqc";
+		};
+		mstp5_clks: mstp5_clks at e6150144 {
+			compatible = "renesas,r8a7792-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
+			clocks = <&hp_clk>, <&extal_clk>, <&p_clk>;
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7792_CLK_AUDIO_DMAC0
+				R8A7792_CLK_THERMAL R8A7792_CLK_PWM
+			>;
+			clock-output-names = "thermal", "pwm", "audmac0";
+		};
+		mstp7_clks: mstp7_clks at e615014c {
+			compatible = "renesas,r8a7792-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+			clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
+				 <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>;
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
+				R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
+				R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
+				R8A7792_CLK_DU1 R8A7792_CLK_DU0
+			>;
+			clock-output-names = "hscif1", "hscif0", "scif3",
+					     "scif2", "scif1", "scif0",
+					     "du1", "du0";
+		};
+		mstp8_clks: mstp8_clks at e6150990 {
+			compatible = "renesas,r8a7792-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
+			clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
+				 <&zg_clk>, <&zg_clk>, <&hp_clk>;
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7792_CLK_VIN5 R8A7792_CLK_VIN4
+				R8A7792_CLK_VIN3 R8A7792_CLK_VIN2
+				R8A7792_CLK_VIN1 R8A7792_CLK_VIN0
+				R8A7792_CLK_ETHERAVB
+			>;
+			clock-output-names = "vin5", "vin4", "vin3", "vin2",
+					     "vin1", "vin0", "etheravb";
+		};
+		mstp9_clks: mstp9_clks at e6150994 {
+			compatible = "renesas,r8a7792-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
+			clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
+				 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
+				 <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>,
+				 <&cpg_clocks R8A7792_CLK_QSPI>, <&cp_clk>,
+				 <&cp_clk>, <&hp_clk>, <&cp_clk>, <&hp_clk>,
+				 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6
+				R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4
+				R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2
+				R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0
+				R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10
+				R8A7792_CLK_CAN1 R8A7792_CLK_CAN0
+				R8A7792_CLK_QSPI_MOD R8A7792_CLK_GPIO9
+				R8A7792_CLK_GPIO8 R8A7792_CLK_I2C5
+				R8A7792_CLK_IICDVFS R8A7792_CLK_I2C4
+				R8A7792_CLK_I2C3 R8A7792_CLK_I2C2
+				R8A7792_CLK_I2C1 R8A7792_CLK_I2C0
+			>;
+			clock-output-names = "gpio7", "gpio6", "gpio5", "gpio4",
+					     "gpio3", "gpio2", "gpio1", "gpio0",
+					     "gpio11", "gpio10", "can1", "can0",
+					     "qspi_mod", "gpio9", "gpio8",
+					     "i2c5", "iic3", "i2c4", "i2c3",
+					     "i2c2", "i2c1", "i2c0";
+		};
+		mstp10_clks: mstp10_clks at e6150998 {
+			compatible = "renesas,r8a7792-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
+			clocks = <&p_clk>, <&p_clk>, <&p_clk>;
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7792_CLK_SSI_ALL
+				R8A7792_CLK_SSI4 R8A7792_CLK_SSI3
+			>;
+			clock-output-names = "ssi", "ssi4", "ssi3";
+		};
+	};
+};

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Simon Horman]

On Wed, Jun 01, 2016 at 01:24:21AM +0300, Sergei Shtylyov wrote:
> The initial R8A7792 SoC device tree including 2 CPU cores, GIC, timer, SYSC,
> and the required  clock descriptions.
> 
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

This is rather large for an initial DTSI. Did you give any consideration
to splitting it up: e.g. only providing what is needed to get to a serial
console?

With regards to SMP. Have you checked to make sure CPU hotplug works
on all CPUs? And that the system behaves sanely on suspend/resume.
If it is not possible to verify this at this stage then I would recommend
only enabling one CPU at this stage.

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Sergei Shtylyov]

On 06/01/2016 03:57 AM, Simon Horman wrote:

>> The initial R8A7792 SoC device tree including 2 CPU cores, GIC, timer, SYSC,
>> and the required  clock descriptions.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> This is rather large for an initial DTSI. Did you give any consideration
> to splitting it up: e.g. only providing what is needed to get to a serial
> console?

    You mean dropping the majority of clocks, right?

> With regards to SMP. Have you checked to make sure CPU hotplug works
> on all CPUs? And that the system behaves sanely on suspend/resume.
> If it is not possible to verify this at this stage then I would recommend
> only enabling one CPU at this stage.

    No, the SMP support isn't ready yet.
    And I'll have to enable SMP on R8A7794 as well...

MBR, Sergei

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Sergei Shtylyov]

Hello.

On 06/01/2016 03:57 AM, Simon Horman wrote:

>> The initial R8A7792 SoC device tree including 2 CPU cores, GIC, timer, SYSC,
>> and the required  clock descriptions.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> This is rather large for an initial DTSI. Did you give any consideration
> to splitting it up: e.g. only providing what is needed to get to a serial
> console?

    Was done in the v2 patchset...

> With regards to SMP. Have you checked to make sure CPU hotplug works
> on all CPUs?

    How to test the CPU hotplug? I've now added the SMP support and made sure 
both CPUs are online and serve IRQs...

> And that the system behaves sanely on suspend/resume.

    I'd be thankful if you told me how to test that. :-)

> If it is not possible to verify this at this stage then I would recommend
> only enabling one CPU at this stage.

    Had a hard time debugging SMP until I realized I'd removed CPU1 from the 
device tree. :-)

MBR, Sergei

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Geert Uytterhoeven]

Hi Sergei,

On Tue, Jun 7, 2016 at 12:26 AM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
>> With regards to SMP. Have you checked to make sure CPU hotplug works
>> on all CPUs?
>
>    How to test the CPU hotplug? I've now added the SMP support and made sure
> both CPUs are online and serve IRQs...

Off/online all CPUs:

    for i in /sys/*/*/cpu/cpu[0-9]*; do echo 0 > $i/online; echo 1 >
$i/online; done

Offline all CPUs:

    for i in /sys/*/*/cpu/cpu[0-9]*; do echo 0 > $i/online; done; cat
/proc/cpuinfo

Online all CPUs:

   for i in /sys/*/*/cpu/cpu[0-9]*; do echo 1 > $i/online; done; cat
/proc/cpuinfo

>> And that the system behaves sanely on suspend/resume.
>
>    I'd be thankful if you told me how to test that. :-)

System suspend:

    echo mem > /sys/power/state

System resume: You're gonna need a "wakeup-source" in your DTS, e.g. gpio-keys.
Serial should work too, echo "enabled" to the corresponding wakeup
file in /sys first.

In case of issues, try "echo 0 > /sys/module/printk/parameters/console_suspend".

Good luck!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Sergei Shtylyov]

On 06/07/2016 10:13 AM, Geert Uytterhoeven wrote:

[...]

>>> And that the system behaves sanely on suspend/resume.
>>
>>    I'd be thankful if you told me how to test that. :-)
>
> System suspend:
>
>     echo mem > /sys/power/state

    Oh. I know that one! :-)

> System resume: You're gonna need a "wakeup-source" in your DTS, e.g. gpio-keys.
> Serial should work too, echo "enabled" to the corresponding wakeup
> file in /sys first.

    I'm afraid I couldn't find that file. All I saw were RPM controls...

> In case of issues, try "echo 0 > /sys/module/printk/parameters/console_suspend".

    There's no problems suspending, it's the resuming that's a problem for me.

> Good luck!

    As usual, there was no luck. :-)

WBR, Sergei

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Simon Horman]

On Tue, Jun 07, 2016 at 11:58:45PM +0300, Sergei Shtylyov wrote:
> On 06/07/2016 10:13 AM, Geert Uytterhoeven wrote:
> 
> [...]
> 
> >>>And that the system behaves sanely on suspend/resume.
> >>
> >>   I'd be thankful if you told me how to test that. :-)
> >
> >System suspend:
> >
> >    echo mem > /sys/power/state
> 
>    Oh. I know that one! :-)
> 
> >System resume: You're gonna need a "wakeup-source" in your DTS, e.g. gpio-keys.
> >Serial should work too, echo "enabled" to the corresponding wakeup
> >file in /sys first.
> 
>    I'm afraid I couldn't find that file. All I saw were RPM controls...
> 
> >In case of issues, try "echo 0 > /sys/module/printk/parameters/console_suspend".
> 
>    There's no problems suspending, it's the resuming that's a problem for me.
> 
> >Good luck!
> 
>    As usual, there was no luck. :-)
> 
> WBR, Sergei

Does resume work for UP (i.e. without SMP)?

How did testing CPU hotplug go? Did it work for all CPUs?

If things work less well for SMP than UP I am inclined to ask
you to defer adding SMP support.

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Sergei Shtylyov]

On 06/10/2016 04:02 AM, Simon Horman wrote:

>> [...]
>>
>>>>> And that the system behaves sanely on suspend/resume.
>>>>
>>>>   I'd be thankful if you told me how to test that. :-)
>>>
>>> System suspend:
>>>
>>>    echo mem > /sys/power/state
>>
>>    Oh. I know that one! :-)
>>
>>> System resume: You're gonna need a "wakeup-source" in your DTS, e.g. gpio-keys.
>>> Serial should work too, echo "enabled" to the corresponding wakeup
>>> file in /sys first.
>>
>>    I'm afraid I couldn't find that file. All I saw were RPM controls...
>>
>>> In case of issues, try "echo 0 > /sys/module/printk/parameters/console_suspend".
>>
>>    There's no problems suspending, it's the resuming that's a problem for me.
>>
>>> Good luck!
>>
>>    As usual, there was no luck. :-)
>>
>> WBR, Sergei
>
> Does resume work for UP (i.e. without SMP)?

    No. My problem with resume is I can't wake up the remote system. I don't 
see the needed 'wakeup' file in /sys/devices/platform/soc/e6e60000.serial/...
     However, if I enable CONFIG_PM_[ADVANCED_]DEBUG and do

$ echo -n core /sys/.power/pm_test

the system happily wakes up after a small delay (5 s), w/either SMP or UP kernel.

> How did testing CPU hotplug go? Did it work for all CPUs?

    Sure!
    The only problem I'm seeing (again) is the RCAN clock failing to register:

rcar_gen2_cpg_clocks_init: failed to register cpg_clocks rcan clock (-12)

    I was going to look at it yesterday but (wrongly) thought it somehow cured 
itself... I'll look at it now.

MBR, Sergei

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Geert Uytterhoeven]

Hi Sergei,

On Fri, Jun 10, 2016 at 9:29 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
>    The only problem I'm seeing (again) is the RCAN clock failing to
> register:
>
> rcar_gen2_cpg_clocks_init: failed to register cpg_clocks rcan clock (-12)
>
>    I was going to look at it yesterday but (wrongly) thought it somehow
> cured itself... I'll look at it now.

The RCAN parent is the second clock in the CPG node's "clocks" property,
which you didn't provide.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Sergei Shtylyov]

On 06/10/2016 11:42 PM, Geert Uytterhoeven wrote:

>>    The only problem I'm seeing (again) is the RCAN clock failing to
>> register:
>>
>> rcar_gen2_cpg_clocks_init: failed to register cpg_clocks rcan clock (-12)
>>
>>    I was going to look at it yesterday but (wrongly) thought it somehow
>> cured itself... I'll look at it now.
>
> The RCAN parent is the second clock in the CPG node's "clocks" property,
> which you didn't provide.

    Actually, the things are more complex. The figure 7.1c suggests that the 
RCAN clock has different parent on R8A7792 than on the other SoCs -- namely 
PLL1/VCO 1/4. That may be, since there's just no USB_EXTAL signal on this SoC 
(it doesn't seem to support any USB IPs). Which means the 'clk-rcar-gen2' 
driver can't work with the RCAN clock in its current form.

> Gr{oetje,eeting}s,
>
>                         Geert

MBR, Sergei

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Geert Uytterhoeven]

Hi Sergei,

On Fri, Jun 10, 2016 at 10:50 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> On 06/10/2016 11:42 PM, Geert Uytterhoeven wrote:
>>>    The only problem I'm seeing (again) is the RCAN clock failing to
>>> register:
>>>
>>> rcar_gen2_cpg_clocks_init: failed to register cpg_clocks rcan clock (-12)
>>>
>>>    I was going to look at it yesterday but (wrongly) thought it somehow
>>> cured itself... I'll look at it now.
>>
>> The RCAN parent is the second clock in the CPG node's "clocks" property,
>> which you didn't provide.
>
>    Actually, the things are more complex. The figure 7.1c suggests that the
> RCAN clock has different parent on R8A7792 than on the other SoCs -- namely
> PLL1/VCO 1/4. That may be, since there's just no USB_EXTAL signal on this
> SoC (it doesn't seem to support any USB IPs). Which means the
> 'clk-rcar-gen2' driver can't work with the RCAN clock in its current form.

Right, I had forgotten about that.
Fortunately the clk-rcar-gen2 driver has a sane failure mode for this case ;-)

it seems the RCAN clock can just be modeled as a fixed clock. However,
its divider value isn't clear to me, as 15.9 MHz cannot be generated from PLL1
using an integer divider. Morimoto-san, can you please ask for clarification?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Sergei Shtylyov]

On 6/13/2016 10:12 AM, Geert Uytterhoeven wrote:

>>>>    The only problem I'm seeing (again) is the RCAN clock failing to
>>>> register:
>>>>
>>>> rcar_gen2_cpg_clocks_init: failed to register cpg_clocks rcan clock (-12)
>>>>
>>>>    I was going to look at it yesterday but (wrongly) thought it somehow
>>>> cured itself... I'll look at it now.
>>>
>>> The RCAN parent is the second clock in the CPG node's "clocks" property,
>>> which you didn't provide.
>>
>>    Actually, the things are more complex. The figure 7.1c suggests that the
>> RCAN clock has different parent on R8A7792 than on the other SoCs -- namely
>> PLL1/VCO 1/4. That may be, since there's just no USB_EXTAL signal on this
>> SoC (it doesn't seem to support any USB IPs). Which means the
>> 'clk-rcar-gen2' driver can't work with the RCAN clock in its current form.
>
> Right, I had forgotten about that.
> Fortunately the clk-rcar-gen2 driver has a sane failure mode for this case ;-)

    What do you mean?

> it seems the RCAN clock can just be modeled as a fixed clock. However,
> its divider value isn't clear to me,

    IIRC, the fixed RCAN divisor was equal to 6.

[...]

> Gr{oetje,eeting}s,
>
>                         Geert

MBR, Sergei

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Geert Uytterhoeven]

Hi Sergei,

On Mon, Jun 13, 2016 at 1:24 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> On 6/13/2016 10:12 AM, Geert Uytterhoeven wrote:
>>>>>    The only problem I'm seeing (again) is the RCAN clock failing to
>>>>> register:
>>>>>
>>>>> rcar_gen2_cpg_clocks_init: failed to register cpg_clocks rcan clock
>>>>> (-12)
>>>>>
>>>>>    I was going to look at it yesterday but (wrongly) thought it somehow
>>>>> cured itself... I'll look at it now.
>>>>
>>>>
>>>> The RCAN parent is the second clock in the CPG node's "clocks" property,
>>>> which you didn't provide.
>>>
>>>
>>>    Actually, the things are more complex. The figure 7.1c suggests that
>>> the
>>> RCAN clock has different parent on R8A7792 than on the other SoCs --
>>> namely
>>> PLL1/VCO 1/4. That may be, since there's just no USB_EXTAL signal on this
>>> SoC (it doesn't seem to support any USB IPs). Which means the
>>> 'clk-rcar-gen2' driver can't work with the RCAN clock in its current
>>> form.
>>
>> Right, I had forgotten about that.
>> Fortunately the clk-rcar-gen2 driver has a sane failure mode for this case
>> ;-)
>
>    What do you mean?

I mean that it failed due to the missing parent clock, instead of continuing
silently with a wrong clock rate.

>> it seems the RCAN clock can just be modeled as a fixed clock. However,
>> its divider value isn't clear to me,
>
>    IIRC, the fixed RCAN divisor was equal to 6.

1560 / 6 != 15.9.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Kuninori Morimoto]

Hi Geert

> Right, I had forgotten about that.
> Fortunately the clk-rcar-gen2 driver has a sane failure mode for this case ;-)
> 
> it seems the RCAN clock can just be modeled as a fixed clock. However,
> its divider value isn't clear to me, as 15.9 MHz cannot be generated from PLL1
> using an integer divider. Morimoto-san, can you please ask for clarification?

OK.
Now, I asked to HW team about that.
Please wait.

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Kuninori Morimoto]

Hi Geert

> > Right, I had forgotten about that.
> > Fortunately the clk-rcar-gen2 driver has a sane failure mode for this case ;-)
> > 
> > it seems the RCAN clock can just be modeled as a fixed clock. However,
> > its divider value isn't clear to me, as 15.9 MHz cannot be generated from PLL1
> > using an integer divider. Morimoto-san, can you please ask for clarification?
> 
> OK.
> Now, I asked to HW team about that.
> Please wait.

RCAN divider is fixed for 1/49

PLL1 (= 1560MHz) 
  -> 1/2 (= 780MHz)
    -> RCAN divider 1/49 (= 15.9183..MHz)

Is this clear for you ?

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Geert Uytterhoeven]

Hi Morimoto-san,

On Fri, Jun 17, 2016 at 4:14 AM, Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
>> > Right, I had forgotten about that.
>> > Fortunately the clk-rcar-gen2 driver has a sane failure mode for this case ;-)
>> >
>> > it seems the RCAN clock can just be modeled as a fixed clock. However,
>> > its divider value isn't clear to me, as 15.9 MHz cannot be generated from PLL1
>> > using an integer divider. Morimoto-san, can you please ask for clarification?
>>
>> OK.
>> Now, I asked to HW team about that.
>> Please wait.
>
> RCAN divider is fixed for 1/49
>
> PLL1 (= 1560MHz)
>   -> 1/2 (= 780MHz)
>     -> RCAN divider 1/49 (= 15.9183..MHz)
>
> Is this clear for you ?

Thanks, that's exactly what we need to know.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Simon Horman]

On Fri, Jun 10, 2016 at 10:29:17PM +0300, Sergei Shtylyov wrote:
> On 06/10/2016 04:02 AM, Simon Horman wrote:
> 
> >>[...]
> >>
> >>>>>And that the system behaves sanely on suspend/resume.
> >>>>
> >>>>  I'd be thankful if you told me how to test that. :-)
> >>>
> >>>System suspend:
> >>>
> >>>   echo mem > /sys/power/state
> >>
> >>   Oh. I know that one! :-)
> >>
> >>>System resume: You're gonna need a "wakeup-source" in your DTS, e.g. gpio-keys.
> >>>Serial should work too, echo "enabled" to the corresponding wakeup
> >>>file in /sys first.
> >>
> >>   I'm afraid I couldn't find that file. All I saw were RPM controls...
> >>
> >>>In case of issues, try "echo 0 > /sys/module/printk/parameters/console_suspend".
> >>
> >>   There's no problems suspending, it's the resuming that's a problem for me.
> >>
> >>>Good luck!
> >>
> >>   As usual, there was no luck. :-)
> >>
> >>WBR, Sergei
> >
> >Does resume work for UP (i.e. without SMP)?
> 
>    No. My problem with resume is I can't wake up the remote system. I don't
> see the needed 'wakeup' file in
> /sys/devices/platform/soc/e6e60000.serial/...
>     However, if I enable CONFIG_PM_[ADVANCED_]DEBUG and do
> 
> $ echo -n core /sys/.power/pm_test
> 
> the system happily wakes up after a small delay (5 s), w/either SMP or UP kernel.

That seems promising but it seems curious that there is no wakeup file.

On Lager the following procedure works for me using
renesas-devel-20160613-v4.7-rc3 and shmobile defconfig.

0. Add wakeup-source property to serial at e6ce0000 node in DT
1. echo enabled > /sys/devices/platform/e6e60000.serial/tty/ttySC0/power/wakeup
2. echo mem > /sys/power/state
3. Provide input on serial console

* Success! *

> >How did testing CPU hotplug go? Did it work for all CPUs?
> 
>    Sure!

Great!

>    The only problem I'm seeing (again) is the RCAN clock failing to register:
> 
> rcar_gen2_cpg_clocks_init: failed to register cpg_clocks rcan clock (-12)
> 
>    I was going to look at it yesterday but (wrongly) thought it somehow
> cured itself... I'll look at it now.

Is this resolved? If not perhaps you could consider removing the node
in question for now.

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Sergei Shtylyov]

Hello.

On 06/14/2016 03:43 AM, Simon Horman wrote:

>>>> [...]
>>>>
>>>>>>> And that the system behaves sanely on suspend/resume.
>>>>>>
>>>>>>  I'd be thankful if you told me how to test that. :-)
>>>>>
>>>>> System suspend:
>>>>>
>>>>>   echo mem > /sys/power/state
>>>>
>>>>   Oh. I know that one! :-)
>>>>
>>>>> System resume: You're gonna need a "wakeup-source" in your DTS, e.g. gpio-keys.
>>>>> Serial should work too, echo "enabled" to the corresponding wakeup
>>>>> file in /sys first.
>>>>
>>>>   I'm afraid I couldn't find that file. All I saw were RPM controls...
>>>>
>>>>> In case of issues, try "echo 0 > /sys/module/printk/parameters/console_suspend".
>>>>
>>>>   There's no problems suspending, it's the resuming that's a problem for me.
>>>>
>>>>> Good luck!
>>>>
>>>>   As usual, there was no luck. :-)
>>>>
>>>> WBR, Sergei
>>>
>>> Does resume work for UP (i.e. without SMP)?
>>
>>    No. My problem with resume is I can't wake up the remote system. I don't
>> see the needed 'wakeup' file in
>> /sys/devices/platform/soc/e6e60000.serial/...
>>     However, if I enable CONFIG_PM_[ADVANCED_]DEBUG and do
>>
>> $ echo -n core /sys/.power/pm_test
>>
>> the system happily wakes up after a small delay (5 s), w/either SMP or UP kernel.
>
> That seems promising but it seems curious that there is no wakeup file.
>
> On Lager the following procedure works for me using
> renesas-devel-20160613-v4.7-rc3 and shmobile defconfig.
>
> 0. Add wakeup-source property to serial at e6ce0000 node in DT

    Ah, stupid me, it was the piece that I'd overlooked!

> 1. echo enabled > /sys/devices/platform/e6e60000.serial/tty/ttySC0/power/wakeup
> 2. echo mem > /sys/power/state
> 3. Provide input on serial console
>
> * Success! *

    Yeah, works now!
    Sorry, I had no previous experience with the PM. Was unsupported feature 
back in MontaVista... :-)

>>> How did testing CPU hotplug go? Did it work for all CPUs?
>>
>>    Sure!
>
> Great!
>
>>    The only problem I'm seeing (again) is the RCAN clock failing to register:
>>
>> rcar_gen2_cpg_clocks_init: failed to register cpg_clocks rcan clock (-12)
>>
>>    I was going to look at it yesterday but (wrongly) thought it somehow
>> cured itself... I'll look at it now.
>
> Is this resolved? If not perhaps you could consider removing the node
> in question for now.

    That's what I did in v5, i.e. removed the RCAN CPG clock (not the whole 
node)...

MBR, Sergei

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Simon Horman]

On Wed, Jun 15, 2016 at 12:08:21AM +0300, Sergei Shtylyov wrote:
> Hello.
> 
> On 06/14/2016 03:43 AM, Simon Horman wrote:
> 
> >>>>[...]
> >>>>
> >>>>>>>And that the system behaves sanely on suspend/resume.
> >>>>>>
> >>>>>> I'd be thankful if you told me how to test that. :-)
> >>>>>
> >>>>>System suspend:
> >>>>>
> >>>>>  echo mem > /sys/power/state
> >>>>
> >>>>  Oh. I know that one! :-)
> >>>>
> >>>>>System resume: You're gonna need a "wakeup-source" in your DTS, e.g. gpio-keys.
> >>>>>Serial should work too, echo "enabled" to the corresponding wakeup
> >>>>>file in /sys first.
> >>>>
> >>>>  I'm afraid I couldn't find that file. All I saw were RPM controls...
> >>>>
> >>>>>In case of issues, try "echo 0 > /sys/module/printk/parameters/console_suspend".
> >>>>
> >>>>  There's no problems suspending, it's the resuming that's a problem for me.
> >>>>
> >>>>>Good luck!
> >>>>
> >>>>  As usual, there was no luck. :-)
> >>>>
> >>>>WBR, Sergei
> >>>
> >>>Does resume work for UP (i.e. without SMP)?
> >>
> >>   No. My problem with resume is I can't wake up the remote system. I don't
> >>see the needed 'wakeup' file in
> >>/sys/devices/platform/soc/e6e60000.serial/...
> >>    However, if I enable CONFIG_PM_[ADVANCED_]DEBUG and do
> >>
> >>$ echo -n core /sys/.power/pm_test
> >>
> >>the system happily wakes up after a small delay (5 s), w/either SMP or UP kernel.
> >
> >That seems promising but it seems curious that there is no wakeup file.
> >
> >On Lager the following procedure works for me using
> >renesas-devel-20160613-v4.7-rc3 and shmobile defconfig.
> >
> >0. Add wakeup-source property to serial at e6ce0000 node in DT
> 
>    Ah, stupid me, it was the piece that I'd overlooked!
> 
> >1. echo enabled > /sys/devices/platform/e6e60000.serial/tty/ttySC0/power/wakeup
> >2. echo mem > /sys/power/state
> >3. Provide input on serial console
> >
> >* Success! *
> 
>    Yeah, works now!
>    Sorry, I had no previous experience with the PM. Was unsupported feature
> back in MontaVista... :-)

Great, thanks for your persistence.

FWIW, I always have to refer to some notes in order to exercise PM.

> >>>How did testing CPU hotplug go? Did it work for all CPUs?
> >>
> >>   Sure!
> >
> >Great!
> >
> >>   The only problem I'm seeing (again) is the RCAN clock failing to register:
> >>
> >>rcar_gen2_cpg_clocks_init: failed to register cpg_clocks rcan clock (-12)
> >>
> >>   I was going to look at it yesterday but (wrongly) thought it somehow
> >>cured itself... I'll look at it now.
> >
> >Is this resolved? If not perhaps you could consider removing the node
> >in question for now.
> 
>    That's what I did in v5, i.e. removed the RCAN CPG clock (not the whole
> node)...

Great.

[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

[Geert Uytterhoeven]

On Wed, Jun 1, 2016 at 12:24 AM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> The initial R8A7792 SoC device tree including 2 CPU cores, GIC, timer, SYSC,
> and the required  clock descriptions.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
>  arch/arm/boot/dts/r8a7792.dtsi |  423 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 423 insertions(+)
>
> Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
> ===================================================================
> --- /dev/null
> +++ renesas/arch/arm/boot/dts/r8a7792.dtsi
> @@ -0,0 +1,423 @@
> +/*
> + * Device Tree Source for the r8a7792 SoC
> + *
> + * Copyright (C) 2016 Cogent Embedded Inc.
> + *
> + * This file is licensed under the terms of the GNU General Public License
> + * version 2.  This program is licensed "as is" without any warranty of any
> + * kind, whether express or implied.
> + */
> +
> +#include <dt-bindings/clock/r8a7792-clock.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/interrupt-controller/irq.h> is included
implicitly by the above.

> +#include <dt-bindings/power/r8a7792-sysc.h>
> +
> +/ {
> +       compatible = "renesas,r8a7792";
> +       interrupt-parent = <&gic>;
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               cpu0: cpu at 0 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a15";
> +                       reg = <0>;
> +                       clock-frequency = <1000000000>;
> +                       clocks = <&cpg_clocks R8A7792_CLK_Z>;
> +                       power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
> +                       next-level-cache = <&L2_CA15>;
> +               };
> +
> +               cpu1: cpu at 1 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a15";
> +                       reg = <1>;
> +                       clock-frequency = <1000000000>;
> +                       power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
> +                       next-level-cache = <&L2_CA15>;
> +               };
> +
> +               L2_CA15: cache-controller at 0 {
> +                       compatible = "cache";
> +                       reg = <0>;
> +                       cache-unified;
> +                       cache-level = <2>;
> +                       power-domains = <&sysc R8A7792_PD_CA15_SCU>;
> +               };
> +       };
> +
> +       gic: interrupt-controller at f1001000 {

It would be good to group all on-SoC devices under an "soc" node, like we
started doing for r8a7795.

> +       clocks {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               /* External root clock */
> +               extal_clk: extal {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       /* This value must be overridden by the board. */
> +                       clock-frequency = <0>;
> +               };

The fixed clocks should be at the root level these days.

> +               /* Special CPG clocks */
> +               cpg_clocks: cpg_clocks at e6150000 {
> +                       compatible = "renesas,r8a7792-cpg-clocks",
> +                                    "renesas,rcar-gen2-cpg-clocks";
> +                       reg = <0 0xe6150000 0 0x1000>;
> +                       clocks = <&extal_clk>;
> +                       #clock-cells = <1>;
> +                       clock-output-names = "main", "pll0", "pll1", "pll3",
> +                                            "lb", "qspi", "sdh", "sd0", "sd1",
> +                                            "z";

"sdh", "sd0", and "sd1" do not exist. Please remove them.

> +               z2_clk: z2 {
> +                       compatible = "fixed-factor-clock";
> +                       clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
> +                       #clock-cells = <0>;
> +                       clock-div = <2>;
> +                       clock-mult = <1>;
> +               };

V2H doesn't have Z2.

> +               i_clk: i {
> +                       compatible = "fixed-factor-clock";
> +                       clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
> +                       #clock-cells = <0>;
> +                       clock-div = <2>;
> +                       clock-mult = <1>;
> +               };

clock-div = <3>;

> +               cp_clk: cp {
> +                       compatible = "fixed-factor-clock";
> +                       clocks = <&extal_clk>;
> +                       #clock-cells = <0>;
> +                       clock-div = <2>;
> +                       clock-mult = <1>;
> +               };

On V2H, CP is derived from PLL1, cfr. CL.
The clock derived from EXTAL is called CPEX.

> +               mstp1_clks: mstp1_clks at e6150134 {
> +                       compatible = "renesas,r8a7792-mstp-clocks",
> +                                    "renesas,cpg-mstp-clocks";
> +                       reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
> +                       clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
> +                                <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
> +                       #clock-cells = <1>;
> +                       clock-indices = <
> +                               R8A7792_CLK_TMU1 R8A7792_CLK_TMU3
> +                               R8A7792_CLK_TMU2 R8A7792_CLK_CMT0
> +                               R8A7792_CLK_TMU0 R8A7792_CLK_VSP1DU1
> +                               R8A7792_CLK_VSP1DU0 R8A7792_CLK_VSP1_SY
> +                       >;
> +                       clock-output-names = "tmu1", "tmu3", "tmu2", "cmt0",
> +                                            "tmu0", "vsp1du1", "vsp1du0",

These are called "vsp1-du1", "vsp1-du0" in all other R-Car Gen2 dtsis.

> +                                            "vsp1-sy";
> +               };
> +               mstp2_clks: mstp2_clks at e6150138 {
> +                       compatible = "renesas,r8a7792-mstp-clocks",
> +                                    "renesas,cpg-mstp-clocks";
> +                       reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
> +                       clocks = <&mp_clk>, <&zs_clk>, <&zs_clk>;
> +                       #clock-cells = <1>;
> +                       clock-indices = <
> +                               R8A7792_CLK_MSIOF1
> +                               R8A7792_CLK_SYS_DMAC0 R8A7792_CLK_SYS_DMAC1

Wrong order of the DMACs.

> +                       >;
> +                       clock-output-names = "msiof1", "sys-dmac0", "sys-dmac1";

Wrong order of the DMACs.

> +               };
> +               mstp3_clks: mstp3_clks at e615013c {
> +                       compatible = "renesas,r8a7792-mstp-clocks",
> +                                    "renesas,cpg-mstp-clocks";
> +                       reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
> +                       clocks = <&cp_clk>, <&cpg_clocks R8A7792_CLK_SD0>,

As there's no SD0, this can't be correct.

> +                                <&rclk_clk>;
> +                       #clock-cells = <1>;
> +                       clock-indices = <
> +                               R8A7792_CLK_TPU0 R8A7792_CLK_SDHI0
> +                               R8A7792_CLK_CMT1
> +                       >;
> +                       clock-output-names = "tpu0", "sdhi0", "cmt1";
> +               };

> +               mstp5_clks: mstp5_clks at e6150144 {
> +                       compatible = "renesas,r8a7792-mstp-clocks",
> +                                    "renesas,cpg-mstp-clocks";
> +                       reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
> +                       clocks = <&hp_clk>, <&extal_clk>, <&p_clk>;
> +                       #clock-cells = <1>;
> +                       clock-indices = <
> +                               R8A7792_CLK_AUDIO_DMAC0
> +                               R8A7792_CLK_THERMAL R8A7792_CLK_PWM
> +                       >;
> +                       clock-output-names = "thermal", "pwm", "audmac0";

clock-output-names = "audmac0", "thermal", "pwm";

> +               };


> +               mstp9_clks: mstp9_clks at e6150994 {
> +                       compatible = "renesas,r8a7792-mstp-clocks",
> +                                    "renesas,cpg-mstp-clocks";
> +                       reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
> +                       clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
> +                                <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
> +                                <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>,
> +                                <&cpg_clocks R8A7792_CLK_QSPI>, <&cp_clk>,
> +                                <&cp_clk>, <&hp_clk>, <&cp_clk>, <&hp_clk>,
> +                                <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
> +                       #clock-cells = <1>;
> +                       clock-indices = <
> +                               R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6
> +                               R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4
> +                               R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2
> +                               R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0
> +                               R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10
> +                               R8A7792_CLK_CAN1 R8A7792_CLK_CAN0
> +                               R8A7792_CLK_QSPI_MOD R8A7792_CLK_GPIO9
> +                               R8A7792_CLK_GPIO8 R8A7792_CLK_I2C5
> +                               R8A7792_CLK_IICDVFS R8A7792_CLK_I2C4
> +                               R8A7792_CLK_I2C3 R8A7792_CLK_I2C2
> +                               R8A7792_CLK_I2C1 R8A7792_CLK_I2C0
> +                       >;
> +                       clock-output-names = "gpio7", "gpio6", "gpio5", "gpio4",
> +                                            "gpio3", "gpio2", "gpio1", "gpio0",
> +                                            "gpio11", "gpio10", "can1", "can0",

These are called "rcan1", "rcan0" in other dtsis.

> +                                            "qspi_mod", "gpio9", "gpio8",
> +                                            "i2c5", "iic3", "i2c4", "i2c3",
> +                                            "i2c2", "i2c1", "i2c0";
> +               };

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 08/13] ARM: dts: r8a7792: add SYS-DMAC support

[Sergei Shtylyov]

Describe SYS-DMAC0/1 in the R8A7792 device tree.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
 arch/arm/boot/dts/r8a7792.dtsi |   60 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi
+++ renesas/arch/arm/boot/dts/r8a7792.dtsi
@@ -80,6 +80,66 @@
 		#power-domain-cells = <1>;
 	};
 
+	dmac0: dma-controller at e6700000 {
+		compatible = "renesas,dmac-r8a7792", "renesas,rcar-dmac";
+		reg = <0 0xe6700000 0 0x20000>;
+		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "error",
+				  "ch0", "ch1", "ch2", "ch3", "ch4", "ch5",
+				  "ch6", "ch7", "ch8", "ch9", "ch10", "ch11",
+				  "ch12", "ch13", "ch14";
+		clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
+		clock-names = "fck";
+		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+		#dma-cells = <1>;
+		dma-channels = <15>;
+	};
+
+	dmac1: dma-controller at e6720000 {
+		compatible = "renesas,dmac-r8a7792", "renesas,rcar-dmac";
+		reg = <0 0xe6720000 0 0x20000>;
+		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "error",
+				  "ch0", "ch1", "ch2", "ch3", "ch4", "ch5",
+				  "ch6", "ch7",	"ch8", "ch9", "ch10", "ch11",
+				  "ch12", "ch13", "ch14";
+		clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
+		clock-names = "fck";
+		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+		#dma-cells = <1>;
+		dma-channels = <15>;
+	};
+
 	clocks {
 		#address-cells = <2>;
 		#size-cells = <2>;

[PATCH 08/13] ARM: dts: r8a7792: add SYS-DMAC support

[Simon Horman]

On Wed, Jun 01, 2016 at 01:25:24AM +0300, Sergei Shtylyov wrote:
> Describe SYS-DMAC0/1 in the R8A7792 device tree.
> 
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Acked-by: Simon Horman <horms+renesas@verge.net.au>

[PATCH 08/13] ARM: dts: r8a7792: add SYS-DMAC support

[Geert Uytterhoeven]

On Wed, Jun 1, 2016 at 12:25 AM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe SYS-DMAC0/1 in the R8A7792 device tree.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 09/13] ARM: dts: r8a7792: add [H]SCIF support

[Sergei Shtylyov]

Describe [H]SCIFs in the R8A7792 device tree.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
 arch/arm/boot/dts/r8a7792.dtsi |   90 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 90 insertions(+)

Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi
+++ renesas/arch/arm/boot/dts/r8a7792.dtsi
@@ -140,6 +140,96 @@
 		dma-channels = <15>;
 	};
 
+	scif0: serial at e6e60000 {
+		compatible = "renesas,scif-r8a7792", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
+		reg = <0 0xe6e60000 0 64>;
+		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+		       <&dmac1 0x29>, <&dmac1 0x2a>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
+	scif1: serial at e6e68000 {
+		compatible = "renesas,scif-r8a7792", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
+		reg = <0 0xe6e68000 0 64>;
+		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+		       <&dmac1 0x2d>, <&dmac1 0x2e>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
+	scif2: serial at e6e58000 {
+		compatible = "renesas,scif-r8a7792", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
+		reg = <0 0xe6e58000 0 64>;
+		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+		       <&dmac1 0x2b>, <&dmac1 0x2c>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
+	scif3: serial at e6ea8000 {
+		compatible = "renesas,scif-r8a7792", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
+		reg = <0 0xe6ea8000 0 64>;
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+		       <&dmac1 0x2f>, <&dmac1 0x30>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
+	hscif0: serial at e62c0000 {
+		compatible = "renesas,hscif-r8a7792", "renesas,rcar-gen2-hscif",
+			     "renesas,hscif";
+		reg = <0 0xe62c0000 0 96>;
+		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+		       <&dmac1 0x39>, <&dmac1 0x3a>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
+	hscif1: serial at e62c8000 {
+		compatible = "renesas,hscif-r8a7792", "renesas,rcar-gen2-hscif",
+			     "renesas,hscif";
+		reg = <0 0xe62c8000 0 96>;
+		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+		       <&dmac1 0x4d>, <&dmac1 0x4e>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
 	clocks {
 		#address-cells = <2>;
 		#size-cells = <2>;

[PATCH 09/13] ARM: dts: r8a7792: add [H]SCIF support

[Simon Horman]

On Wed, Jun 01, 2016 at 01:26:56AM +0300, Sergei Shtylyov wrote:
> Describe [H]SCIFs in the R8A7792 device tree.
> 
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

This looks correct to me.

I am wondering if you have been able to confirm DMA operation of the
devices enabled later on in the series.

> 
> ---
>  arch/arm/boot/dts/r8a7792.dtsi |   90 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 90 insertions(+)
> 
> Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
> ===================================================================
> --- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi
> +++ renesas/arch/arm/boot/dts/r8a7792.dtsi
> @@ -140,6 +140,96 @@
>  		dma-channels = <15>;
>  	};
>  
> +	scif0: serial at e6e60000 {
> +		compatible = "renesas,scif-r8a7792", "renesas,rcar-gen2-scif",
> +			     "renesas,scif";
> +		reg = <0 0xe6e60000 0 64>;
> +		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
> +			 <&scif_clk>;
> +		clock-names = "fck", "brg_int", "scif_clk";
> +		dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
> +		       <&dmac1 0x29>, <&dmac1 0x2a>;
> +		dma-names = "tx", "rx", "tx", "rx";
> +		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
> +		status = "disabled";
> +	};
> +
> +	scif1: serial at e6e68000 {
> +		compatible = "renesas,scif-r8a7792", "renesas,rcar-gen2-scif",
> +			     "renesas,scif";
> +		reg = <0 0xe6e68000 0 64>;
> +		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
> +			 <&scif_clk>;
> +		clock-names = "fck", "brg_int", "scif_clk";
> +		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
> +		       <&dmac1 0x2d>, <&dmac1 0x2e>;
> +		dma-names = "tx", "rx", "tx", "rx";
> +		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
> +		status = "disabled";
> +	};
> +
> +	scif2: serial at e6e58000 {
> +		compatible = "renesas,scif-r8a7792", "renesas,rcar-gen2-scif",
> +			     "renesas,scif";
> +		reg = <0 0xe6e58000 0 64>;
> +		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
> +			 <&scif_clk>;
> +		clock-names = "fck", "brg_int", "scif_clk";
> +		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
> +		       <&dmac1 0x2b>, <&dmac1 0x2c>;
> +		dma-names = "tx", "rx", "tx", "rx";
> +		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
> +		status = "disabled";
> +	};
> +
> +	scif3: serial at e6ea8000 {
> +		compatible = "renesas,scif-r8a7792", "renesas,rcar-gen2-scif",
> +			     "renesas,scif";
> +		reg = <0 0xe6ea8000 0 64>;
> +		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
> +			 <&scif_clk>;
> +		clock-names = "fck", "brg_int", "scif_clk";
> +		dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
> +		       <&dmac1 0x2f>, <&dmac1 0x30>;
> +		dma-names = "tx", "rx", "tx", "rx";
> +		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
> +		status = "disabled";
> +	};
> +
> +	hscif0: serial at e62c0000 {
> +		compatible = "renesas,hscif-r8a7792", "renesas,rcar-gen2-hscif",
> +			     "renesas,hscif";
> +		reg = <0 0xe62c0000 0 96>;
> +		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
> +			 <&scif_clk>;
> +		clock-names = "fck", "brg_int", "scif_clk";
> +		dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
> +		       <&dmac1 0x39>, <&dmac1 0x3a>;
> +		dma-names = "tx", "rx", "tx", "rx";
> +		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
> +		status = "disabled";
> +	};
> +
> +	hscif1: serial at e62c8000 {
> +		compatible = "renesas,hscif-r8a7792", "renesas,rcar-gen2-hscif",
> +			     "renesas,hscif";
> +		reg = <0 0xe62c8000 0 96>;
> +		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
> +			 <&scif_clk>;
> +		clock-names = "fck", "brg_int", "scif_clk";
> +		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
> +		       <&dmac1 0x4d>, <&dmac1 0x4e>;
> +		dma-names = "tx", "rx", "tx", "rx";
> +		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
> +		status = "disabled";
> +	};
> +
>  	clocks {
>  		#address-cells = <2>;
>  		#size-cells = <2>;
> 

[PATCH 09/13] ARM: dts: r8a7792: add [H]SCIF support

[Sergei Shtylyov]

On 06/01/2016 04:13 AM, Simon Horman wrote:

>> Describe [H]SCIFs in the R8A7792 device tree.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> This looks correct to me.
>
> I am wondering if you have been able to confirm DMA operation of the
> devices enabled later on in the series.

    The SCIF DMA seems to work now that enabled it in the driver. Not sure 
what you meant by "the devices enabled later in the seties"...

MBR, Sergei

[PATCH 09/13] ARM: dts: r8a7792: add [H]SCIF support

[Geert Uytterhoeven]

On Wed, Jun 1, 2016 at 12:26 AM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe [H]SCIFs in the R8A7792 device tree.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 10/13] ARM: dts: r8a7792: add IRQC support

[Sergei Shtylyov]

Describe the IRQC interrupt controller in the R8A7792 device tree.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
 arch/arm/boot/dts/r8a7792.dtsi |   13 +++++++++++++
 1 file changed, 13 insertions(+)

Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi
+++ renesas/arch/arm/boot/dts/r8a7792.dtsi
@@ -62,6 +62,19 @@
 			      IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
+	irqc: interrupt-controller at e61c0000 {
+		compatible = "renesas,irqc-r8a7792", "renesas,irqc";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		reg = <0 0xe61c0000 0 0x200>;
+		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp4_clks R8A7792_CLK_IRQC>;
+		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <GIC_PPI 13

[PATCH 10/13] ARM: dts: r8a7792: add IRQC support

[Simon Horman]

On Wed, Jun 01, 2016 at 01:29:05AM +0300, Sergei Shtylyov wrote:
> Describe the IRQC interrupt controller in the R8A7792 device tree.
> 
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> 
> ---
>  arch/arm/boot/dts/r8a7792.dtsi |   13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
> ===================================================================
> --- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi
> +++ renesas/arch/arm/boot/dts/r8a7792.dtsi
> @@ -62,6 +62,19 @@
>  			      IRQ_TYPE_LEVEL_HIGH)>;
>  	};
>  
> +	irqc: interrupt-controller at e61c0000 {

Could you consider using irqc0 as the node name for consistency with the
DT of other R-Car Gen2 SoCs?

What follows looks correct to me.

> +		compatible = "renesas,irqc-r8a7792", "renesas,irqc";
> +		#interrupt-cells = <2>;
> +		interrupt-controller;
> +		reg = <0 0xe61c0000 0 0x200>;
> +		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp4_clks R8A7792_CLK_IRQC>;
> +		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
> +	};
> +
>  	timer {
>  		compatible = "arm,armv7-timer";
>  		interrupts = <GIC_PPI 13
> 

[PATCH 10/13] ARM: dts: r8a7792: add IRQC support

[Sergei Shtylyov]

On 06/01/2016 04:18 AM, Simon Horman wrote:

>> Describe the IRQC interrupt controller in the R8A7792 device tree.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>>  arch/arm/boot/dts/r8a7792.dtsi |   13 +++++++++++++
>>  1 file changed, 13 insertions(+)
>>
>> Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
>> ===================================================================
>> --- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi
>> +++ renesas/arch/arm/boot/dts/r8a7792.dtsi
>> @@ -62,6 +62,19 @@
>>  			      IRQ_TYPE_LEVEL_HIGH)>;
>>  	};
>>
>> +	irqc: interrupt-controller at e61c0000 {
>
> Could you consider using irqc0 as the node name for consistency with the
> DT of other R-Car Gen2 SoCs?

    Frankly speaking I didn't get that name indexing thing at all. Could you 
share the reasoning behind it?

> What follows looks correct to me.

    Thank you. :-)

MBR, Sergei

[PATCH 10/13] ARM: dts: r8a7792: add IRQC support

[Geert Uytterhoeven]

On Wed, Jun 1, 2016 at 12:29 AM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe the IRQC interrupt controller in the R8A7792 device tree.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 12/13] ARM: dts: blanche: initial device tree

[Sergei Shtylyov]

Add the initial device  tree for the R8A7792 SoC based Blanche board.
The board has 2 debug serial ports: SCIF0 and SCIF3; include support for
them,  so that  the serial console  can  work.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
 arch/arm/boot/dts/Makefile            |    1 
 arch/arm/boot/dts/r8a7792-blanche.dts |   44 ++++++++++++++++++++++++++++++++++
 2 files changed, 45 insertions(+)

Index: renesas/arch/arm/boot/dts/Makefile
===================================================================
--- renesas.orig/arch/arm/boot/dts/Makefile
+++ renesas/arch/arm/boot/dts/Makefile
@@ -638,6 +638,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
 	r8a7790-lager.dtb \
 	r8a7791-koelsch.dtb \
 	r8a7791-porter.dtb \
+	r8a7792-blanche.dtb \
 	r8a7793-gose.dtb \
 	r8a7794-alt.dtb \
 	r8a7794-silk.dtb \
Index: renesas/arch/arm/boot/dts/r8a7792-blanche.dts
===================================================================
--- /dev/null
+++ renesas/arch/arm/boot/dts/r8a7792-blanche.dts
@@ -0,0 +1,44 @@
+/*
+ * Device Tree Source for the Blanche board
+ *
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7792.dtsi"
+
+/ {
+	model = "Blanche";
+	compatible = "renesas,blanche", "renesas,r8a7792";
+
+	aliases {
+		serial0 = &scif0;
+		serial1 = &scif3;
+	};
+
+	chosen {
+		bootargs = "ignore_loglevel";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory at 40000000 {
+		device_type = "memory";
+		reg = <0 0x40000000 0 0x40000000>;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <20000000>;
+};
+
+&scif0 {
+	status = "okay";
+};
+
+&scif3 {
+	status = "okay";
+};

[PATCH 12/13] ARM: dts: blanche: initial device tree

[Simon Horman]

On Wed, Jun 01, 2016 at 01:32:35AM +0300, Sergei Shtylyov wrote:
> Add the initial device  tree for the R8A7792 SoC based Blanche board.
> The board has 2 debug serial ports: SCIF0 and SCIF3; include support for
> them,  so that  the serial console  can  work.
> 
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

At this time I do not have access to documentation or hardware for this
board. So I am relying on you to test this and make sure it complies
with the spec.

What you have looks reasonable to me:

Acked-by: Simon Horman <horms+renesas@verge.net.au>

[PATCH 12/13] ARM: dts: blanche: initial device tree

[Sergei Shtylyov]

On 06/01/2016 04:21 AM, Simon Horman wrote:

>> Add the initial device  tree for the R8A7792 SoC based Blanche board.
>> The board has 2 debug serial ports: SCIF0 and SCIF3; include support for
>> them,  so that  the serial console  can  work.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> At this time I do not have access to documentation or hardware for this
> board. So I am relying on you to test this and make sure it complies
> with the spec.

    Don't worry, the patches have been tested on the real hardware.

> What you have looks reasonable to me:
>
> Acked-by: Simon Horman <horms+renesas@verge.net.au>

    Thank you. :-)

MBR, Sergei

[PATCH 12/13] ARM: dts: blanche: initial device tree

[Geert Uytterhoeven]

On Wed, Jun 1, 2016 at 12:32 AM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add the initial device  tree for the R8A7792 SoC based Blanche board.
> The board has 2 debug serial ports: SCIF0 and SCIF3; include support for
> them,  so that  the serial console  can  work.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 13/13] ARM: dts: blanche: add Ethernet support

[Sergei Shtylyov]

R8A7792  SoC  doesn't have the EtherMAC core, so SMSC  LAN89218  Ethernet
chip was used instead on the Blanche board; this chip  is compatible with
SMSC LAN9115  for  which there's a (device tree aware) driver. Describe
the  chip in  the  Blanche device tree;  enable DHCP and NFS root in the
kernel command line for the kernel booting.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
 arch/arm/boot/dts/r8a7792-blanche.dts |   23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

Index: renesas/arch/arm/boot/dts/r8a7792-blanche.dts
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7792-blanche.dts
+++ renesas/arch/arm/boot/dts/r8a7792-blanche.dts
@@ -21,7 +21,7 @@
 	};
 
 	chosen {
-		bootargs = "ignore_loglevel";
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -29,6 +29,27 @@
 		device_type = "memory";
 		reg = <0 0x40000000 0 0x40000000>;
 	};
+
+	d3_3v: regulator-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "D3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	ethernet at 18000000 {
+		compatible = "smsc,lan89218", "smsc,lan9115";
+		reg = <0 0x18000000 0 0x100>;
+		phy-mode = "mii";
+		interrupt-parent = <&irqc>;
+		interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+		smsc,irq-push-pull;
+		reg-io-width = <4>;
+		vddvario-supply = <&d3_3v>;
+		vdd33a-supply = <&d3_3v>;
+	};
 };
 
 &extal_clk {

[PATCH 13/13] ARM: dts: blanche: add Ethernet support

[Simon Horman]

On Wed, Jun 01, 2016 at 01:33:49AM +0300, Sergei Shtylyov wrote:
> R8A7792  SoC  doesn't have the EtherMAC core, so SMSC  LAN89218  Ethernet
> chip was used instead on the Blanche board; this chip  is compatible with
> SMSC LAN9115  for  which there's a (device tree aware) driver. Describe
> the  chip in  the  Blanche device tree;  enable DHCP and NFS root in the
> kernel command line for the kernel booting.
> 
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

At this time I do not have access to documentation or hardware for this
board. So I am relying on you to test this and make sure it complies
with the spec.

What you have looks reasonable to me:

Acked-by: Simon Horman <horms+renesas@verge.net.au>

[PATCH 13/13] ARM: dts: blanche: add Ethernet support

[Geert Uytterhoeven]

Hi Sergei,

On Wed, Jun 1, 2016 at 12:33 AM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> --- renesas.orig/arch/arm/boot/dts/r8a7792-blanche.dts
> +++ renesas/arch/arm/boot/dts/r8a7792-blanche.dts

> +       ethernet at 18000000 {
> +               compatible = "smsc,lan89218", "smsc,lan9115";

The "smsc,lan89218" needs to be documented in the device tree bindings.
Google couldn't find any evidence you submitted a patch for that.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 13/13] ARM: dts: blanche: add Ethernet support

[Sergei Shtylyov]

Hello.

On 6/1/2016 11:22 AM, Geert Uytterhoeven wrote:

>> --- renesas.orig/arch/arm/boot/dts/r8a7792-blanche.dts
>> +++ renesas/arch/arm/boot/dts/r8a7792-blanche.dts
>
>> +       ethernet at 18000000 {
>> +               compatible = "smsc,lan89218", "smsc,lan9115";
>
> The "smsc,lan89218" needs to be documented in the device tree bindings.

    Have you looked at those bindings?

> Google couldn't find any evidence you submitted a patch for that.

    Because the bindings document *any* LAN9115 compatible chip already.

> Gr{oetje,eeting}s,
>
>                         Geert

MBR, Sergei

[PATCH 13/13] ARM: dts: blanche: add Ethernet support

[Geert Uytterhoeven]

Hi Sergei,

On Wed, Jun 1, 2016 at 2:16 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> On 6/1/2016 11:22 AM, Geert Uytterhoeven wrote:
>>> --- renesas.orig/arch/arm/boot/dts/r8a7792-blanche.dts
>>> +++ renesas/arch/arm/boot/dts/r8a7792-blanche.dts
>>
>>> +       ethernet at 18000000 {
>>> +               compatible = "smsc,lan89218", "smsc,lan9115";
>>
>>
>> The "smsc,lan89218" needs to be documented in the device tree bindings.
>
>    Have you looked at those bindings?

Now I did.

>> Google couldn't find any evidence you submitted a patch for that.
>
>    Because the bindings document *any* LAN9115 compatible chip already.

Ah, generic wildcard, not listing valid values. Hence checkpatch complained...

Google predict-while-you-type suggests "lan89218aq"? Should you use that?
BTW, that's why we always want to document all valid values...

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 13/13] ARM: dts: blanche: add Ethernet support

[Sergei Shtylyov]

On 06/01/2016 03:27 PM, Geert Uytterhoeven wrote:

>>>> --- renesas.orig/arch/arm/boot/dts/r8a7792-blanche.dts
>>>> +++ renesas/arch/arm/boot/dts/r8a7792-blanche.dts
>>>
>>>> +       ethernet at 18000000 {
>>>> +               compatible = "smsc,lan89218", "smsc,lan9115";
>>>
>>>
>>> The "smsc,lan89218" needs to be documented in the device tree bindings.
>>
>>    Have you looked at those bindings?
>
> Now I did.
>
>>> Google couldn't find any evidence you submitted a patch for that.
>>
>>    Because the bindings document *any* LAN9115 compatible chip already.
>
> Ah, generic wildcard, not listing valid values. Hence checkpatch complained...

    Note that it doesn't complain about "smsc,lan9220" though that is only 
mentioned in the example.

> Google predict-while-you-type suggests "lan89218aq"? Should you use that?

    No, my googling shows that the suffix can be different, and the Microchip 
(the new owner?) has it without the suffix on their site.

> BTW, that's why we always want to document all valid values...

> Gr{oetje,eeting}s,
>
>                         Geert

MBR, Sergei

[PATCH 00/13] Add R8A7794/SILK board eMMC DT support

[Geert Uytterhoeven]

Hi Sergei,

On Wed, Jun 1, 2016 at 12:06 AM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
>    Here's the set of 13 patches against Simon Horman's 'renesas.git' repo,
> 'renesas-devel-20160530-v4.7-rc1' tag. We add the device tree support for
> the R8A7792-based Blanche board. The R-Car 'clk' driver patch was posted last
> week separately...
>
> [01/13] ARM: shmobile: r8a7792: add clock index macros
> [02/13] ARM: shmobile: r8a7792: add power domain index macros
> [03/13] soc: renesas: rcar-sysc: add R8A7792 support
> [04/13] ARM: shmobile: r8a7792: basic SoC support
> [05/13] DT: clock: rcar-gen2-cpg-clocks: document R8A7792 support
> [06/13] DT: clock: cpg-mstp-clocks: document-R8A7792-support
> [07/13] ARM: dts: r8a7792: initial SoC device tree
> [08/13] ARM: dts: r8a7792: add SYS-DMAC support
> [09/13] ARM: dts: r8a7792: add [H]SCIF support
> [10/13] ARM dts: r8a7792: add IRQC support
> [11/13] DT: arm: shmobile: document Blanche board
> [12/13] ARM: dts: blanche: initial device tree
> [13/13] ARM: dts: blanche: add Ethernet support

Thanks for your series!

The subject doesn't seem to cover the contents, though:
> [PATCH 00/13] Add R8A7794/SILK board eMMC DT support

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 00/13] Add R8A7794/SILK board eMMC DT support

[Sergei Shtylyov]

Hello.

On 6/1/2016 10:04 AM, Geert Uytterhoeven wrote:

>>    Here's the set of 13 patches against Simon Horman's 'renesas.git' repo,
>> 'renesas-devel-20160530-v4.7-rc1' tag. We add the device tree support for
>> the R8A7792-based Blanche board. The R-Car 'clk' driver patch was posted last
>> week separately...
>>
>> [01/13] ARM: shmobile: r8a7792: add clock index macros
>> [02/13] ARM: shmobile: r8a7792: add power domain index macros
>> [03/13] soc: renesas: rcar-sysc: add R8A7792 support
>> [04/13] ARM: shmobile: r8a7792: basic SoC support
>> [05/13] DT: clock: rcar-gen2-cpg-clocks: document R8A7792 support
>> [06/13] DT: clock: cpg-mstp-clocks: document-R8A7792-support
>> [07/13] ARM: dts: r8a7792: initial SoC device tree
>> [08/13] ARM: dts: r8a7792: add SYS-DMAC support
>> [09/13] ARM: dts: r8a7792: add [H]SCIF support
>> [10/13] ARM dts: r8a7792: add IRQC support
>> [11/13] DT: arm: shmobile: document Blanche board
>> [12/13] ARM: dts: blanche: initial device tree
>> [13/13] ARM: dts: blanche: add Ethernet support
>
> Thanks for your series!
>
> The subject doesn't seem to cover the contents, though:
>> [PATCH 00/13] Add R8A7794/SILK board eMMC DT support

    Oops. :-(
    Sorry about that...

> Gr{oetje,eeting}s,
>
>                         Geert

MBR, Sergei