* [PATCH 0/11] Add R8A7745/SK-RZG1E board support
@ 2016-10-28 22:04 Sergei Shtylyov
2016-10-28 22:07 ` [PATCH 01/11] ARM: shmobile: r8a7745: add power domain index macros Sergei Shtylyov
` (9 more replies)
0 siblings, 10 replies; 23+ messages in thread
From: Sergei Shtylyov @ 2016-10-28 22:04 UTC (permalink / raw)
To: linux-arm-kernel
Hello.
Here's the set of 11 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20161027-v4.9-rc2' tag plus the R8A7743/SK-RZG1M patch series.
I'm adding the device tree support for the R8A7745-based SK-RZG1E board.
The SoC is close to R8A7794 and the board seems identical to the R8A7794/SILK
board. The device tree patches depend on the R8A7745 CPG/MSSR driver series
just posted in order to compile and work.
[01/12] ARM: shmobile: r8a7745: add power domain index macros
[02/12] soc: renesas: rcar-sysc: add R8A7745 support
[03/12] ARM: shmobile: r8a7745: basic SoC support
[04/12] ARM: dts: r8a7745: initial SoC device tree
[05/12] ARM: dts: r8a7745: add SYS-DMAC support
[06/12] ARM: dts: r8a7745: add [H]SCIF{A|B} support
[07/12] ARM: dts: r8a7745: add Ether support
[08/12] ARM: dts: r8a7745: add IRQC support
[09/12] ARM: shmobile: document SK-RZG1M board
[10/12] ARM: dts: sk-rzg1e: initial device tree
[11/12] ARM: dts: sk-rzg1e: add Ether support
WBR, Sergei
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 01/11] ARM: shmobile: r8a7745: add power domain index macros 2016-10-28 22:04 [PATCH 0/11] Add R8A7745/SK-RZG1E board support Sergei Shtylyov @ 2016-10-28 22:07 ` Sergei Shtylyov 2016-11-02 9:46 ` Geert Uytterhoeven 2016-10-28 22:16 ` [PATCH 03/11] ARM: shmobile: r8a7745: basic SoC support Sergei Shtylyov ` (8 subsequent siblings) 9 siblings, 1 reply; 23+ messages in thread From: Sergei Shtylyov @ 2016-10-28 22:07 UTC (permalink / raw) To: linux-arm-kernel Add macros usable by the device tree sources to reference R8A7745 SYSC power domains by index. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- include/dt-bindings/power/r8a7745-sysc.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) Index: renesas/include/dt-bindings/power/r8a7745-sysc.h =================================================================== --- /dev/null +++ renesas/include/dt-bindings/power/r8a7745-sysc.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __DT_BINDINGS_POWER_R8A7745_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7745_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7745_PD_CA7_CPU0 5 +#define R8A7745_PD_CA7_CPU1 6 +#define R8A7745_PD_SGX 20 +#define R8A7745_PD_CA7_SCU 21 + +/* Always-on power area */ +#define R8A7745_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7745_SYSC_H__ */ ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 01/11] ARM: shmobile: r8a7745: add power domain index macros 2016-10-28 22:07 ` [PATCH 01/11] ARM: shmobile: r8a7745: add power domain index macros Sergei Shtylyov @ 2016-11-02 9:46 ` Geert Uytterhoeven 0 siblings, 0 replies; 23+ messages in thread From: Geert Uytterhoeven @ 2016-11-02 9:46 UTC (permalink / raw) To: linux-arm-kernel On Sat, Oct 29, 2016 at 12:07 AM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Add macros usable by the device tree sources to reference R8A7745 SYSC power > domains by index. > > Based on the original (and large) patch by Dmitry Shifrin > <dmitry.shifrin@cogentembedded.com>. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 03/11] ARM: shmobile: r8a7745: basic SoC support 2016-10-28 22:04 [PATCH 0/11] Add R8A7745/SK-RZG1E board support Sergei Shtylyov 2016-10-28 22:07 ` [PATCH 01/11] ARM: shmobile: r8a7745: add power domain index macros Sergei Shtylyov @ 2016-10-28 22:16 ` Sergei Shtylyov 2016-10-31 6:22 ` Rob Herring 2016-11-02 9:49 ` Geert Uytterhoeven 2016-10-28 22:17 ` [PATCH 04/11] ARM: dts: r8a7745: initial SoC device tree Sergei Shtylyov ` (7 subsequent siblings) 9 siblings, 2 replies; 23+ messages in thread From: Sergei Shtylyov @ 2016-10-28 22:16 UTC (permalink / raw) To: linux-arm-kernel Add minimal support for the RZ/G1E (R8A7745) SoC. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ arch/arm/mach-shmobile/Kconfig | 4 ++++ arch/arm/mach-shmobile/setup-rcar-gen2.c | 1 + 3 files changed, 7 insertions(+) Index: renesas/Documentation/devicetree/bindings/arm/shmobile.txt =================================================================== --- renesas.orig/Documentation/devicetree/bindings/arm/shmobile.txt +++ renesas/Documentation/devicetree/bindings/arm/shmobile.txt @@ -15,6 +15,8 @@ SoCs: compatible = "renesas,r8a7740" - RZ/G1M (R8A77430) compatible = "renesas,r8a7743" + - RZ/G1E (R8A77450) + compatible = "renesas,r8a7745" - R-Car M1A (R8A77781) compatible = "renesas,r8a7778" - R-Car H1 (R8A77790) Index: renesas/arch/arm/mach-shmobile/Kconfig =================================================================== --- renesas.orig/arch/arm/mach-shmobile/Kconfig +++ renesas/arch/arm/mach-shmobile/Kconfig @@ -73,6 +73,10 @@ config ARCH_R8A7743 select ARCH_RCAR_GEN2 select ARM_ERRATA_798181 if SMP +config ARCH_R8A7745 + bool "RZ/G1E (R8A77450)" + select ARCH_RCAR_GEN2 + config ARCH_R8A7778 bool "R-Car M1A (R8A77781)" select ARCH_RCAR_GEN1 Index: renesas/arch/arm/mach-shmobile/setup-rcar-gen2.c =================================================================== --- renesas.orig/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ renesas/arch/arm/mach-shmobile/setup-rcar-gen2.c @@ -225,6 +225,7 @@ MACHINE_END static const char * const rz_g1_boards_compat_dt[] __initconst = { "renesas,r8a7743", + "renesas,r8a7745", NULL, }; ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 03/11] ARM: shmobile: r8a7745: basic SoC support 2016-10-28 22:16 ` [PATCH 03/11] ARM: shmobile: r8a7745: basic SoC support Sergei Shtylyov @ 2016-10-31 6:22 ` Rob Herring 2016-11-02 9:49 ` Geert Uytterhoeven 1 sibling, 0 replies; 23+ messages in thread From: Rob Herring @ 2016-10-31 6:22 UTC (permalink / raw) To: linux-arm-kernel On Sat, Oct 29, 2016 at 01:16:54AM +0300, Sergei Shtylyov wrote: > Add minimal support for the RZ/G1E (R8A7745) SoC. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > --- > Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ Acked-by: Rob Herring <robh@kernel.org> > arch/arm/mach-shmobile/Kconfig | 4 ++++ > arch/arm/mach-shmobile/setup-rcar-gen2.c | 1 + > 3 files changed, 7 insertions(+) ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 03/11] ARM: shmobile: r8a7745: basic SoC support 2016-10-28 22:16 ` [PATCH 03/11] ARM: shmobile: r8a7745: basic SoC support Sergei Shtylyov 2016-10-31 6:22 ` Rob Herring @ 2016-11-02 9:49 ` Geert Uytterhoeven 1 sibling, 0 replies; 23+ messages in thread From: Geert Uytterhoeven @ 2016-11-02 9:49 UTC (permalink / raw) To: linux-arm-kernel On Sat, Oct 29, 2016 at 12:16 AM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Add minimal support for the RZ/G1E (R8A7745) SoC. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 04/11] ARM: dts: r8a7745: initial SoC device tree 2016-10-28 22:04 [PATCH 0/11] Add R8A7745/SK-RZG1E board support Sergei Shtylyov 2016-10-28 22:07 ` [PATCH 01/11] ARM: shmobile: r8a7745: add power domain index macros Sergei Shtylyov 2016-10-28 22:16 ` [PATCH 03/11] ARM: shmobile: r8a7745: basic SoC support Sergei Shtylyov @ 2016-10-28 22:17 ` Sergei Shtylyov 2016-11-02 10:03 ` Geert Uytterhoeven 2016-10-28 22:18 ` [PATCH 05/11] ARM: dts: r8a7745: add SYS-DMAC support Sergei Shtylyov ` (6 subsequent siblings) 9 siblings, 1 reply; 23+ messages in thread From: Sergei Shtylyov @ 2016-10-28 22:17 UTC (permalink / raw) To: linux-arm-kernel The initial R8A7745 SoC device tree including CPU0, GIC, timer, SYSC, RST, CPG, and the required clock descriptions. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- arch/arm/boot/dts/r8a7745.dtsi | 120 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7745.dtsi =================================================================== --- /dev/null +++ renesas/arch/arm/boot/dts/r8a7745.dtsi @@ -0,0 +1,120 @@ +/* + * Device Tree Source for the r8a7745 SoC + * + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r8a7745-cpg-mssr.h> +#include <dt-bindings/power/r8a7745-sysc.h> + +/ { + compatible = "renesas,r8a7745"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; + power-domains = <&sysc R8A7745_PD_CA7_CPU0>; + next-level-cache = <&L2_CA7>; + }; + + L2_CA7: cache-controller at 0 { + compatible = "cache"; + reg = <0>; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7745_PD_CA7_SCU>; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller at f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + cpg: clock-controller at e6150000 { + compatible = "renesas,r8a7745-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + }; + + sysc: system-controller at e6180000 { + compatible = "renesas,r8a7745-sysc"; + reg = <0 0xe6180000 0 0x200>; + #power-domain-cells = <1>; + }; + + rst: reset-controller at e6160000 { + compatible = "renesas,r8a7745-rst"; + reg = <0 0xe6160000 0 0x100>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; +}; ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 04/11] ARM: dts: r8a7745: initial SoC device tree 2016-10-28 22:17 ` [PATCH 04/11] ARM: dts: r8a7745: initial SoC device tree Sergei Shtylyov @ 2016-11-02 10:03 ` Geert Uytterhoeven 0 siblings, 0 replies; 23+ messages in thread From: Geert Uytterhoeven @ 2016-11-02 10:03 UTC (permalink / raw) To: linux-arm-kernel On Sat, Oct 29, 2016 at 12:17 AM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > The initial R8A7745 SoC device tree including CPU0, GIC, timer, SYSC, RST, > CPG, and the required clock descriptions. > > Based on the original (and large) patch by Dmitry Shifrin > <dmitry.shifrin@cogentembedded.com>. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > arch/arm/boot/dts/r8a7745.dtsi | 120 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 120 insertions(+) > > Index: renesas/arch/arm/boot/dts/r8a7745.dtsi > =================================================================== > --- /dev/null > +++ renesas/arch/arm/boot/dts/r8a7745.dtsi > + gic: interrupt-controller at f1001000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0 0xf1001000 0 0x1000>, > + <0 0xf1002000 0 0x1000>, > + <0 0xf1004000 0 0x2000>, > + <0 0xf1006000 0 0x2000>; > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | > + IRQ_TYPE_LEVEL_HIGH)>; You may want to align IRQ_TYPE_LEVEL_HIGH with GIC_CPU_MASK_SIMPLE. > + }; > + > + timer { > + compatible = "arm,armv7-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | > + IRQ_TYPE_LEVEL_LOW)>; Likewise. > + }; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 05/11] ARM: dts: r8a7745: add SYS-DMAC support 2016-10-28 22:04 [PATCH 0/11] Add R8A7745/SK-RZG1E board support Sergei Shtylyov ` (2 preceding siblings ...) 2016-10-28 22:17 ` [PATCH 04/11] ARM: dts: r8a7745: initial SoC device tree Sergei Shtylyov @ 2016-10-28 22:18 ` Sergei Shtylyov 2016-11-02 10:08 ` Geert Uytterhoeven 2016-10-28 22:19 ` [PATCH 06/11] ARM: dts: r8a7745: add [H]SCIF{A|B} support Sergei Shtylyov ` (5 subsequent siblings) 9 siblings, 1 reply; 23+ messages in thread From: Sergei Shtylyov @ 2016-10-28 22:18 UTC (permalink / raw) To: linux-arm-kernel Describe SYS-DMAC0/1 in the R8A7745 device tree. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- arch/arm/boot/dts/r8a7745.dtsi | 64 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7745.dtsi =================================================================== --- renesas.orig/arch/arm/boot/dts/r8a7745.dtsi +++ renesas/arch/arm/boot/dts/r8a7745.dtsi @@ -93,6 +93,70 @@ compatible = "renesas,r8a7745-rst"; reg = <0 0xe6160000 0 0x0200>; }; + + dmac0: dma-controller at e6700000 { + compatible = "renesas,dmac-r8a7745", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller at e6720000 { + compatible = "renesas,dmac-r8a7745", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; }; /* External root clock */ ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 05/11] ARM: dts: r8a7745: add SYS-DMAC support 2016-10-28 22:18 ` [PATCH 05/11] ARM: dts: r8a7745: add SYS-DMAC support Sergei Shtylyov @ 2016-11-02 10:08 ` Geert Uytterhoeven 0 siblings, 0 replies; 23+ messages in thread From: Geert Uytterhoeven @ 2016-11-02 10:08 UTC (permalink / raw) To: linux-arm-kernel On Sat, Oct 29, 2016 at 12:18 AM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Describe SYS-DMAC0/1 in the R8A7745 device tree. > > Based on the original (and large) patch by Dmitry Shifrin > <dmitry.shifrin@cogentembedded.com>. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 06/11] ARM: dts: r8a7745: add [H]SCIF{A|B} support 2016-10-28 22:04 [PATCH 0/11] Add R8A7745/SK-RZG1E board support Sergei Shtylyov ` (3 preceding siblings ...) 2016-10-28 22:18 ` [PATCH 05/11] ARM: dts: r8a7745: add SYS-DMAC support Sergei Shtylyov @ 2016-10-28 22:19 ` Sergei Shtylyov 2016-11-02 10:12 ` Geert Uytterhoeven 2016-11-15 17:55 ` Simon Horman 2016-10-28 22:21 ` [PATCH 07/11] ARM: dts: r8a7745: add Ether support Sergei Shtylyov ` (4 subsequent siblings) 9 siblings, 2 replies; 23+ messages in thread From: Sergei Shtylyov @ 2016-10-28 22:19 UTC (permalink / raw) To: linux-arm-kernel Describe [H]SCIF{|A|B} ports in the R8A7745 device tree. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- arch/arm/boot/dts/r8a7745.dtsi | 261 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 261 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7745.dtsi =================================================================== --- renesas.orig/arch/arm/boot/dts/r8a7745.dtsi +++ renesas/arch/arm/boot/dts/r8a7745.dtsi @@ -157,6 +157,267 @@ #dma-cells = <1>; dma-channels = <15>; }; + + scifa0: serial at e6c40000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa1: serial at e6c50000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa2: serial at e6c60000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 0x40>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa3: serial at e6c70000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 0x40>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa4: serial at e6c78000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 0x40>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa5: serial at e6c80000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 0x40>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb0: serial at e6c20000 { + compatible = "renesas,scifb-r8a7745", + "renesas,rzg-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb1: serial at e6c30000 { + compatible = "renesas,scifb-r8a7745", + "renesas,rzg-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb2: serial at e6ce0000 { + compatible = "renesas,scifb-r8a7745", + "renesas,rzg-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif0: serial at e6e60000 { + compatible = "renesas,scif-r8a7745", "renesas,rzg-scif", + "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif1: serial at e6e68000 { + compatible = "renesas,scif-r8a7745", "renesas,rzg-scif", + "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif2: serial at e6e58000 { + compatible = "renesas,scif-r8a7745", "renesas,rzg-scif", + "renesas,scif"; + reg = <0 0xe6e58000 0 0x40>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 719>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif3: serial at e6ea8000 { + compatible = "renesas,scif-r8a7745", "renesas,rzg-scif", + "renesas,scif"; + reg = <0 0xe6ea8000 0 0x40>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 718>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif4: serial at e6ee0000 { + compatible = "renesas,scif-r8a7745", "renesas,rzg-scif", + "renesas,scif"; + reg = <0 0xe6ee0000 0 0x40>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 715>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif5: serial at e6ee8000 { + compatible = "renesas,scif-r8a7745", "renesas,rzg-scif", + "renesas,scif"; + reg = <0 0xe6ee8000 0 0x40>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 714>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif0: serial at e62c0000 { + compatible = "renesas,hscif-r8a7745", + "renesas,rzg-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif1: serial at e62c8000 { + compatible = "renesas,hscif-r8a7745", + "renesas,rzg-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 0x60>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif2: serial at e62d0000 { + compatible = "renesas,hscif-r8a7745", + "renesas,rzg-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 0x60>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 713>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; }; /* External root clock */ ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 06/11] ARM: dts: r8a7745: add [H]SCIF{A|B} support 2016-10-28 22:19 ` [PATCH 06/11] ARM: dts: r8a7745: add [H]SCIF{A|B} support Sergei Shtylyov @ 2016-11-02 10:12 ` Geert Uytterhoeven 2016-11-15 17:55 ` Simon Horman 1 sibling, 0 replies; 23+ messages in thread From: Geert Uytterhoeven @ 2016-11-02 10:12 UTC (permalink / raw) To: linux-arm-kernel On Sat, Oct 29, 2016 at 12:19 AM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Describe [H]SCIF{|A|B} ports in the R8A7745 device tree. > > Based on the original (and large) patch by Dmitry Shifrin > <dmitry.shifrin@cogentembedded.com>. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> After you've fixed the family-specific compatible values: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > arch/arm/boot/dts/r8a7745.dtsi | 261 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 261 insertions(+) > > Index: renesas/arch/arm/boot/dts/r8a7745.dtsi > =================================================================== > --- renesas.orig/arch/arm/boot/dts/r8a7745.dtsi > +++ renesas/arch/arm/boot/dts/r8a7745.dtsi > @@ -157,6 +157,267 @@ > #dma-cells = <1>; > dma-channels = <15>; > }; > + > + scifa0: serial at e6c40000 { > + compatible = "renesas,scifa-r8a7745", > + "renesas,rzg-scifa", "renesas,scifa"; s/renesas,rzg-/renesas,rcar-gen2-/g Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 06/11] ARM: dts: r8a7745: add [H]SCIF{A|B} support 2016-10-28 22:19 ` [PATCH 06/11] ARM: dts: r8a7745: add [H]SCIF{A|B} support Sergei Shtylyov 2016-11-02 10:12 ` Geert Uytterhoeven @ 2016-11-15 17:55 ` Simon Horman 1 sibling, 0 replies; 23+ messages in thread From: Simon Horman @ 2016-11-15 17:55 UTC (permalink / raw) To: linux-arm-kernel On Sat, Oct 29, 2016 at 01:19:40AM +0300, Sergei Shtylyov wrote: > Describe [H]SCIF{|A|B} ports in the R8A7745 device tree. > > Based on the original (and large) patch by Dmitry Shifrin > <dmitry.shifrin@cogentembedded.com>. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> I have queued this up after updating the indentation to use tabs where possible. ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 07/11] ARM: dts: r8a7745: add Ether support 2016-10-28 22:04 [PATCH 0/11] Add R8A7745/SK-RZG1E board support Sergei Shtylyov ` (4 preceding siblings ...) 2016-10-28 22:19 ` [PATCH 06/11] ARM: dts: r8a7745: add [H]SCIF{A|B} support Sergei Shtylyov @ 2016-10-28 22:21 ` Sergei Shtylyov 2016-11-02 10:14 ` Geert Uytterhoeven 2016-10-28 22:22 ` [PATCH 08/12] ARM: dts: r8a7745: add IRQC support Sergei Shtylyov ` (3 subsequent siblings) 9 siblings, 1 reply; 23+ messages in thread From: Sergei Shtylyov @ 2016-10-28 22:21 UTC (permalink / raw) To: linux-arm-kernel Define the generic R8A7745 part of the Ether device node. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- arch/arm/boot/dts/r8a7745.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7745.dtsi =================================================================== --- renesas.orig/arch/arm/boot/dts/r8a7745.dtsi +++ renesas/arch/arm/boot/dts/r8a7745.dtsi @@ -418,6 +418,18 @@ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; status = "disabled"; }; + + ether: ethernet at ee700000 { + compatible = "renesas,ether-r8a7745"; + reg = <0 0xee700000 0 0x400>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; /* External root clock */ ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 07/11] ARM: dts: r8a7745: add Ether support 2016-10-28 22:21 ` [PATCH 07/11] ARM: dts: r8a7745: add Ether support Sergei Shtylyov @ 2016-11-02 10:14 ` Geert Uytterhoeven 0 siblings, 0 replies; 23+ messages in thread From: Geert Uytterhoeven @ 2016-11-02 10:14 UTC (permalink / raw) To: linux-arm-kernel On Sat, Oct 29, 2016 at 12:21 AM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Define the generic R8A7745 part of the Ether device node. > > Based on the original (and large) patch by Dmitry Shifrin > <dmitry.shifrin@cogentembedded.com>. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 08/12] ARM: dts: r8a7745: add IRQC support 2016-10-28 22:04 [PATCH 0/11] Add R8A7745/SK-RZG1E board support Sergei Shtylyov ` (5 preceding siblings ...) 2016-10-28 22:21 ` [PATCH 07/11] ARM: dts: r8a7745: add Ether support Sergei Shtylyov @ 2016-10-28 22:22 ` Sergei Shtylyov 2016-11-02 10:20 ` Geert Uytterhoeven 2016-10-28 22:25 ` [PATCH 10/12] ARM: dts: sk-rzg1e: initial device tree Sergei Shtylyov ` (2 subsequent siblings) 9 siblings, 1 reply; 23+ messages in thread From: Sergei Shtylyov @ 2016-10-28 22:22 UTC (permalink / raw) To: linux-arm-kernel Describe the IRQC interrupt controller in the R8A7745 device tree. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- arch/arm/boot/dts/r8a7745.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7745.dtsi =================================================================== --- renesas.orig/arch/arm/boot/dts/r8a7745.dtsi +++ renesas/arch/arm/boot/dts/r8a7745.dtsi @@ -62,6 +62,25 @@ IRQ_TYPE_LEVEL_HIGH)>; }; + irqc: interrupt-controller at e61c0000 { + compatible = "renesas,irqc-r8a7745", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 08/12] ARM: dts: r8a7745: add IRQC support 2016-10-28 22:22 ` [PATCH 08/12] ARM: dts: r8a7745: add IRQC support Sergei Shtylyov @ 2016-11-02 10:20 ` Geert Uytterhoeven 0 siblings, 0 replies; 23+ messages in thread From: Geert Uytterhoeven @ 2016-11-02 10:20 UTC (permalink / raw) To: linux-arm-kernel On Sat, Oct 29, 2016 at 12:22 AM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Describe the IRQC interrupt controller in the R8A7745 device tree. > > Based on the original (and large) patch by Dmitry Shifrin > <dmitry.shifrin@cogentembedded.com>. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Subject is off-by-one (the series has only 11 patches) Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 10/12] ARM: dts: sk-rzg1e: initial device tree 2016-10-28 22:04 [PATCH 0/11] Add R8A7745/SK-RZG1E board support Sergei Shtylyov ` (6 preceding siblings ...) 2016-10-28 22:22 ` [PATCH 08/12] ARM: dts: r8a7745: add IRQC support Sergei Shtylyov @ 2016-10-28 22:25 ` Sergei Shtylyov 2016-10-28 22:28 ` Sergei Shtylyov 2016-10-28 22:29 ` Sergei Shtylyov 2016-10-28 22:31 ` [PATCH 11/12] ARM: dts: sk-rzg1e: add Ether support Sergei Shtylyov 9 siblings, 1 reply; 23+ messages in thread From: Sergei Shtylyov @ 2016-10-28 22:25 UTC (permalink / raw) To: linux-arm-kernel --- arch/arm/boot/dts/Makefile | 1 arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 39 +++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) Index: renesas/arch/arm/boot/dts/Makefile =================================================================== --- renesas.orig/arch/arm/boot/dts/Makefile +++ renesas/arch/arm/boot/dts/Makefile @@ -678,6 +678,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ r8a7743-sk-rzg1m.dtb \ + r8a7745-sk-rzg1e.dtb \ r8a7778-bockw.dtb \ r8a7779-marzen.dtb \ r8a7790-lager.dtb \ Index: renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts =================================================================== --- /dev/null +++ renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts @@ -0,0 +1,39 @@ +/* + * Device Tree Source for the SK-RZG1E board + * + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7745.dtsi" + +/ { + model = "SK-RZG1E"; + compatible = "renesas,sk-rzg1e", "renesas,r8a7745"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory at 40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&scif2 { + status = "okay"; +}; ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 10/12] ARM: dts: sk-rzg1e: initial device tree 2016-10-28 22:25 ` [PATCH 10/12] ARM: dts: sk-rzg1e: initial device tree Sergei Shtylyov @ 2016-10-28 22:28 ` Sergei Shtylyov 0 siblings, 0 replies; 23+ messages in thread From: Sergei Shtylyov @ 2016-10-28 22:28 UTC (permalink / raw) To: linux-arm-kernel On 10/29/2016 01:25 AM, Sergei Shtylyov wrote: > --- Oops, no description! :-/ I'll repost. MBR, Sergei ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 10/12] ARM: dts: sk-rzg1e: initial device tree 2016-10-28 22:04 [PATCH 0/11] Add R8A7745/SK-RZG1E board support Sergei Shtylyov ` (7 preceding siblings ...) 2016-10-28 22:25 ` [PATCH 10/12] ARM: dts: sk-rzg1e: initial device tree Sergei Shtylyov @ 2016-10-28 22:29 ` Sergei Shtylyov 2016-11-02 10:26 ` Geert Uytterhoeven 2016-10-28 22:31 ` [PATCH 11/12] ARM: dts: sk-rzg1e: add Ether support Sergei Shtylyov 9 siblings, 1 reply; 23+ messages in thread From: Sergei Shtylyov @ 2016-10-28 22:29 UTC (permalink / raw) To: linux-arm-kernel Add the initial device tree for the R8A7745 SoC based SK-RZG1E board. The board has 1 debug serial port (SCIF2); include support for it, so that the serial console can work. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- arch/arm/boot/dts/Makefile | 1 arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 39 +++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) Index: renesas/arch/arm/boot/dts/Makefile =================================================================== --- renesas.orig/arch/arm/boot/dts/Makefile +++ renesas/arch/arm/boot/dts/Makefile @@ -678,6 +678,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ r8a7743-sk-rzg1m.dtb \ + r8a7745-sk-rzg1e.dtb \ r8a7778-bockw.dtb \ r8a7779-marzen.dtb \ r8a7790-lager.dtb \ Index: renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts =================================================================== --- /dev/null +++ renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts @@ -0,0 +1,39 @@ +/* + * Device Tree Source for the SK-RZG1E board + * + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7745.dtsi" + +/ { + model = "SK-RZG1E"; + compatible = "renesas,sk-rzg1e", "renesas,r8a7745"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory at 40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&scif2 { + status = "okay"; +}; ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 10/12] ARM: dts: sk-rzg1e: initial device tree 2016-10-28 22:29 ` Sergei Shtylyov @ 2016-11-02 10:26 ` Geert Uytterhoeven 0 siblings, 0 replies; 23+ messages in thread From: Geert Uytterhoeven @ 2016-11-02 10:26 UTC (permalink / raw) To: linux-arm-kernel On Sat, Oct 29, 2016 at 12:29 AM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Add the initial device tree for the R8A7745 SoC based SK-RZG1E board. > The board has 1 debug serial port (SCIF2); include support for it, > so that the serial console can work. > > Based on the original (and large) patch by Dmitry Shifrin > <dmitry.shifrin@cogentembedded.com>. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Subject is off-by-one (the series has only 11 patches) Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 11/12] ARM: dts: sk-rzg1e: add Ether support 2016-10-28 22:04 [PATCH 0/11] Add R8A7745/SK-RZG1E board support Sergei Shtylyov ` (8 preceding siblings ...) 2016-10-28 22:29 ` Sergei Shtylyov @ 2016-10-28 22:31 ` Sergei Shtylyov 2016-11-02 10:26 ` Geert Uytterhoeven 9 siblings, 1 reply; 23+ messages in thread From: Sergei Shtylyov @ 2016-10-28 22:31 UTC (permalink / raw) To: linux-arm-kernel Define the SK-RZG1E board dependent part of the Ether device node. Enable DHCP and NFS root for the kernel booting. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) Index: renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts =================================================================== --- renesas.orig/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts +++ renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts @@ -20,7 +20,7 @@ }; chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; @@ -37,3 +37,16 @@ &scif2 { status = "okay"; }; + +ðer { + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy at 1 { + reg = <1>; + interrupt-parent = <&irqc>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +}; ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 11/12] ARM: dts: sk-rzg1e: add Ether support 2016-10-28 22:31 ` [PATCH 11/12] ARM: dts: sk-rzg1e: add Ether support Sergei Shtylyov @ 2016-11-02 10:26 ` Geert Uytterhoeven 0 siblings, 0 replies; 23+ messages in thread From: Geert Uytterhoeven @ 2016-11-02 10:26 UTC (permalink / raw) To: linux-arm-kernel On Sat, Oct 29, 2016 at 12:31 AM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Define the SK-RZG1E board dependent part of the Ether device node. > Enable DHCP and NFS root for the kernel booting. > > Based on the original (and large) patch by Dmitry Shifrin > <dmitry.shifrin@cogentembedded.com>. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Subject is off-by-one (the series has only 11 patches) Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2016-11-15 17:55 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz follow: Atom feed
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2016-10-28 22:04 [PATCH 0/11] Add R8A7745/SK-RZG1E board support Sergei Shtylyov
2016-10-28 22:07 ` [PATCH 01/11] ARM: shmobile: r8a7745: add power domain index macros Sergei Shtylyov
2016-11-02 9:46 ` Geert Uytterhoeven
2016-10-28 22:16 ` [PATCH 03/11] ARM: shmobile: r8a7745: basic SoC support Sergei Shtylyov
2016-10-31 6:22 ` Rob Herring
2016-11-02 9:49 ` Geert Uytterhoeven
2016-10-28 22:17 ` [PATCH 04/11] ARM: dts: r8a7745: initial SoC device tree Sergei Shtylyov
2016-11-02 10:03 ` Geert Uytterhoeven
2016-10-28 22:18 ` [PATCH 05/11] ARM: dts: r8a7745: add SYS-DMAC support Sergei Shtylyov
2016-11-02 10:08 ` Geert Uytterhoeven
2016-10-28 22:19 ` [PATCH 06/11] ARM: dts: r8a7745: add [H]SCIF{A|B} support Sergei Shtylyov
2016-11-02 10:12 ` Geert Uytterhoeven
2016-11-15 17:55 ` Simon Horman
2016-10-28 22:21 ` [PATCH 07/11] ARM: dts: r8a7745: add Ether support Sergei Shtylyov
2016-11-02 10:14 ` Geert Uytterhoeven
2016-10-28 22:22 ` [PATCH 08/12] ARM: dts: r8a7745: add IRQC support Sergei Shtylyov
2016-11-02 10:20 ` Geert Uytterhoeven
2016-10-28 22:25 ` [PATCH 10/12] ARM: dts: sk-rzg1e: initial device tree Sergei Shtylyov
2016-10-28 22:28 ` Sergei Shtylyov
2016-10-28 22:29 ` Sergei Shtylyov
2016-11-02 10:26 ` Geert Uytterhoeven
2016-10-28 22:31 ` [PATCH 11/12] ARM: dts: sk-rzg1e: add Ether support Sergei Shtylyov
2016-11-02 10:26 ` Geert Uytterhoeven
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