* GIC_CPU_MASK_SIMPLE(8)" on big.LITTLE?
@ 2015-01-05 10:37 Geert Uytterhoeven
2015-01-12 14:45 ` Liviu Dudau
0 siblings, 1 reply; 3+ messages in thread
From: Geert Uytterhoeven @ 2015-01-05 10:37 UTC (permalink / raw)
To: linux-arm-kernel
A while ago, I wondered:
| It's my understanding GIC_CPU_MASK_SIMPLE should reflect the actual number
| of CPU cores the interrupt is wired too. Is that correct?
|
| [Fixes for incorrect masks on shmobile]
|
| Should it be "GIC_CPU_MASK_SIMPLE(8)" on big.LITTLE configurations
| with four Cortex-A15 cores and four Cortex-A7 cores?
| Or should the interrupts be delivered to the four Cortex-A15 cores
| only by default?
|
| Note that incorrect masks for GIC PPI interrupts are not limited to
| shmobile. Presumably the interrupt specifiers got copied around a lot,
| cfr. the proliferation of "GIC_CPU_MASK_SIMPLE(4)" (and the older
| hardcoded "0xf0x" variant) in various dtsi files, not always limited to
| quad-core CPUs.
In the mean time, arch/arm64/boot/dts/arm/juno.dts got added, which has 2 A57
cores and 4 A53 cores, and uses GIC_CPU_MASK_SIMPLE(6), so it seems like
my two RFC patches to use GIC_CPU_MASK_SIMPLE(8) for 4 A15 cores and 4
A7 cores are actually correct?
Thanks for your comments!
References:
1. Original RFC series:
[PATCH/RFC 0/4] ARM: shmobile: Correct masks for GIC PPI interrupts
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/306743.html
2. RFC patches:
a. [PATCH/RFC 3/4] ARM: shmobile: r8a7790: Correct mask for GIC
PPI interrupts
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/306741.html
b. [PATCH/RFC 4/4] ARM: shmobile: r8a73a4: Correct mask for GIC
PPI interrupts
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/306740.html
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 3+ messages in thread
* GIC_CPU_MASK_SIMPLE(8)" on big.LITTLE?
2015-01-05 10:37 GIC_CPU_MASK_SIMPLE(8)" on big.LITTLE? Geert Uytterhoeven
@ 2015-01-12 14:45 ` Liviu Dudau
2015-01-12 15:33 ` Geert Uytterhoeven
0 siblings, 1 reply; 3+ messages in thread
From: Liviu Dudau @ 2015-01-12 14:45 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jan 05, 2015 at 10:37:47AM +0000, Geert Uytterhoeven wrote:
> A while ago, I wondered:
>
> | It's my understanding GIC_CPU_MASK_SIMPLE should reflect the actual number
> | of CPU cores the interrupt is wired too. Is that correct?
> |
> | [Fixes for incorrect masks on shmobile]
> |
> | Should it be "GIC_CPU_MASK_SIMPLE(8)" on big.LITTLE configurations
> | with four Cortex-A15 cores and four Cortex-A7 cores?
> | Or should the interrupts be delivered to the four Cortex-A15 cores
> | only by default?
> |
> | Note that incorrect masks for GIC PPI interrupts are not limited to
> | shmobile. Presumably the interrupt specifiers got copied around a lot,
> | cfr. the proliferation of "GIC_CPU_MASK_SIMPLE(4)" (and the older
> | hardcoded "0xf0x" variant) in various dtsi files, not always limited to
> | quad-core CPUs.
>
> In the mean time, arch/arm64/boot/dts/arm/juno.dts got added, which has 2 A57
> cores and 4 A53 cores, and uses GIC_CPU_MASK_SIMPLE(6), so it seems like
> my two RFC patches to use GIC_CPU_MASK_SIMPLE(8) for 4 A15 cores and 4
> A7 cores are actually correct?
>
> Thanks for your comments!
>
> References:
> 1. Original RFC series:
> [PATCH/RFC 0/4] ARM: shmobile: Correct masks for GIC PPI interrupts
> http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/306743.html
> 2. RFC patches:
> a. [PATCH/RFC 3/4] ARM: shmobile: r8a7790: Correct mask for GIC
> PPI interrupts
> http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/306741.html
> b. [PATCH/RFC 4/4] ARM: shmobile: r8a73a4: Correct mask for GIC
> PPI interrupts
> http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/306740.html
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
>
Hi Geert,
Sorry for delay in responding, I'm just coming back online.
Your patches are correct, the mask should reflect the number of CPUs present *and* they way
they are wired in the GIC. AFAIK, HW designers have been sane so far and wired the CPUs
in sequence in the GIC, but I lack inside knowledge of the shmobile design.
Best regards,
Liviu
--
====================
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
?\_(?)_/?
^ permalink raw reply [flat|nested] 3+ messages in thread
* GIC_CPU_MASK_SIMPLE(8)" on big.LITTLE?
2015-01-12 14:45 ` Liviu Dudau
@ 2015-01-12 15:33 ` Geert Uytterhoeven
0 siblings, 0 replies; 3+ messages in thread
From: Geert Uytterhoeven @ 2015-01-12 15:33 UTC (permalink / raw)
To: linux-arm-kernel
Hi Liviu,
On Mon, Jan 12, 2015 at 3:45 PM, Liviu Dudau <Liviu.Dudau@arm.com> wrote:
> On Mon, Jan 05, 2015 at 10:37:47AM +0000, Geert Uytterhoeven wrote:
>> A while ago, I wondered:
>>
>> | It's my understanding GIC_CPU_MASK_SIMPLE should reflect the actual number
>> | of CPU cores the interrupt is wired too. Is that correct?
>> |
>> | [Fixes for incorrect masks on shmobile]
>> |
>> | Should it be "GIC_CPU_MASK_SIMPLE(8)" on big.LITTLE configurations
>> | with four Cortex-A15 cores and four Cortex-A7 cores?
>> | Or should the interrupts be delivered to the four Cortex-A15 cores
>> | only by default?
>> |
>> | Note that incorrect masks for GIC PPI interrupts are not limited to
>> | shmobile. Presumably the interrupt specifiers got copied around a lot,
>> | cfr. the proliferation of "GIC_CPU_MASK_SIMPLE(4)" (and the older
>> | hardcoded "0xf0x" variant) in various dtsi files, not always limited to
>> | quad-core CPUs.
>>
>> In the mean time, arch/arm64/boot/dts/arm/juno.dts got added, which has 2 A57
>> cores and 4 A53 cores, and uses GIC_CPU_MASK_SIMPLE(6), so it seems like
>> my two RFC patches to use GIC_CPU_MASK_SIMPLE(8) for 4 A15 cores and 4
>> A7 cores are actually correct?
>>
>> Thanks for your comments!
>>
>> References:
>> 1. Original RFC series:
>> [PATCH/RFC 0/4] ARM: shmobile: Correct masks for GIC PPI interrupts
>> http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/306743.html
>> 2. RFC patches:
>> a. [PATCH/RFC 3/4] ARM: shmobile: r8a7790: Correct mask for GIC
>> PPI interrupts
>> http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/306741.html
>> b. [PATCH/RFC 4/4] ARM: shmobile: r8a73a4: Correct mask for GIC
>> PPI interrupts
>> http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/306740.html
> Your patches are correct, the mask should reflect the number of CPUs present *and* they way
> they are wired in the GIC. AFAIK, HW designers have been sane so far and wired the CPUs
> in sequence in the GIC, but I lack inside knowledge of the shmobile design.
Thanks, I will resend them.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 3+ messages in thread
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