* [PATCH v3 1/3] arm64: dts: renesas: r8a7795: move scif node into alphabetical order
2018-01-03 12:41 [PATCH v3 0/3] arm64: dts: r8a779[56]: Add OPPs table for cpu devices Simon Horman
@ 2018-01-03 12:41 ` Simon Horman
2018-01-03 14:02 ` Geert Uytterhoeven
2018-01-03 12:41 ` [PATCH v3 2/3] arm64: dts: renesas: r8a7795: Add OPPs table for cpu devices Simon Horman
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Simon Horman @ 2018-01-03 12:41 UTC (permalink / raw)
To: linux-arm-kernel
Move scif node so that sub-nodes of the root node are in
alphabetical order.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index d12df6f2ff09..24e9209ea54e 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -165,13 +165,6 @@
clock-frequency = <0>;
};
- /* External SCIF clock - to be overridden by boards that provide it */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
@@ -208,6 +201,13 @@
method = "smc";
};
+ /* External SCIF clock - to be overridden by boards that provide it */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
--
2.11.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v3 2/3] arm64: dts: renesas: r8a7795: Add OPPs table for cpu devices
2018-01-03 12:41 [PATCH v3 0/3] arm64: dts: r8a779[56]: Add OPPs table for cpu devices Simon Horman
2018-01-03 12:41 ` [PATCH v3 1/3] arm64: dts: renesas: r8a7795: move scif node into alphabetical order Simon Horman
@ 2018-01-03 12:41 ` Simon Horman
2018-01-03 14:06 ` Geert Uytterhoeven
2018-01-03 12:41 ` [PATCH v3 3/3] arm64: dts: renesas: r8a7796: " Simon Horman
2018-01-03 17:38 ` [PATCH v3 0/3] arm64: dts: r8a779[56]: " Niklas Söderlund
3 siblings, 1 reply; 9+ messages in thread
From: Simon Horman @ 2018-01-03 12:41 UTC (permalink / raw)
To: linux-arm-kernel
From: Dien Pham <dien.pham.ry@rvc.renesas.com>
Define OOP tables for all CPUs.
This allows CPUFreq to function.
Based in part on work by Hien Dang.
Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
v3 [Simon Horman]
- Preserve alphabetical order of sub-nodes of root node
- Do not provide unit name for opps, they have no base address
- Describe clock dependency for all CPU cores
v2 [Simon Horman]
- Only provide one operating points node for each operating-points-v2 node
as per the binding; other nodes were unused and have been removed
v1 [Simon Horman]
- consolidated several patches into one
v0 [Dien Pham]
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 61 ++++++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 24e9209ea54e..1485e6a8e112 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -41,6 +41,8 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
};
a57_1: cpu at 1 {
@@ -50,6 +52,8 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
};
a57_2: cpu at 2 {
@@ -59,6 +63,8 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
};
a57_3: cpu at 3 {
@@ -68,6 +74,8 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
};
a53_0: cpu at 100 {
@@ -77,6 +85,8 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
a53_1: cpu at 101 {
@@ -86,6 +96,8 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
a53_2: cpu at 102 {
@@ -95,6 +107,8 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
a53_3: cpu at 103 {
@@ -104,6 +118,8 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
L2_CA57: cache-controller-0 {
@@ -165,6 +181,51 @@
clock-frequency = <0>;
};
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <830000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <830000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <830000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <960000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ };
+
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
--
2.11.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v3 2/3] arm64: dts: renesas: r8a7795: Add OPPs table for cpu devices
2018-01-03 12:41 ` [PATCH v3 2/3] arm64: dts: renesas: r8a7795: Add OPPs table for cpu devices Simon Horman
@ 2018-01-03 14:06 ` Geert Uytterhoeven
0 siblings, 0 replies; 9+ messages in thread
From: Geert Uytterhoeven @ 2018-01-03 14:06 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jan 3, 2018 at 1:41 PM, Simon Horman <horms+renesas@verge.net.au> wrote:
> From: Dien Pham <dien.pham.ry@rvc.renesas.com>
>
> Define OOP tables for all CPUs.
> This allows CPUFreq to function.
>
> Based in part on work by Hien Dang.
>
> Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Looks good and matches the bindings.
I cannot verify the operating point tuples, though.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 3/3] arm64: dts: renesas: r8a7796: Add OPPs table for cpu devices
2018-01-03 12:41 [PATCH v3 0/3] arm64: dts: r8a779[56]: Add OPPs table for cpu devices Simon Horman
2018-01-03 12:41 ` [PATCH v3 1/3] arm64: dts: renesas: r8a7795: move scif node into alphabetical order Simon Horman
2018-01-03 12:41 ` [PATCH v3 2/3] arm64: dts: renesas: r8a7795: Add OPPs table for cpu devices Simon Horman
@ 2018-01-03 12:41 ` Simon Horman
2018-01-03 14:07 ` Geert Uytterhoeven
2018-01-03 17:38 ` [PATCH v3 0/3] arm64: dts: r8a779[56]: " Niklas Söderlund
3 siblings, 1 reply; 9+ messages in thread
From: Simon Horman @ 2018-01-03 12:41 UTC (permalink / raw)
To: linux-arm-kernel
From: Dien Pham <dien.pham.ry@rvc.renesas.com>
Define OOP tables for all CPUs.
This allows CPUFreq to function.
Based in part on work by Hien Dang.
Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
v3 [Simon Horman]
* Do not give nodes a unit name, they have no base address
* Preserve alphabetical order of sub-nodes of root node
* Describe clock dependency for all CPU cores
v2 [Simon Horman]
- Only provide one operating points node for each operating-points-v2 node
as per the binding; other nodes were unused and have been removed
v1 [Simon Horman]
- consolidated several patches into one
v0 [Dien Pham]
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 62 ++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index c5192d513d7d..e06bde6e2853 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -71,6 +71,8 @@
power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
};
a57_1: cpu at 1 {
@@ -80,6 +82,8 @@
power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
};
a53_0: cpu at 100 {
@@ -89,6 +93,8 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
a53_1: cpu at 101 {
@@ -98,6 +104,8 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
a53_2: cpu at 102 {
@@ -107,6 +115,8 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
a53_3: cpu at 103 {
@@ -116,6 +126,8 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
L2_CA57: cache-controller-0 {
@@ -147,6 +159,56 @@
clock-frequency = <0>;
};
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <960000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ };
+
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
--
2.11.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v3 3/3] arm64: dts: renesas: r8a7796: Add OPPs table for cpu devices
2018-01-03 12:41 ` [PATCH v3 3/3] arm64: dts: renesas: r8a7796: " Simon Horman
@ 2018-01-03 14:07 ` Geert Uytterhoeven
0 siblings, 0 replies; 9+ messages in thread
From: Geert Uytterhoeven @ 2018-01-03 14:07 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jan 3, 2018 at 1:41 PM, Simon Horman <horms+renesas@verge.net.au> wrote:
> From: Dien Pham <dien.pham.ry@rvc.renesas.com>
>
> Define OOP tables for all CPUs.
> This allows CPUFreq to function.
>
> Based in part on work by Hien Dang.
>
> Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Looks good and matches the bindings.
I cannot verify the operating point tuples, though.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 0/3] arm64: dts: r8a779[56]: Add OPPs table for cpu devices
2018-01-03 12:41 [PATCH v3 0/3] arm64: dts: r8a779[56]: Add OPPs table for cpu devices Simon Horman
` (2 preceding siblings ...)
2018-01-03 12:41 ` [PATCH v3 3/3] arm64: dts: renesas: r8a7796: " Simon Horman
@ 2018-01-03 17:38 ` Niklas Söderlund
2018-01-04 16:49 ` Simon Horman
3 siblings, 1 reply; 9+ messages in thread
From: Niklas Söderlund @ 2018-01-03 17:38 UTC (permalink / raw)
To: linux-arm-kernel
Hi Simon,
Thanks for your work.
I tested these patches together with the dependencies of the
topic/rcar-gen3-cpufreq-v4 branch, feel free to add to all patches in
this series.
Tested-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
On 2018-01-03 13:41:02 +0100, Simon Horman wrote:
> These are dependencies for supporting CPUFreq. The remainder of that
> work is being posted separately and can be found at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git topic/rcar-gen3-cpufreq-v4
>
>
> Patch 1: Cleanup of DTS, only related as its an apply-time conflict
> Patches 2 & 3: Add OPPs
>
> Changes since v2:
> * Preserve alphabetical order of sub-nodes of root node
> * Do not provide unit name for opps, they have no base address
> * Describe clock dependency for all CPU cores
>
> Changes since v1:
> * Only provide one operating points node for each operating-points-v2 node
> as per the binding; other nodes were unused and have been removed
>
> A description of steps taken to lightly exercise the same feature for the
> r8a7795 the above can be found at the link below. The results are the same
> for the r8a7796 with the exception that it has two active CPU cores rather
> than four.
>
> http://elinux.org/Tests:R-CAR-GEN3-CPUFreq
>
>
> Dien Pham (2):
> arm64: dts: renesas: r8a7795: Add OPPs table for cpu devices
> arm64: dts: renesas: r8a7796: Add OPPs table for cpu devices
>
> Simon Horman (1):
> arm64: dts: renesas: r8a7795: move scif node into alphabetical order
>
> arch/arm64/boot/dts/renesas/r8a7795.dtsi | 71 +++++++++++++++++++++++++++++---
> arch/arm64/boot/dts/renesas/r8a7796.dtsi | 62 ++++++++++++++++++++++++++++
> 2 files changed, 128 insertions(+), 5 deletions(-)
>
> --
> 2.11.0
>
--
Regards,
Niklas S?derlund
^ permalink raw reply [flat|nested] 9+ messages in thread