[PATCH v2 4/4] ARM: pxa168/gplugd: Add support for SD port 1

[PATCH v2 4/4] ARM: pxa168/gplugd: Add support for SD port 1

[Tanmay Upadhyay]

v2 - after sdhci-pxav1 driver is merged with sdhci-pxav2, pass
     pxav1_controller = 1
   - as sdhci device numbering now starts from 1, call
     pxa168_add_sdh accordingly

Signed-off-by: Tanmay Upadhyay <tanmay.upadhyay@einfochips.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
---
 arch/arm/mach-mmp/gplugd.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c
index 6915656..d7947e7 100644
--- a/arch/arm/mach-mmp/gplugd.c
+++ b/arch/arm/mach-mmp/gplugd.c
@@ -154,6 +154,11 @@ struct pxa168_eth_platform_data gplugd_eth_platform_data = {
 	.init        = gplugd_eth_init,
 };
 
+struct sdhci_pxa_platdata gplugd_sdh_platdata = {
+	.delay_in_ms = 5,
+	.pxav1_controller = 1,
+};
+
 static void __init select_disp_freq(void)
 {
 	/* set GPIO 35 & clear GPIO 85 to set LCD External Clock to 74.25 MHz */
@@ -186,6 +191,7 @@ static void __init gplugd_init(void)
 	pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(gplugd_i2c_board_info));
 
 	pxa168_add_eth(&gplugd_eth_platform_data);
+	pxa168_add_sdh(1, &gplugd_sdh_platdata);
 }
 
 MACHINE_START(GPLUGD, "PXA168-based GuruPlug Display (gplugD) Platform")
-- 
1.7.0.4

[PATCH 0/4] Add SD support for PXA168 & gplugD

[Tanmay Upadhyay]

This patch series adds support for on-chip SD controller on PXA168

Tanmay Upadhyay (4):
  mmc: sdhci-pxa: Trivial fix in Kconfig
  ARM: pxa168: Add SDHCI support
  mmc: sdhci-pxa: Add SDHCI driver for PXA16x
  ARM: pxa168/gplugd: Add support for SD port 1

 arch/arm/mach-mmp/Kconfig               |    1 -
 arch/arm/mach-mmp/clock-pxa168.c        |   47 +++++++++++++++++++++++++++++++
 arch/arm/mach-mmp/gplugd.c              |    6 ++++
 arch/arm/mach-mmp/include/mach/pxa168.h |   20 +++++++++++++
 arch/arm/mach-mmp/pxa168.c              |    4 +++
 drivers/mmc/host/Kconfig                |   11 ++++----
 drivers/mmc/host/sdhci-pxav2.c          |   30 +++++++++++++++++++-
 drivers/mmc/host/sdhci.c                |    3 ++
 drivers/mmc/host/sdhci.h                |    1 +
 include/linux/platform_data/pxa_sdhci.h |    2 ++
 10 files changed, 118 insertions(+), 7 deletions(-)

-- 
1.7.9.5

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[PATCH 1/4] mmc: sdhci-pxa: Trivial fix in Kconfig

[Tanmay Upadhyay]

Select MMC_SDHCI_PXAV3 by default if CPU is MMP2
Select MMC_SDHCI_PXAV2 by default if CPU is PXA910

Signed-off-by: Tanmay Upadhyay <tanmay.upadhyay@einfochips.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
---
 drivers/mmc/host/Kconfig |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 8d13c65..e5faed8 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -198,7 +198,7 @@ config MMC_SDHCI_PXAV3
 	depends on CLKDEV_LOOKUP
 	select MMC_SDHCI
 	select MMC_SDHCI_PLTFM
-	default CPU_MMP2
+	default y if CPU_MMP2
 	help
 	  This selects the Marvell(R) PXAV3 SD Host Controller.
 	  If you have a MMP2 platform with SD Host Controller
@@ -211,7 +211,7 @@ config MMC_SDHCI_PXAV2
 	depends on CLKDEV_LOOKUP
 	select MMC_SDHCI
 	select MMC_SDHCI_PLTFM
-	default CPU_PXA910
+	default y if CPU_PXA910
 	help
 	  This selects the Marvell(R) PXAV2 SD Host Controller.
 	  If you have a PXA9XX platform with SD Host Controller
-- 
1.7.9.5

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*************************************************************************************************************************************************************


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[PATCH v6 2/4] ARM: pxa168: Add SDHCI support

[Tanmay Upadhyay]

v2 - clock register for SDHCI are not common across all MMP SoCs.
     So, move PXA168 implementation to pxa168.c

v3 - sdhci-pxav1 driver code is merged with sdhci-pxav2. So, change
     the device name accordingly
   - start sdhci device numbering from 1 as other PXA168 devices
     does that

v4 - Use different names for SD clock registers for PXA168 instead
     of redefining them in pxa168.c. Suggested by Haojian Zhuang

v5 - Have two different clock enable functions for clock block 1 & 2
     & don't change indentation in regs-apmu.h as suggested by Haojian
     Zhuang
   - Use device name while adding clock as suggested by Russell King

v6 - Rebase for Linux v3.8; de-select COMMON_CLK for PXA168 as its
     SDHCI clocks should be handled differently than others
---
 arch/arm/mach-mmp/Kconfig               |    1 -
 arch/arm/mach-mmp/clock-pxa168.c        |   47 +++++++++++++++++++++++++++++++
 arch/arm/mach-mmp/include/mach/pxa168.h |   20 +++++++++++++
 arch/arm/mach-mmp/pxa168.c              |    4 +++
 4 files changed, 71 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index ebdda83..530245c 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -111,7 +111,6 @@ endmenu
 
 config CPU_PXA168
 	bool
-	select COMMON_CLK
 	select CPU_MOHAWK
 	help
 	  Select code specific to PXA168
diff --git a/arch/arm/mach-mmp/clock-pxa168.c b/arch/arm/mach-mmp/clock-pxa168.c
index 5e6c18c..65ea00e 100644
--- a/arch/arm/mach-mmp/clock-pxa168.c
+++ b/arch/arm/mach-mmp/clock-pxa168.c
@@ -31,11 +31,49 @@
 #define APBC_SSP4	APBC_REG(0x858)
 #define APBC_SSP5	APBC_REG(0x85c)
 
+#define APMU_SDH0	APMU_REG(0x054)
+#define APMU_SDH1	APMU_REG(0x058)
 #define APMU_NAND	APMU_REG(0x060)
 #define APMU_LCD	APMU_REG(0x04c)
+#define APMU_SDH2	APMU_REG(0x0e0)
+#define APMU_SDH3	APMU_REG(0x0e4)
 #define APMU_ETH	APMU_REG(0x0fc)
 #define APMU_USB	APMU_REG(0x05c)
 
+static void sdh1_clk_enable(struct clk *clk)
+{
+	/* Bits 3 & 0 in registers for host 0 should be set for host 1 also */
+	__raw_writel(__raw_readl(APMU_SDH0) | 0x9, APMU_SDH0);
+
+	__raw_writel(__raw_readl(clk->clk_rst) | clk->enable_val, clk->clk_rst);
+}
+
+static void sdh2_clk_enable(struct clk *clk)
+{
+	/* Bits 3 & 0 in registers for host 2 should be set for host 3 also */
+	__raw_writel(__raw_readl(APMU_SDH2) | 0x9, APMU_SDH2);
+
+	__raw_writel(__raw_readl(clk->clk_rst) | clk->enable_val, clk->clk_rst);
+}
+
+static void sdh_clk_disable(struct clk *clk)
+{
+	__raw_writel(__raw_readl(clk->clk_rst) & ~clk->enable_val,
+			clk->clk_rst);
+}
+
+/* Block 1 for controller 0 & 1 */
+struct clkops sdh1_clk_ops = {
+	.enable		= sdh1_clk_enable,
+	.disable	= sdh_clk_disable,
+};
+
+/* Block 2 for controller 2 & 3 */
+struct clkops sdh2_clk_ops = {
+	.enable		= sdh2_clk_enable,
+	.disable	= sdh_clk_disable,
+};
+
 /* APB peripheral clocks */
 static APBC_CLK(uart1, UART1, 1, 14745600);
 static APBC_CLK(uart2, UART2, 1, 14745600);
@@ -60,6 +98,11 @@ static APMU_CLK(lcd, LCD, 0x7f, 312000000);
 static APMU_CLK(eth, ETH, 0x09, 0);
 static APMU_CLK(usb, USB, 0x12, 0);
 
+static APMU_CLK_OPS(sdh1, SDH0, 0x12, 48000000, &sdh1_clk_ops);
+static APMU_CLK_OPS(sdh2, SDH1, 0x12, 48000000, &sdh1_clk_ops);
+static APMU_CLK_OPS(sdh3, SDH2, 0x12, 48000000, &sdh2_clk_ops);
+static APMU_CLK_OPS(sdh4, SDH3, 0x12, 48000000, &sdh2_clk_ops);
+
 /* device and clock bindings */
 static struct clk_lookup pxa168_clkregs[] = {
 	INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
@@ -83,6 +126,10 @@ static struct clk_lookup pxa168_clkregs[] = {
 	INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
 	INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
 	INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
+	INIT_CLKREG(&clk_sdh1, "sdhci-pxav2.0", "PXA-SDHCLK"),
+	INIT_CLKREG(&clk_sdh2, "sdhci-pxav2.1", "PXA-SDHCLK"),
+	INIT_CLKREG(&clk_sdh3, "sdhci-pxav2.2", "PXA-SDHCLK"),
+	INIT_CLKREG(&clk_sdh4, "sdhci-pxav2.3", "PXA-SDHCLK"),
 };
 
 void __init pxa168_clk_init(void)
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 37632d9..805117e 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -17,6 +17,7 @@ extern void pxa168_clear_keypad_wakeup(void);
 #include <mach/cputype.h>
 #include <linux/pxa168_eth.h>
 #include <linux/platform_data/mv_usb.h>
+#include <linux/platform_data/pxa_sdhci.h>
 
 extern struct pxa_device_desc pxa168_device_uart1;
 extern struct pxa_device_desc pxa168_device_uart2;
@@ -36,6 +37,10 @@ extern struct pxa_device_desc pxa168_device_nand;
 extern struct pxa_device_desc pxa168_device_fb;
 extern struct pxa_device_desc pxa168_device_keypad;
 extern struct pxa_device_desc pxa168_device_eth;
+extern struct pxa_device_desc pxa168_device_sdh1;
+extern struct pxa_device_desc pxa168_device_sdh2;
+extern struct pxa_device_desc pxa168_device_sdh3;
+extern struct pxa_device_desc pxa168_device_sdh4;
 
 /* pdata can be NULL */
 extern int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata);
@@ -133,4 +138,19 @@ static inline int pxa168_add_eth(struct pxa168_eth_platform_data *data)
 {
 	return pxa_register_device(&pxa168_device_eth, data, sizeof(*data));
 }
+
+static inline int pxa168_add_sdh(int id, struct sdhci_pxa_platdata *data)
+{
+	struct pxa_device_desc *d = NULL;
+
+	switch (id) {
+	case 1: d = &pxa168_device_sdh1; break;
+	case 2: d = &pxa168_device_sdh2; break;
+	case 3: d = &pxa168_device_sdh3; break;
+	case 4: d = &pxa168_device_sdh4; break;
+	default:
+		return -EINVAL;
+	}
+	return pxa_register_device(d, data, sizeof(*data));
+}
 #endif /* __ASM_MACH_PXA168_H */
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index b7f074f..ab5f273 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -114,6 +114,10 @@ PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61);
 PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8);
 PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c);
 PXA168_DEVICE(eth, "pxa168-eth", -1, MFU, 0xc0800000, 0x0fff);
+PXA168_DEVICE(sdh1, "sdhci-pxav2", 0, SDH1, 0xd4280000, 0x100);
+PXA168_DEVICE(sdh2, "sdhci-pxav2", 1, SDH1, 0xd4281000, 0x100);
+PXA168_DEVICE(sdh3, "sdhci-pxav2", 2, SDH2, 0xd427e000, 0x100);
+PXA168_DEVICE(sdh4, "sdhci-pxav2", 3, SDH2, 0xd427f000, 0x100);
 
 struct resource pxa168_resource_gpio[] = {
 	{
-- 
1.7.9.5

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[PATCH v2 3/4] mmc: sdhci-pxa: Add SDHCI driver for PXA16x

[Tanmay Upadhyay]

PXA16x devices uses SDHCI controller v1. As it's not much different
than v2 controller, v1 driver is merged with sdhci-pxav2 driver

v2 - instead of having separate file sdhci-pxav1, merge code with
     sdhci-pxav2 driver code as suggested by Chris Ball

Signed-off-by: Philip Rakity <prakity@marvell.com>
Signed-off-by: Tanmay Upadhyay <tanmay.upadhyay@einfochips.com>
---
 drivers/mmc/host/Kconfig                |    7 ++++---
 drivers/mmc/host/sdhci-pxav2.c          |   30 +++++++++++++++++++++++++++++-
 drivers/mmc/host/sdhci.c                |    3 +++
 drivers/mmc/host/sdhci.h                |    1 +
 include/linux/platform_data/pxa_sdhci.h |    2 ++
 5 files changed, 39 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index e5faed8..875e2475 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -207,14 +207,15 @@ config MMC_SDHCI_PXAV3
 	  If unsure, say N.
 
 config MMC_SDHCI_PXAV2
-	tristate "Marvell PXA9XX SD Host Controller support (PXAV2)"
+	tristate "Marvell PXA16X/PXA9XX SD Host Controller support (PXAV1/V2)"
 	depends on CLKDEV_LOOKUP
 	select MMC_SDHCI
 	select MMC_SDHCI_PLTFM
 	default y if CPU_PXA910
+	default y if CPU_PXA168
 	help
-	  This selects the Marvell(R) PXAV2 SD Host Controller.
-	  If you have a PXA9XX platform with SD Host Controller
+	  This selects the Marvell(R) PXAV1/V2 SD Host Controller.
+	  If you have a PXA16X or PXA9XX platform with SD Host Controller
 	  and a card slot, say Y or M here.
 
 	  If unsure, say N.
diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c
index ac854aa..5af7d46 100644
--- a/drivers/mmc/host/sdhci-pxav2.c
+++ b/drivers/mmc/host/sdhci-pxav2.c
@@ -30,6 +30,7 @@
 #include <linux/slab.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <linux/delay.h>
 
 #include "sdhci.h"
 #include "sdhci-pltfm.h"
@@ -75,7 +76,13 @@ static void pxav2_set_private_registers(struct sdhci_host *host, u8 mask)
 			writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
 		}
 
-		if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) {
+		if (pdata && pdata->pxav1_controller) {
+			/* no clock gating */
+			tmp = readw(host->ioaddr + SD_FIFO_PARAM);
+			tmp |= DIS_PAD_SD_CLK_GATE;
+			writew(tmp, host->ioaddr + SD_FIFO_PARAM);
+		} else if (pdata && (pdata->flags
+				& PXA_FLAG_ENABLE_CLOCK_GATING)) {
 			tmp = readw(host->ioaddr + SD_FIFO_PARAM);
 			tmp &= ~CLK_GATE_SETTING_BITS;
 			writew(tmp, host->ioaddr + SD_FIFO_PARAM);
@@ -118,6 +125,20 @@ static u32 pxav2_get_max_clock(struct sdhci_host *host)
 	return clk_get_rate(pltfm_host->clk);
 }
 
+/*
+ * we cannot talk to controller for 8 bus cycles according to sdio spec
+ * at lowest speed this is 100,000 HZ per cycle or 800,000 cycles
+ * which is quite a LONG TIME on a fast cpu -- so delay if needed
+ */
+static void platform_specific_completion(struct sdhci_host *host)
+{
+	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
+	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
+
+	if (host->clock < 3200000 && pdata && pdata->delay_in_ms)
+		mdelay(pdata->delay_in_ms);
+}
+
 static struct sdhci_ops pxav2_sdhci_ops = {
 	.get_max_clock = pxav2_get_max_clock,
 	.platform_reset_exit = pxav2_set_private_registers,
@@ -218,6 +239,13 @@ static int sdhci_pxav2_probe(struct platform_device *pdev)
 		if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
 			host->mmc->caps |= MMC_CAP_8_BIT_DATA;
 
+		if (pdata->pxav1_controller) {
+			host->quirks |=	SDHCI_QUIRK_NO_BUSY_IRQ
+					| SDHCI_QUIRK_32BIT_DMA_SIZE;
+			pxav2_sdhci_ops.platform_specific_completion
+				= platform_specific_completion;
+		}
+
 		if (pdata->quirks)
 			host->quirks |= pdata->quirks;
 		if (pdata->host_caps)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 6f0bfc0..430eabd 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1001,6 +1001,9 @@ static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 		mdelay(1);
 	}
 
+	if (host->ops->platform_specific_completion)
+		host->ops->platform_specific_completion(host);
+
 	mod_timer(&host->timer, jiffies + 10 * HZ);
 
 	host->cmd = cmd;
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index a6d69b7..ef2efd3 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -282,6 +282,7 @@ struct sdhci_ops {
 	void	(*platform_resume)(struct sdhci_host *host);
 	void    (*adma_workaround)(struct sdhci_host *host, u32 intmask);
 	void	(*platform_init)(struct sdhci_host *host);
+	void	(*platform_specific_completion)(struct sdhci_host *host);
 };
 
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
diff --git a/include/linux/platform_data/pxa_sdhci.h b/include/linux/platform_data/pxa_sdhci.h
index 27d3156..865a578 100644
--- a/include/linux/platform_data/pxa_sdhci.h
+++ b/include/linux/platform_data/pxa_sdhci.h
@@ -54,6 +54,8 @@ struct sdhci_pxa_platdata {
 	unsigned int	quirks;
 	unsigned int	quirks2;
 	unsigned int	pm_caps;
+	bool		pxav1_controller;  /* set if pxa168 */
+	unsigned int	delay_in_ms;
 };
 
 struct sdhci_pxa {
-- 
1.7.9.5

*************************************************************************************************************************************************************
eInfochips Business Disclaimer : This e-mail message and all attachments transmitted with it are intended solely for the use of the addressee and may contain legally privileged and confidential information. If the reader of this message is not the intended recipient, or an employee or agent responsible for delivering this message to the intended recipient, you are hereby notified that any dissemination, distribution, copying, or other use of this message or its attachments is strictly prohibited. If you have received this message in error, please notify the sender immediately by replying to this message and please delete it from your computer. Any views expressed in this message are those of the individual sender unless otherwise stated. Company has taken enough precautions to prevent the spread of viruses. However the company accepts no liability for any damage caused by any virus transmitted by this email.
*************************************************************************************************************************************************************


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Notice: 
This message has been scanned by Trend Micro Mail Security scanner and is believed to be clean
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[PATCH v2 4/4] ARM: pxa168/gplugd: Add support for SD port 1

[Tanmay Upadhyay]

v2 - after sdhci-pxav1 driver is merged with sdhci-pxav2, pass
     pxav1_controller = 1
   - as sdhci device numbering now starts from 1, call
     pxa168_add_sdh accordingly

Signed-off-by: Tanmay Upadhyay <tanmay.upadhyay@einfochips.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
---
 arch/arm/mach-mmp/gplugd.c |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c
index 5c3d61e..d821368 100644
--- a/arch/arm/mach-mmp/gplugd.c
+++ b/arch/arm/mach-mmp/gplugd.c
@@ -155,6 +155,11 @@ struct pxa168_eth_platform_data gplugd_eth_platform_data = {
 	.init        = gplugd_eth_init,
 };
 
+struct sdhci_pxa_platdata gplugd_sdh_platdata = {
+	.delay_in_ms = 5,
+	.pxav1_controller = 1,
+};
+
 static void __init select_disp_freq(void)
 {
 	/* set GPIO 35 & clear GPIO 85 to set LCD External Clock to 74.25 MHz */
@@ -188,6 +193,7 @@ static void __init gplugd_init(void)
 	platform_device_register(&pxa168_device_gpio);
 
 	pxa168_add_eth(&gplugd_eth_platform_data);
+	pxa168_add_sdh(1, &gplugd_sdh_platdata);
 }
 
 MACHINE_START(GPLUGD, "PXA168-based GuruPlug Display (gplugD) Platform")
-- 
1.7.9.5

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[PATCH v2 4/4] ARM: pxa168/gplugd: Add support for SD port 1

[Haojian Zhuang]

On Mon, Mar 18, 2013 at 2:20 AM, Tanmay Upadhyay
<tanmay.upadhyay@einfochips.com> wrote:
> v2 - after sdhci-pxav1 driver is merged with sdhci-pxav2, pass
>      pxav1_controller = 1
>    - as sdhci device numbering now starts from 1, call
>      pxa168_add_sdh accordingly
>
> Signed-off-by: Tanmay Upadhyay <tanmay.upadhyay@einfochips.com>
> Reviewed-by: Philip Rakity <prakity@marvell.com>
> ---
>  arch/arm/mach-mmp/gplugd.c |    6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c
> index 5c3d61e..d821368 100644
> --- a/arch/arm/mach-mmp/gplugd.c
> +++ b/arch/arm/mach-mmp/gplugd.c
> @@ -155,6 +155,11 @@ struct pxa168_eth_platform_data gplugd_eth_platform_data = {
>         .init        = gplugd_eth_init,
>  };
>
> +struct sdhci_pxa_platdata gplugd_sdh_platdata = {
> +       .delay_in_ms = 5,
> +       .pxav1_controller = 1,
> +};
> +
>  static void __init select_disp_freq(void)
>  {
>         /* set GPIO 35 & clear GPIO 85 to set LCD External Clock to 74.25 MHz */
> @@ -188,6 +193,7 @@ static void __init gplugd_init(void)
>         platform_device_register(&pxa168_device_gpio);
>
>         pxa168_add_eth(&gplugd_eth_platform_data);
> +       pxa168_add_sdh(1, &gplugd_sdh_platdata);
>  }
>
>  MACHINE_START(GPLUGD, "PXA168-based GuruPlug Display (gplugD) Platform")
> --
> 1.7.9.5
>

Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>

[PATCH v6 2/4] ARM: pxa168: Add SDHCI support

[Haojian Zhuang]

On Mon, Mar 18, 2013 at 2:18 AM, Tanmay Upadhyay
<tanmay.upadhyay@einfochips.com> wrote:
> v2 - clock register for SDHCI are not common across all MMP SoCs.
>      So, move PXA168 implementation to pxa168.c
>
> v3 - sdhci-pxav1 driver code is merged with sdhci-pxav2. So, change
>      the device name accordingly
>    - start sdhci device numbering from 1 as other PXA168 devices
>      does that
>
> v4 - Use different names for SD clock registers for PXA168 instead
>      of redefining them in pxa168.c. Suggested by Haojian Zhuang
>
> v5 - Have two different clock enable functions for clock block 1 & 2
>      & don't change indentation in regs-apmu.h as suggested by Haojian
>      Zhuang
>    - Use device name while adding clock as suggested by Russell King
>
> v6 - Rebase for Linux v3.8; de-select COMMON_CLK for PXA168 as its
>      SDHCI clocks should be handled differently than others
> ---
>  arch/arm/mach-mmp/Kconfig               |    1 -
>  arch/arm/mach-mmp/clock-pxa168.c        |   47 +++++++++++++++++++++++++++++++
>  arch/arm/mach-mmp/include/mach/pxa168.h |   20 +++++++++++++
>  arch/arm/mach-mmp/pxa168.c              |    4 +++
>  4 files changed, 71 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
> index ebdda83..530245c 100644
> --- a/arch/arm/mach-mmp/Kconfig
> +++ b/arch/arm/mach-mmp/Kconfig
> @@ -111,7 +111,6 @@ endmenu
>
>  config CPU_PXA168
>         bool
> -       select COMMON_CLK
>         select CPU_MOHAWK
>         help
>           Select code specific to PXA168
> diff --git a/arch/arm/mach-mmp/clock-pxa168.c b/arch/arm/mach-mmp/clock-pxa168.c
> index 5e6c18c..65ea00e 100644
> --- a/arch/arm/mach-mmp/clock-pxa168.c
> +++ b/arch/arm/mach-mmp/clock-pxa168.c
> @@ -31,11 +31,49 @@
>  #define APBC_SSP4      APBC_REG(0x858)
>  #define APBC_SSP5      APBC_REG(0x85c)
>
> +#define APMU_SDH0      APMU_REG(0x054)
> +#define APMU_SDH1      APMU_REG(0x058)
>  #define APMU_NAND      APMU_REG(0x060)
>  #define APMU_LCD       APMU_REG(0x04c)
> +#define APMU_SDH2      APMU_REG(0x0e0)
> +#define APMU_SDH3      APMU_REG(0x0e4)
>  #define APMU_ETH       APMU_REG(0x0fc)
>  #define APMU_USB       APMU_REG(0x05c)
>
> +static void sdh1_clk_enable(struct clk *clk)
> +{
> +       /* Bits 3 & 0 in registers for host 0 should be set for host 1 also */
> +       __raw_writel(__raw_readl(APMU_SDH0) | 0x9, APMU_SDH0);
> +
> +       __raw_writel(__raw_readl(clk->clk_rst) | clk->enable_val, clk->clk_rst);
> +}
> +
> +static void sdh2_clk_enable(struct clk *clk)
> +{
> +       /* Bits 3 & 0 in registers for host 2 should be set for host 3 also */
> +       __raw_writel(__raw_readl(APMU_SDH2) | 0x9, APMU_SDH2);
> +
> +       __raw_writel(__raw_readl(clk->clk_rst) | clk->enable_val, clk->clk_rst);
> +}
> +
> +static void sdh_clk_disable(struct clk *clk)
> +{
> +       __raw_writel(__raw_readl(clk->clk_rst) & ~clk->enable_val,
> +                       clk->clk_rst);
> +}
> +
> +/* Block 1 for controller 0 & 1 */
> +struct clkops sdh1_clk_ops = {
> +       .enable         = sdh1_clk_enable,
> +       .disable        = sdh_clk_disable,
> +};
> +
> +/* Block 2 for controller 2 & 3 */
> +struct clkops sdh2_clk_ops = {
> +       .enable         = sdh2_clk_enable,
> +       .disable        = sdh_clk_disable,
> +};
> +
>  /* APB peripheral clocks */
>  static APBC_CLK(uart1, UART1, 1, 14745600);
>  static APBC_CLK(uart2, UART2, 1, 14745600);
> @@ -60,6 +98,11 @@ static APMU_CLK(lcd, LCD, 0x7f, 312000000);
>  static APMU_CLK(eth, ETH, 0x09, 0);
>  static APMU_CLK(usb, USB, 0x12, 0);
>
> +static APMU_CLK_OPS(sdh1, SDH0, 0x12, 48000000, &sdh1_clk_ops);
> +static APMU_CLK_OPS(sdh2, SDH1, 0x12, 48000000, &sdh1_clk_ops);
> +static APMU_CLK_OPS(sdh3, SDH2, 0x12, 48000000, &sdh2_clk_ops);
> +static APMU_CLK_OPS(sdh4, SDH3, 0x12, 48000000, &sdh2_clk_ops);
> +
>  /* device and clock bindings */
>  static struct clk_lookup pxa168_clkregs[] = {
>         INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
> @@ -83,6 +126,10 @@ static struct clk_lookup pxa168_clkregs[] = {
>         INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
>         INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
>         INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
> +       INIT_CLKREG(&clk_sdh1, "sdhci-pxav2.0", "PXA-SDHCLK"),
> +       INIT_CLKREG(&clk_sdh2, "sdhci-pxav2.1", "PXA-SDHCLK"),
> +       INIT_CLKREG(&clk_sdh3, "sdhci-pxav2.2", "PXA-SDHCLK"),
> +       INIT_CLKREG(&clk_sdh4, "sdhci-pxav2.3", "PXA-SDHCLK"),
>  };
>
>  void __init pxa168_clk_init(void)
> diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
> index 37632d9..805117e 100644
> --- a/arch/arm/mach-mmp/include/mach/pxa168.h
> +++ b/arch/arm/mach-mmp/include/mach/pxa168.h
> @@ -17,6 +17,7 @@ extern void pxa168_clear_keypad_wakeup(void);
>  #include <mach/cputype.h>
>  #include <linux/pxa168_eth.h>
>  #include <linux/platform_data/mv_usb.h>
> +#include <linux/platform_data/pxa_sdhci.h>
>
>  extern struct pxa_device_desc pxa168_device_uart1;
>  extern struct pxa_device_desc pxa168_device_uart2;
> @@ -36,6 +37,10 @@ extern struct pxa_device_desc pxa168_device_nand;
>  extern struct pxa_device_desc pxa168_device_fb;
>  extern struct pxa_device_desc pxa168_device_keypad;
>  extern struct pxa_device_desc pxa168_device_eth;
> +extern struct pxa_device_desc pxa168_device_sdh1;
> +extern struct pxa_device_desc pxa168_device_sdh2;
> +extern struct pxa_device_desc pxa168_device_sdh3;
> +extern struct pxa_device_desc pxa168_device_sdh4;
>
>  /* pdata can be NULL */
>  extern int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata);
> @@ -133,4 +138,19 @@ static inline int pxa168_add_eth(struct pxa168_eth_platform_data *data)
>  {
>         return pxa_register_device(&pxa168_device_eth, data, sizeof(*data));
>  }
> +
> +static inline int pxa168_add_sdh(int id, struct sdhci_pxa_platdata *data)
> +{
> +       struct pxa_device_desc *d = NULL;
> +
> +       switch (id) {
> +       case 1: d = &pxa168_device_sdh1; break;
> +       case 2: d = &pxa168_device_sdh2; break;
> +       case 3: d = &pxa168_device_sdh3; break;
> +       case 4: d = &pxa168_device_sdh4; break;
> +       default:
> +               return -EINVAL;
> +       }
> +       return pxa_register_device(d, data, sizeof(*data));
> +}
>  #endif /* __ASM_MACH_PXA168_H */
> diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
> index b7f074f..ab5f273 100644
> --- a/arch/arm/mach-mmp/pxa168.c
> +++ b/arch/arm/mach-mmp/pxa168.c
> @@ -114,6 +114,10 @@ PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61);
>  PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8);
>  PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c);
>  PXA168_DEVICE(eth, "pxa168-eth", -1, MFU, 0xc0800000, 0x0fff);
> +PXA168_DEVICE(sdh1, "sdhci-pxav2", 0, SDH1, 0xd4280000, 0x100);
> +PXA168_DEVICE(sdh2, "sdhci-pxav2", 1, SDH1, 0xd4281000, 0x100);
> +PXA168_DEVICE(sdh3, "sdhci-pxav2", 2, SDH2, 0xd427e000, 0x100);
> +PXA168_DEVICE(sdh4, "sdhci-pxav2", 3, SDH2, 0xd427f000, 0x100);
>
>  struct resource pxa168_resource_gpio[] = {
>         {
> --
> 1.7.9.5
>

No, we shouldn't drop COMMON_CLK. Now you're using legacy code that
isn't our goal.

You should enable DT mode. Please refer to drivers/clk/mmp/clk-pxa168.c.
I think that SD clocks are already considered.

Regards
Haojian

[PATCH v6 2/4] ARM: pxa168: Add SDHCI support

[Tanmay Upadhyay]

On 3/17/13 8:13 PM, Haojian Zhuang wrote:
> On Mon, Mar 18, 2013 at 2:18 AM, Tanmay Upadhyay
> <tanmay.upadhyay@einfochips.com> wrote:
>> v2 - clock register for SDHCI are not common across all MMP SoCs.
>>       So, move PXA168 implementation to pxa168.c
>>
>> v3 - sdhci-pxav1 driver code is merged with sdhci-pxav2. So, change
>>       the device name accordingly
>>     - start sdhci device numbering from 1 as other PXA168 devices
>>       does that
>>
>> v4 - Use different names for SD clock registers for PXA168 instead
>>       of redefining them in pxa168.c. Suggested by Haojian Zhuang
>>
>> v5 - Have two different clock enable functions for clock block 1 & 2
>>       & don't change indentation in regs-apmu.h as suggested by Haojian
>>       Zhuang
>>     - Use device name while adding clock as suggested by Russell King
>>
>> v6 - Rebase for Linux v3.8; de-select COMMON_CLK for PXA168 as its
>>       SDHCI clocks should be handled differently than others
>> ---
>>   arch/arm/mach-mmp/Kconfig               |    1 -
>>   arch/arm/mach-mmp/clock-pxa168.c        |   47 +++++++++++++++++++++++++++++++
>>   arch/arm/mach-mmp/include/mach/pxa168.h |   20 +++++++++++++
>>   arch/arm/mach-mmp/pxa168.c              |    4 +++
>>   4 files changed, 71 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
>> index ebdda83..530245c 100644
>> --- a/arch/arm/mach-mmp/Kconfig
>> +++ b/arch/arm/mach-mmp/Kconfig
>> @@ -111,7 +111,6 @@ endmenu
>>
>>   config CPU_PXA168
>>          bool
>> -       select COMMON_CLK
>>          select CPU_MOHAWK
>>          help
>>            Select code specific to PXA168
>> diff --git a/arch/arm/mach-mmp/clock-pxa168.c b/arch/arm/mach-mmp/clock-pxa168.c
>> index 5e6c18c..65ea00e 100644
>> --- a/arch/arm/mach-mmp/clock-pxa168.c
>> +++ b/arch/arm/mach-mmp/clock-pxa168.c
>> @@ -31,11 +31,49 @@
>>   #define APBC_SSP4      APBC_REG(0x858)
>>   #define APBC_SSP5      APBC_REG(0x85c)
>>
>> +#define APMU_SDH0      APMU_REG(0x054)
>> +#define APMU_SDH1      APMU_REG(0x058)
>>   #define APMU_NAND      APMU_REG(0x060)
>>   #define APMU_LCD       APMU_REG(0x04c)
>> +#define APMU_SDH2      APMU_REG(0x0e0)
>> +#define APMU_SDH3      APMU_REG(0x0e4)
>>   #define APMU_ETH       APMU_REG(0x0fc)
>>   #define APMU_USB       APMU_REG(0x05c)
>>
>> +static void sdh1_clk_enable(struct clk *clk)
>> +{
>> +       /* Bits 3 & 0 in registers for host 0 should be set for host 1 also */
>> +       __raw_writel(__raw_readl(APMU_SDH0) | 0x9, APMU_SDH0);
>> +
>> +       __raw_writel(__raw_readl(clk->clk_rst) | clk->enable_val, clk->clk_rst);
>> +}
>> +
>> +static void sdh2_clk_enable(struct clk *clk)
>> +{
>> +       /* Bits 3 & 0 in registers for host 2 should be set for host 3 also */
>> +       __raw_writel(__raw_readl(APMU_SDH2) | 0x9, APMU_SDH2);
>> +
>> +       __raw_writel(__raw_readl(clk->clk_rst) | clk->enable_val, clk->clk_rst);
>> +}
>> +
>> +static void sdh_clk_disable(struct clk *clk)
>> +{
>> +       __raw_writel(__raw_readl(clk->clk_rst) & ~clk->enable_val,
>> +                       clk->clk_rst);
>> +}
>> +
>> +/* Block 1 for controller 0 & 1 */
>> +struct clkops sdh1_clk_ops = {
>> +       .enable         = sdh1_clk_enable,
>> +       .disable        = sdh_clk_disable,
>> +};
>> +
>> +/* Block 2 for controller 2 & 3 */
>> +struct clkops sdh2_clk_ops = {
>> +       .enable         = sdh2_clk_enable,
>> +       .disable        = sdh_clk_disable,
>> +};
>> +
>>   /* APB peripheral clocks */
>>   static APBC_CLK(uart1, UART1, 1, 14745600);
>>   static APBC_CLK(uart2, UART2, 1, 14745600);
>> @@ -60,6 +98,11 @@ static APMU_CLK(lcd, LCD, 0x7f, 312000000);
>>   static APMU_CLK(eth, ETH, 0x09, 0);
>>   static APMU_CLK(usb, USB, 0x12, 0);
>>
>> +static APMU_CLK_OPS(sdh1, SDH0, 0x12, 48000000, &sdh1_clk_ops);
>> +static APMU_CLK_OPS(sdh2, SDH1, 0x12, 48000000, &sdh1_clk_ops);
>> +static APMU_CLK_OPS(sdh3, SDH2, 0x12, 48000000, &sdh2_clk_ops);
>> +static APMU_CLK_OPS(sdh4, SDH3, 0x12, 48000000, &sdh2_clk_ops);
>> +
>>   /* device and clock bindings */
>>   static struct clk_lookup pxa168_clkregs[] = {
>>          INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
>> @@ -83,6 +126,10 @@ static struct clk_lookup pxa168_clkregs[] = {
>>          INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
>>          INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
>>          INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
>> +       INIT_CLKREG(&clk_sdh1, "sdhci-pxav2.0", "PXA-SDHCLK"),
>> +       INIT_CLKREG(&clk_sdh2, "sdhci-pxav2.1", "PXA-SDHCLK"),
>> +       INIT_CLKREG(&clk_sdh3, "sdhci-pxav2.2", "PXA-SDHCLK"),
>> +       INIT_CLKREG(&clk_sdh4, "sdhci-pxav2.3", "PXA-SDHCLK"),
>>   };
>>
>>   void __init pxa168_clk_init(void)
>> diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
>> index 37632d9..805117e 100644
>> --- a/arch/arm/mach-mmp/include/mach/pxa168.h
>> +++ b/arch/arm/mach-mmp/include/mach/pxa168.h
>> @@ -17,6 +17,7 @@ extern void pxa168_clear_keypad_wakeup(void);
>>   #include <mach/cputype.h>
>>   #include <linux/pxa168_eth.h>
>>   #include <linux/platform_data/mv_usb.h>
>> +#include <linux/platform_data/pxa_sdhci.h>
>>
>>   extern struct pxa_device_desc pxa168_device_uart1;
>>   extern struct pxa_device_desc pxa168_device_uart2;
>> @@ -36,6 +37,10 @@ extern struct pxa_device_desc pxa168_device_nand;
>>   extern struct pxa_device_desc pxa168_device_fb;
>>   extern struct pxa_device_desc pxa168_device_keypad;
>>   extern struct pxa_device_desc pxa168_device_eth;
>> +extern struct pxa_device_desc pxa168_device_sdh1;
>> +extern struct pxa_device_desc pxa168_device_sdh2;
>> +extern struct pxa_device_desc pxa168_device_sdh3;
>> +extern struct pxa_device_desc pxa168_device_sdh4;
>>
>>   /* pdata can be NULL */
>>   extern int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata);
>> @@ -133,4 +138,19 @@ static inline int pxa168_add_eth(struct pxa168_eth_platform_data *data)
>>   {
>>          return pxa_register_device(&pxa168_device_eth, data, sizeof(*data));
>>   }
>> +
>> +static inline int pxa168_add_sdh(int id, struct sdhci_pxa_platdata *data)
>> +{
>> +       struct pxa_device_desc *d = NULL;
>> +
>> +       switch (id) {
>> +       case 1: d = &pxa168_device_sdh1; break;
>> +       case 2: d = &pxa168_device_sdh2; break;
>> +       case 3: d = &pxa168_device_sdh3; break;
>> +       case 4: d = &pxa168_device_sdh4; break;
>> +       default:
>> +               return -EINVAL;
>> +       }
>> +       return pxa_register_device(d, data, sizeof(*data));
>> +}
>>   #endif /* __ASM_MACH_PXA168_H */
>> diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
>> index b7f074f..ab5f273 100644
>> --- a/arch/arm/mach-mmp/pxa168.c
>> +++ b/arch/arm/mach-mmp/pxa168.c
>> @@ -114,6 +114,10 @@ PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61);
>>   PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8);
>>   PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c);
>>   PXA168_DEVICE(eth, "pxa168-eth", -1, MFU, 0xc0800000, 0x0fff);
>> +PXA168_DEVICE(sdh1, "sdhci-pxav2", 0, SDH1, 0xd4280000, 0x100);
>> +PXA168_DEVICE(sdh2, "sdhci-pxav2", 1, SDH1, 0xd4281000, 0x100);
>> +PXA168_DEVICE(sdh3, "sdhci-pxav2", 2, SDH2, 0xd427e000, 0x100);
>> +PXA168_DEVICE(sdh4, "sdhci-pxav2", 3, SDH2, 0xd427f000, 0x100);
>>
>>   struct resource pxa168_resource_gpio[] = {
>>          {
>> --
>> 1.7.9.5
>>
> No, we shouldn't drop COMMON_CLK. Now you're using legacy code that
> isn't our goal.
>
> You should enable DT mode. Please refer to drivers/clk/mmp/clk-pxa168.c.
> I think that SD clocks are already considered.
>
> Regards
> Haojian

I am sorry, I wasn't aware of this development. As per 
ARMADA_16x_Software_Manual.pdf enabling clock for SD controller 2 & 4 
needs to set bit 3 & 0 in registers for SD controller 1 & 3 
(respectively). This is done by below code in my patch. Now what's the 
best way to do this with new COMMON_CLK implementation? If I make SD 
clock 0 & 2 parents for 1 & 3, it will unnecessarily keep clocks enabled 
for other controllers whether or not they are needed. What's "DT" mode?

+static void sdh1_clk_enable(struct clk *clk)
+{
+       /* Bits 3 & 0 in registers for host 0 should be set for host 1 also */
+       __raw_writel(__raw_readl(APMU_SDH0) | 0x9, APMU_SDH0);
...

+static void sdh2_clk_enable(struct clk *clk)
+{
+       /* Bits 3 & 0 in registers for host 2 should be set for host 3 also */
+       __raw_writel(__raw_readl(APMU_SDH2) | 0x9, APMU_SDH2);

Thanks,

Tanmay

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