From: haojian.zhuang@gmail.com (Haojian Zhuang)
To: linux-arm-kernel@lists.infradead.org
Subject: Question about ION carveout heap support partial cache flush
Date: Mon, 27 Aug 2012 21:45:23 +0800 [thread overview]
Message-ID: <CAN1soZyPp4--G3GjSpy8JZViFE4ed8dSyRnxgBfORam21SzpDQ@mail.gmail.com> (raw)
In-Reply-To: <CAMj5BkjqUNV2o_BMyHH8C5ZCsUf6qChamc6h4H-a9otEGVBx4A@mail.gmail.com>
On Mon, Aug 27, 2012 at 4:56 PM, zhangfei gao <zhangfei.gao@gmail.com> wrote:
>
> Any suggestion of flushing cache according to cache line, instead of PAGE_SIZE.
> In order to get specific area, we use addr from user directly, which
> may not be the PAGE start.
>
> We have some usage case to flush cache according to cache line.
> CPU - cache - ddr - gpu
> 1. For correctness, driver only flush used size, if align to PAGE_SIZE,
> other area may be flushed by mistake.
> 2. for efficiency, cache line align will be perfered.
I think that maybe flushing PAGE_SIZE is acceptable. ION/PMEM is always designed
for large memory sharing. Maybe you can monitor the partial flushing
user case, I doubt
they're always flushing several pages, not several cachelines.
next prev parent reply other threads:[~2012-08-27 13:45 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CAMj5BkgffAW6azUjwz+iCF1tBLmBDRBvBjR-_fTr=4G=h+BLZw@mail.gmail.com>
[not found] ` <CAN1soZyZ=4wjKkVrk5--2U_8SeT7qee9QAfhss7NgqtQAz+RrA@mail.gmail.com>
2012-08-27 8:23 ` Question about ION carveout heap support partial cache flush zhangfei gao
2012-08-27 8:29 ` Russell King - ARM Linux
2012-08-27 8:56 ` zhangfei gao
2012-08-27 13:45 ` Haojian Zhuang [this message]
2012-08-27 13:43 ` Haojian Zhuang
2012-08-27 19:14 ` Russell King - ARM Linux
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