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Tue, 15 Oct 2024 02:00:40 -0700 (PDT) MIME-Version: 1.0 References: <20241014135210.224913-1-linux.amoon@gmail.com> <20241014135210.224913-3-linux.amoon@gmail.com> <20241015051141.g6fh222zrkvnn4l6@thinkpad> In-Reply-To: <20241015051141.g6fh222zrkvnn4l6@thinkpad> From: Anand Moon Date: Tue, 15 Oct 2024 14:30:23 +0530 Message-ID: Subject: Re: [PATCH v8 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function To: Manivannan Sadhasivam Cc: Shawn Lin , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Philipp Zabel , "open list:PCIE DRIVER FOR ROCKCHIP" , "open list:PCIE DRIVER FOR ROCKCHIP" , "moderated list:ARM/Rockchip SoC support" , open list Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241015_020043_204405_039CFC82 X-CRM114-Status: GOOD ( 22.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Manivannan, Thanks for your review comments. On Tue, 15 Oct 2024 at 10:41, Manivannan Sadhasivam wrote: > > On Mon, Oct 14, 2024 at 07:22:03PM +0530, Anand Moon wrote: > > Refactor the reset control handling in the Rockchip PCIe driver, > > introduce a more robust and efficient method for assert and > > deassert reset controller using reset_control_bulk*() API. Using the > > reset_control_bulk APIs, the reset handling for the core clocks reset > > unit becomes much simpler. > > > > Spilt the reset controller in two groups as per the > > RK3399 TM 17.5.8.1 PCIe Initialization Sequence > > 17.5.8.1.1 PCIe as Root Complex. > > > > 6. De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N > > simultaneously. > > > > I'd reword it slightly: > > Following the recommendations in 'Rockchip RK3399 TRM v1.3 Part2': > > 1. Split the reset controls into two groups as per section '17.5.8.1.1 PC= Ie > as Root Complex'. > > 2. Deassert the 'Pipe, MGMT Sticky, MGMT, Core' resets in groups as per s= ection > '17.5.8.1.1 PCIe as Root Complex'. This is accomplished using the > reset_control_bulk APIs. > > > - devm_reset_control_bulk_get_exclusive(): Allows the driver to get all > > resets defined in the DT thereby removing the hardcoded reset names > > in the driver. > > - reset_control_bulk_assert(): Allows the driver to assert the resets > > defined in the driver. > > - reset_control_bulk_deassert(): Allows the driver to deassert the rese= ts > > defined in the driver. > > > > No need to list out the APIs. Just add them to the first paragraph itself= to > explain how they are used. > Here is a short version of the commit message. Introduce a more robust and efficient method for assert and deassert the reset controller using the reset_control_bulk*() API. Simplify reset handling for the core clocks reset unit with the reset_control_bulk APIs. devm_reset_control_bulk_get_exclusive(): Obtain all resets from the device tree, removing hardcoded names. reset_control_bulk_assert(): assert the resets defined in the driver. reset_control_bulk_deassert(): deassert the resets defined in the driver.. Following the recommendations in 'Rockchip RK3399 TRM v1.3 Part2': 1. Split the reset controls into two groups as per section '17.5.8.1.1 PCIe as Root Complex'. 2. Deassert the 'Pipe, MGMT Sticky, MGMT, Core' resets in groups as per sec= tion '17.5.8.1.1 PCIe as Root Complex'. This is accomplished using the reset_control_bulk APIs. Does this look good to you? Let me know if you need any further adjustments= ! I will fix this for CLK bulk as well. > > Signed-off-by: Anand Moon > > Some nitpicks below. Rest looks good. I will fix these in the next version. > - Mani > > -- > =E0=AE=AE=E0=AE=A3=E0=AE=BF=E0=AE=B5=E0=AE=A3=E0=AF=8D=E0=AE=A3=E0=AE=A9= =E0=AF=8D =E0=AE=9A=E0=AE=A4=E0=AE=BE=E0=AE=9A=E0=AE=BF=E0=AE=B5=E0=AE=AE= =E0=AF=8D Thanks -Anand