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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=6+RXNXhpTXKEfC6S70g/8i+oFfgdbr0pGKSaIvIWKGI=; b=uKP3gI5BVUFiVBMazv7JN43nTmtGNXhrHGgnEpNPp1Y2WBPMl+0R8h0epQsc+L5lf4 lPfvhCJ2s/b58dYY8w63heYKmYYpby494dt03jDDoCJ56tHMTZ2Co2Y6uzfnWk+FLX0t OqFEstkYNwSCRPRy1WvzWD/JpvDJ2ZEop1kNJ5+jfpT+8ToOQKgy8e17UtcWQnuqPxic /wp3q7hyV9WS9X6Vw+fyIhXK1Szn4MQMHQCMX8b9ojYew/SAeGSlU9J4Q+Ar8MiuXywR 7FB6ISkDxr4lq6mS60ltgcVP5ySvBnrc1BW08OvVsTIu75L7DPLQZ8fMAPkPchvxv82j egEA== X-Gm-Message-State: APjAAAU/BNgdSs86NIYhm/LR2Rk0LVu6SQkpl1DNlFOjHGYgFZFgSXhE bON2z45T9zOly++HZKLLi+kx6zb+5Cdq4UYMUa5SPA== X-Google-Smtp-Source: APXvYqyfVT1jfyR3JEPZVwQbvsih7FgsTA5dsHiTL3lseum+/tgxSuhr6IxQZcqS6/dg//vok6rwysMx73So/rHsbIU= X-Received: by 2002:a24:ee83:: with SMTP id b125mr29308149iti.43.1555443454772; Tue, 16 Apr 2019 12:37:34 -0700 (PDT) MIME-Version: 1.0 References: <20190325215632.17013-1-mathieu.poirier@linaro.org> <79296dd5-809f-abac-cde8-a1c55592f12b@arm.com> In-Reply-To: <79296dd5-809f-abac-cde8-a1c55592f12b@arm.com> From: Mathieu Poirier Date: Tue, 16 Apr 2019 13:37:23 -0600 Message-ID: Subject: Re: [PATCH v2 00/16] coresight: Add support for CPU-wide trace scenarios To: Robert Walker X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190416_123736_976075_DA3BFB78 X-CRM114-Status: GOOD ( 24.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander Shishkin , Peter Zijlstra , Coresight ML , Mike Leach , linux-arm-kernel Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Robert, On Thu, 11 Apr 2019 at 12:52, Robert Walker wrote: > > Hi Mathieu, > > On 25/03/2019 21:56, Mathieu Poirier wrote: > > This is the second revision of a patchset that adds support for CPU-wide > > trace scenarios and as such, it is now possible to issue the following > > commands: > > > > # perf record -e cs_etm/@20070000.etr/ -C 2,3 $COMMAND > > # perf record -e cs_etm/@20070000.etr/ -a $COMMAND > > > > The solution is designed to work for both 1:1 and N:1 source/sink > > topologies, though the former hasn't been tested for lack of access to HW. > > > > Most of the changes revolve around allowing more than one event to use > > a sink when operated from perf. More specifically the first event to > > use a sink switches it on while the last one is tasked to aggregate traces > > and switching off the device. > > > > This is the kernel part of the solution, with the user space portion to be > > released in a later set. All patches (user and kernel) have been rebased > > on v5.1-rc2 and are hosted here[1]. Everything has been tested on Juno and > > 410c dragonboard platforms. > > > > Regards, > > Mathieu > > > > [1]. https://git.linaro.org/people/mathieu.poirier/coresight.git (5.1-rc2-cpu-wide-v2) > > > I've tested this patch set and the associated perf patches on the HiKey > 960 - trace collection and decode appears to work OK. However, in order > to get the timestamps in the trace stream, I needed to enable the > CoreSight Timestamp generator before starting trace. Without this, all > the timestamp packets had a value of 0. This will likely affect other > platforms. For testing purposes, I enabled it by poking the control > register directly via /dev/mem, but for full support you will need a > driver for this component (it's fairly simple - just a single register > to write to enable / disable) and entries in the device tree / ACPI > tables - it's similar to the helper devices like CTI & CATU which aren't > on the trace data path, but are associated with a device that is. > Thank you for taking the time to test this. Can I add your "Tested-by:" to the set? Platforms where the timestamp generator needs to explicitly be enabled are slowly emerging - I have heard of the issue on the CS mailing list about a month ago. Since I don't have HW to test the feature it will not be part of this set. > Also, the use of a counter to generate the timestamps periodically > conflicts with the ETM strobing patch we've been using for AutoFDO. > This strobing requires 2 counters and as most ETM implementations only > have 2 counters, there is only one available if one is used for > timestamps. We'll have to do some investigation to work out a way > around this. I noticed that clocks were in short supply and as such added an explicity test to make sure there were enough of them before proceeding. Like topology issues there isn't much we can currently do other than preventing a trace session from moving forward if there isn't enough counters. Thanks, Mathieu > > Regards > > Rob > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel