* [RFC v9 0/8] ARM: shmobile: DT initialisation of INTC
@ 2013-01-09 6:29 Simon Horman
2013-01-09 6:30 ` [PATCH 1/8] SH: intc: Add support OF for INTC Simon Horman
` (7 more replies)
0 siblings, 8 replies; 17+ messages in thread
From: Simon Horman @ 2013-01-09 6:29 UTC (permalink / raw)
To: linux-arm-kernel
The aims of this series are:
* Add DT bindings to to INTC
* Allowing sh7372 and r8a7740 ARM shmobile SoCs to use DT
to initialise INTCA
Changes since v8
* Address review of bindings by Mark Rutland
Change between v7 and v8
* Squash the first and second patch of the series and rename there result
"SH: intc: Add support OF for INTC"
Changes between v5 and v7 (v6 was not publicly released)
* Drop support for sh73a0 SoC.
To be useful this requires a fuller initialisation than jsut INCA.
In particular, cascade IRQs that are shared between INTC and GIC
need to be handled.
* Drop board support
This will be revisited on a per-board basis, ideally with
filler INTC initialisation via DT in place
* Drop GIC initialisation
This will also be revisited on a per-board basis.
* Remove unused INTC DT helper functions
Status:
I am reasonably happy with this series and plan to merge the patch set.
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 1/8] SH: intc: Add support OF for INTC 2013-01-09 6:29 [RFC v9 0/8] ARM: shmobile: DT initialisation of INTC Simon Horman @ 2013-01-09 6:30 ` Simon Horman 2013-01-09 11:53 ` Mark Rutland 2013-01-09 6:30 ` [PATCH 2/8] ARM: shmobile: Add support OF of INTC for r8a7740 Simon Horman ` (6 subsequent siblings) 7 siblings, 1 reply; 17+ messages in thread From: Simon Horman @ 2013-01-09 6:30 UTC (permalink / raw) To: linux-arm-kernel From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> This provides OF support of SH/INTC. The SH/INTC driver is used by SuperH and ARM/SH-MOBILE. At the moment, SuperH does not have the plan corresponding to DT. DT of SH/INTC has taken the form where the table data of the C is managed by DT, in order to maintain compatibility. Cc: Magnus Damm <damm@opensource.se> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- v9 * As suggested by Mark Rutland - Update compatible string to use '-' instead of '_' - Enhance documentation - Remove group_size, it can be calculated - Allow missing traling reg * Add intc_groups and remove group_size. The number of groups can be calculated by containing them in a intc_groups node. v8 * Squash "SH: intc: Add support OF of IRQ" into this patch * Change patch title from "ARM: shmobile: Add support OF for INTC of shmobile" to "SH: intc: Add support OF for INTC" v7 * Delete "renesas,sh_intcs" and "renesas,sh_intca_irq_pins" as compatible. Update their documentation. * Remove of_sh_intc_get_meminfo() and of_sh_intc_get_pint and of_sh_intc_get_intc(). They are not used. v2 - v6 * No change --- Documentation/devicetree/bindings/sh/intc.txt | 191 ++++++++ drivers/sh/intc/Makefile | 1 + drivers/sh/intc/core.c | 2 +- drivers/sh/intc/internals.h | 3 +- drivers/sh/intc/irqdomain.c | 6 +- drivers/sh/intc/of_intc.c | 577 +++++++++++++++++++++++++ include/linux/sh_intc.h | 56 +++ 7 files changed, 831 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/sh/intc.txt create mode 100644 drivers/sh/intc/of_intc.c diff --git a/Documentation/devicetree/bindings/sh/intc.txt b/Documentation/devicetree/bindings/sh/intc.txt new file mode 100644 index 0000000..eb605ce --- /dev/null +++ b/Documentation/devicetree/bindings/sh/intc.txt @@ -0,0 +1,191 @@ +* Renesas SuperH / SH-MOBILE Interrupt Controller + +The SH/INTC driver is used by SuperH and ARM/SH-MOBILE. +At the moment, SuperH does not have the plan corresponding to DT. +DT of SH/INTC has taken the form where the table data of the C +is managed by DT, in order to maintain compatibility. + +The main node requires the following properties: + +- compatible : "renesas,sh-intc" + +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Must be 1 +- #address-cells : Must be 1 +- #size-cells : Must be 1 +- ranges : Empty as we have a 1-1 mapping to parent's + address space +- reg : Specifies base physical address(s) and size of + the INTC registers +- intsrc* : Interrupt source + Associate an interrupt source with its vector + +- *_registers : These describe the vector table, mask, priority, ack, + and sense registers. It must contain the following: + + -- intc_vectors : This describes the interrupt sources + This node requires the following property: + *vector_table : List of interrupt sources + + -- intc_mask_registers : This specifies the contents of the mask registers + This node requires the following properties: + * address-cells : Must be 1 + * size-cells : Must be 1 + * ranges : Empty as we have a 1-1 mapping to parent's + address space + * intc_mask* : A mask register + This node requires the following properties: + ** reg : This specifies the address of mask registers. + The first entry specifies the mask register and + the second entry specifies the mask clear + register. The first cell is the register's + address, and the second cell is the register's size + which must be 1, 2 or 4 bytes. + ** reginfo : This specifies the interrupt sources controlled by + the mask. The list entries correspond to bits of + the mask from most to least significant. A value + of 0 may be used for unused bits in the mask. + Trailing list entries may be omitted in which + case they will be treated as 0. + + -- intc_prio_registers : This sets up the contents of the priority registers + This node requires the following properties: + * address-cells : Must be 1 + * size-cells : Must be 1 + * ranges : Empty as we have a 1-1 mapping to parent's + address space + * intc_prio* : A sense register + This node requires the following properties: + ** reg : This specifies the address of the priority register. + The first entry specifies the priority set + register and the second entry specifies priority + clear register. The first cell is the register's + address, and the second cell is the register's + size which must be 1, 2 or 4 bytes. If there is + not priority clear register then they entry may + be omitted or 0 used as the register's address. + ** field-width: Width of each group in the register in bits. + A group contains the priority for a single + interrupt vector. Thus a 16 bit register with + a field-width of 4 may control the priority for + 4 (16 / 4) interrupt sources. + ** reginfo : This specifies the interrupt sources or interrupt + source groups controlled by the priority register. + The list entries correspond to the groups of the + priority register from least to most significant. + A value of 0 may be used for unused groups. + Trailing list entries may be omitted in which + case they will be treated as 0. + + -- intc_sense_registers : This sets up the contents of the sense registers + This node requires the following properties: + * address-cells : Must be 1 + * size-cells : Must be 1 + * ranges : Empty as we have a 1-1 mapping to parent's + address space + * intc_prio* : A sense register + This node requires the following properties: + ** reg : This specifies the address of the sense register. + The first cell is the register's address, and the + second cell is the register's size which must be + 1, 2 or 4 bytes. + ** field-width: Width of each group in the register in bits. + A group contains the priority for a single + interrupt vector. Thus a 16 bit register with + a field-width of 4 may control the priority for + 4 (16 / 4) interrupt sources. + ** reginfo : This specifies the interrupt sources controlled by + the sense register. The list entries correspond + to the groups of the priority register from least + to most significant. A value of 0 may be used + for unused groups. Trailing list entries may be + omitted in which case they will be treated as 0. + + -- intc_ack_registers : This sets up the contents of the ACK registers + This node requires the following properties: + * address-cells : Must be 1 + * size-cells : Must be 1 + * ranges : Empty as we have a 1-1 mapping to parent's + address space + * intc_ack* : An ACK registers + This node requires the following properties: + ** reg : This specifies the address of the ACK register. + The first cell is the register's address, and the + second cell is the register's size which must be + 1, 2 or 4 bytes. + ** reginfo : This specifies the interrupt sources controlled by + the ACK register. The list entries correspond to + bits of the ACK register from most to least + significant. A value of 0 may be used for unused + bits in the mask. Trailing list entries may be + omitted in which case they will be treated as 0. + +Optional: + +- intc_groups : The interrupt source groups + Interrupt sources may be grouped with a group + sharing the same bits of an interrupt priority + register. + This node requires the following property: + * intc_group* : An interrupt source group + This node requires the following property: + ** group : The list of interrupt sources that + belong to the group. + +- intc_intevtsa : This sets up the contents of INTEVTSA. + This node requires the following properties: + * vector : This specifies the interrupt source + +Example: + + intca: interrupt-controller at 0 { + compatible = "renesas,sh_intc"; + interrupt-controller; + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + reg = <0xe6940000 0x200>, <0xe6950000 0x200>; + group_size = <19>; + + DIRC: intsrc1 { vector = <0x0560>; }; + ATAPI: intsrc2 { vector = <0x05E0>; }; + .... + + DMAC1_1: intc_group0 { group = <&DMAC1_1_DEI0 &DMAC1_1_DEI1 + &DMAC1_1_DEI2 &DMAC1_1_DEI3>; }; + DMAC1_2: intc_group1 { group = <&DMAC1_2_DEI4 &DMAC1_2_DEI5 + &DMAC1_2_DADERR>; }; + .... + intc_vectors { + vector_table = <&DIRC &ATAPI &IIC1_ALI &IIC1_TACKI &IIC1_WAITI, + .... + }; + + intc_mask_registers { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc_mask0 { + reg = <0xe6940080 1>, <0xe69400c0 1>; + reginfo = <&DMAC2_1_DEI3 &DMAC2_1_DEI2 &DMAC2_1_DEI1 + &DMAC2_1_DEI0 0 0 &AP_ARM_COMMTX &AP_ARM_COMMRX>; + }; + .... + }; + + intc_prio_registers { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc_prio0 { + reg = <0xe6940000 2>; + field-width = <4>; + reginfo = <&DMAC3_1 &DMAC3_2 &CMT2 &ICBS0>; + }; + .... + }; + }; diff --git a/drivers/sh/intc/Makefile b/drivers/sh/intc/Makefile index 54ec2a0..b53ab7e 100644 --- a/drivers/sh/intc/Makefile +++ b/drivers/sh/intc/Makefile @@ -3,3 +3,4 @@ obj-y := access.o chip.o core.o handle.o irqdomain.o virq.o obj-$(CONFIG_INTC_BALANCING) += balancing.o obj-$(CONFIG_INTC_USERIMASK) += userimask.o obj-$(CONFIG_INTC_MAPPING_DEBUG) += virq-debugfs.o +obj-$(CONFIG_OF) += of_intc.o diff --git a/drivers/sh/intc/core.c b/drivers/sh/intc/core.c index 8f32a13..3963af3 100644 --- a/drivers/sh/intc/core.c +++ b/drivers/sh/intc/core.c @@ -311,7 +311,7 @@ int __init register_intc_controller(struct intc_desc *desc) BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ - intc_irq_domain_init(d, hw); + intc_irq_domain_init(d, hw, desc->of_node); /* register the vectors one by one */ for (i = 0; i < hw->nr_vectors; i++) { diff --git a/drivers/sh/intc/internals.h b/drivers/sh/intc/internals.h index 7dff08e..e6f64bf 100644 --- a/drivers/sh/intc/internals.h +++ b/drivers/sh/intc/internals.h @@ -190,7 +190,8 @@ void intc_enable_disable_enum(struct intc_desc *desc, struct intc_desc_int *d, intc_enum enum_id, int enable); /* irqdomain.c */ -void intc_irq_domain_init(struct intc_desc_int *d, struct intc_hw_desc *hw); +void intc_irq_domain_init(struct intc_desc_int *d, struct intc_hw_desc *hw, + struct device_node *of_node); /* virq.c */ void intc_subgroup_init(struct intc_desc *desc, struct intc_desc_int *d); diff --git a/drivers/sh/intc/irqdomain.c b/drivers/sh/intc/irqdomain.c index 3968f1c..c56c736 100644 --- a/drivers/sh/intc/irqdomain.c +++ b/drivers/sh/intc/irqdomain.c @@ -42,7 +42,7 @@ static const struct irq_domain_ops intc_evt_ops = { }; void __init intc_irq_domain_init(struct intc_desc_int *d, - struct intc_hw_desc *hw) + struct intc_hw_desc *hw, struct device_node *np) { unsigned int irq_base, irq_end; @@ -59,10 +59,10 @@ void __init intc_irq_domain_init(struct intc_desc_int *d, * tree penalty for linear cases with non-zero hwirq bases. */ if (irq_base == 0 && irq_end == (irq_base + hw->nr_vectors - 1)) - d->domain = irq_domain_add_linear(NULL, hw->nr_vectors, + d->domain = irq_domain_add_linear(np, hw->nr_vectors, &intc_evt_ops, NULL); else - d->domain = irq_domain_add_tree(NULL, &intc_evt_ops, NULL); + d->domain = irq_domain_add_tree(np, &intc_evt_ops, NULL); BUG_ON(!d->domain); } diff --git a/drivers/sh/intc/of_intc.c b/drivers/sh/intc/of_intc.c new file mode 100644 index 0000000..1d5f47e --- /dev/null +++ b/drivers/sh/intc/of_intc.c @@ -0,0 +1,577 @@ +/* + * OF helpers for SH intc + * + * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * Copyright (C) 2012 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/string.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/sh_intc.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> +#include <linux/of_address.h> + +static int __init of_sh_intc_get_reg_addrs(struct device_node *np, + unsigned long *set_reg, unsigned long *clr_reg, + unsigned long *reg_width, + unsigned long *field_width) +{ + struct resource res; + int err; + + if (set_reg) { + err = of_address_to_resource(np, 0, &res); + if (err) + return err; + *set_reg = res.start; + } + + if (resource_size(&res) && reg_width) + *reg_width = resource_size(&res) * 8; /* byte */ + + if (clr_reg) { + err = of_address_to_resource(np, 1, &res); + /* It is ok for this to be missing */ + if (err != -EINVAL) { + if (err) + return err; + *clr_reg = res.start; + } + } + + if (field_width) { + u32 width; + err = of_property_read_u32(np, "field-width", &width); + if (err) + return err; + *field_width = width; + } + + return 0; +} + +static int of_sh_intc_parse_vector(struct device_node *np, uint32_t *vect) +{ + return of_property_read_u32(np, "vector", vect); +} + +static int of_sh_intc_parse_group(struct device_node *np, + struct intc_group *grp) +{ + const __be32 *list, *list_end; + int size, ret = 0, count = 0; + phandle phandle; + + /* Retrieve the phandle list property */ + list = of_get_property(np, "group", &size); + if (!list) + return -ENOENT; + + list_end = list + size / sizeof(*list); + + grp->enum_id = np->phandle; + /* Loop over the phandles until all the requested entry is found */ + while (list < list_end) { + /* If phandle is 0, then it is an empty entry with + no arguments. */ + phandle = be32_to_cpup(list); + if (phandle) + grp->enum_ids[count] = phandle; + list++; + count++; + } + + pr_debug("%d:[", grp->enum_id); + for (size = 0 ; size < count ; size++) + pr_debug(" %d ", grp->enum_ids[size]); + + pr_debug("]\n"); + + return ret; +} + +static int of_sh_intc_parse_vectortbl(struct device_node *np, + struct intc_vect **vect, int *tbl_size) +{ + const __be32 *list, *list_end; + int size, ret = 0, count = 0; + struct device_node *node = NULL; + phandle phandle; + + /* Retrieve the phandle list property */ + list = of_get_property(np, "vector_table", &size); + if (!list) + return -ENOENT; + + *tbl_size = size / sizeof(*list); + + pr_debug("vector table size: %d\n", *tbl_size); + + *vect = kzalloc(sizeof(struct intc_vect) * *tbl_size, + GFP_KERNEL); + if (!*vect) + return -ENOMEM; + + list_end = list + *tbl_size; + + /* Loop over the phandles until all the requested entry is found */ + while (list < list_end) { + /* If phandle is 0, then it is an empty entry with + no arguments. */ + phandle = be32_to_cpup(list); + if (phandle) { + uint32_t vector_id; + + (*vect)[count].enum_id = phandle; + node = of_find_node_by_phandle(phandle); + + ret = of_sh_intc_parse_vector(node, &vector_id); + if (ret) + return ret; + + (*vect)[count].vect = vector_id; + pr_debug("id %d : vector 0x%x\n", + (*vect)[count].enum_id, (*vect)[count].vect); + } else { + ret = -EINVAL; + goto error; + } + list++; + count++; + } + return ret; + +error: + kfree(*vect); + + return ret; +} + +static int of_sh_intc_parse_reginfo(struct device_node *np, + struct intc_mask_reg *mask, + struct intc_prio_reg *prio, + struct intc_sense_reg *sense) +{ + const __be32 *list, *list_end; + int size, id, ret = 0, count = 0; + phandle phandle; + + /* Retrieve the phandle list property */ + list = of_get_property(np, "reginfo", &size); + if (!list) + return -ENOENT; + + list_end = list + size / sizeof(*list); + + /* Loop over the phandles until all the requested entry is found */ + while (list < list_end) { + /* If phandle is 0, then it is an empty entry with + no arguments. */ + phandle = be32_to_cpup(list); + if (phandle) + id = phandle; + else + id = 0; + + if (mask) + mask->enum_ids[count] = id; + if (prio) + prio->enum_ids[count] = id; + if (sense) + sense->enum_ids[count] = id; + + pr_debug("reg: [%d] %d\n", count, id); + list++; + count++; + } + + return ret; +} + +static struct device_node * +__init of_sh_intc_check_base_node(struct device_node *np, + const char *node_name, int *tbl_size) +{ + struct device_node *node; + + node = of_find_node_by_name(np, node_name); + if (!node) { + pr_err("%s table not found\n", node_name); + return NULL; + } + + pr_debug("%s\n", node->full_name); + + *tbl_size = of_get_child_count(node); + + pr_debug("Size of %s: %d\n", node_name, *tbl_size); + + return node; +} + +static int __init of_sh_intc_get_mask_ack(struct device_node *np, + struct intc_mask_reg **masks, int *tbl_size, + const char *base_name, const char *reg_name) +{ + struct device_node *intc_node, *reg_node; + int i, ret; + char node_name[13]; /* intc_mask + 999 */ + + intc_node = of_sh_intc_check_base_node(np, base_name, tbl_size); + if (!intc_node) + return -ENOENT; + + *masks = kzalloc(sizeof(struct intc_mask_reg) * *tbl_size, GFP_KERNEL); + if (!*masks) + return -ENOMEM; + + for (i = 0 ; i < *tbl_size; i++) { + memset(node_name, 0, sizeof(node_name)); + snprintf(node_name, sizeof(node_name), "%s%d", reg_name, i); + + pr_debug("intc node[%d]: name: %s\n", i, node_name); + + reg_node = of_find_node_by_name(intc_node, node_name); + if (!reg_node) { + pr_warn("%s not found\n", node_name); + ret = -EINVAL; + goto error; + } + + ret = of_sh_intc_get_reg_addrs(reg_node, &(*masks)[i].set_reg, + &(*masks)[i].clr_reg, + &(*masks)[i].reg_width, NULL); + if (ret) + goto error; + +#ifdef CONFIG_INTC_BALANCING + of_property_read_u32(reg_node, "dist_reg", + &(*masks)[i].dist_reg); +#endif +#ifdef CONFIG_SMP + of_property_read_u32(reg_node, "smp", + (u32 *)&(*masks)[i].smp); +#endif + + pr_debug("set reg: 0x%lx clr reg: 0x%lx reg_width: %ld\n", + (*masks)[i].set_reg, (*masks)[i].clr_reg, + (*masks)[i].reg_width); + + ret = of_sh_intc_parse_reginfo(reg_node, &(*masks)[i], NULL, + NULL); + if (ret) + goto error; + } + + return ret; + +error: + kfree(*masks); + return ret; +} + +static int __init of_sh_intc_get_vector(struct device_node *np, + struct intc_vect **vectors, int *tbl_size) +{ + struct device_node *intc_node; + + /* Get INTCA vector register info */ + intc_node = of_find_node_by_name(np, "intc_vectors"); + if (!intc_node) { + pr_err("Get INTC vector table not found\n"); + return -ENOENT; + } + + return of_sh_intc_parse_vectortbl(intc_node, vectors, tbl_size); +} + +static int __init of_sh_intc_get_prio(struct device_node *np, + struct intc_prio_reg **prios, int *tbl_size) +{ + struct device_node *intc_node, *reg_node; + int i, ret; + char node_name[13]; /* intc_prio + 999 */ + + intc_node = of_sh_intc_check_base_node(np, "intc_prio_registers", + tbl_size); + if (!intc_node) + return -ENOENT; + + *prios = kzalloc(sizeof(struct intc_prio_reg) * *tbl_size, GFP_KERNEL); + if (!*prios) + return -ENOMEM; + + /* Get INTC priority register info */ + for (i = 0 ; i < *tbl_size; i++) { + memset(node_name, 0, sizeof(node_name)); + snprintf(node_name, sizeof(node_name), "intc_prio%d", i); + + pr_debug("INTC node name: %s\n", node_name); + + reg_node = of_find_node_by_name(intc_node, node_name); + + if (!intc_node) { + pr_err("INTC prio register not found\n"); + ret = -EINVAL; + goto error; + } + + ret = of_sh_intc_get_reg_addrs(reg_node, &(*prios)[i].set_reg, + &(*prios)[i].clr_reg, &(*prios)[i].reg_width, + &(*prios)[i].field_width); + if (ret) + goto error; + + pr_debug("\tset reg: 0x%lx clr reg: 0x%lx\n", + (*prios)[i].set_reg, (*prios)[i].clr_reg); + pr_debug("\treg_width: %ld field_width: %ld\n", + (*prios)[i].reg_width, (*prios)[i].field_width); + + ret = of_sh_intc_parse_reginfo(reg_node, NULL, &(*prios)[i], + NULL); + if (ret) + goto error; + } + + return ret; + +error: + kfree(*prios); + return ret; +} + +static int __init of_sh_intc_get_sense(struct device_node *np, + struct intc_sense_reg **senses, int *tbl_size) +{ + struct device_node *intc_node, *reg_node; + int i, ret; + char node_name[14]; /* intc_sense + 999 */ + + intc_node = of_sh_intc_check_base_node(np, "intc_sense_registers", + tbl_size); + if (!intc_node) + return -ENOENT; + + *senses = kzalloc(sizeof(struct intc_sense_reg) * *tbl_size, + GFP_KERNEL); + if (!*senses) + return -ENOMEM; + + /* Get INTC priority register info */ + for (i = 0 ; i < *tbl_size; i++) { + memset(node_name, 0, sizeof(node_name)); + snprintf(node_name, sizeof(node_name), "intc_sense%d", i); + + pr_debug("INTC node name: %s\n", node_name); + + reg_node = of_find_node_by_name(intc_node, node_name); + + if (!intc_node) { + pr_err("INTC senses register not found\n"); + ret = -EINVAL; + goto error; + } + + ret = of_sh_intc_get_reg_addrs(reg_node, &(*senses)[i].reg, + NULL, &(*senses)[i].reg_width, + &(*senses)[i].field_width); + if (ret) + goto error; + + pr_debug("\tset reg: 0x%lx\n", (*senses)[i].reg); + pr_debug("\treg_width: %ld field_width: %ld\n", + (*senses)[i].reg_width, + (*senses)[i].field_width); + + ret = of_sh_intc_parse_reginfo(reg_node, NULL, NULL, + &(*senses)[i]); + if (ret) + goto error; + } + + return ret; + +error: + kfree(*senses); + return ret; +} + +static int __init of_sh_intc_get_ack(struct device_node *np, + struct intc_mask_reg **masks, int *tbl_size) +{ + return of_sh_intc_get_mask_ack(np, masks, tbl_size, + "intc_ack_registers", "intc_ack"); +} + +static int __init of_sh_intc_get_mask(struct device_node *np, + struct intc_mask_reg **masks, int *tbl_size) +{ + return of_sh_intc_get_mask_ack(np, masks, tbl_size, + "intc_mask_registers", "intc_mask"); +} + +static int __init of_sh_intc_get_group(struct device_node *np, + struct intc_group **groups, int *tbl_size) +{ + struct device_node *node; + int i, ret, size; + const __be32 *list; + struct device_node *grp_node; + char node_name[15]; /* intc_group@999 */ + + node = of_sh_intc_check_base_node(np, "intc_groups", tbl_size); + if (!node || !*tbl_size) + return -ENOENT; + + *groups = kzalloc(sizeof(struct intc_group) * *tbl_size, GFP_KERNEL); + if (!*groups) + return -ENOMEM; + + /* Get INTCA node info */ + for (i = 0 ; i < *tbl_size; i++) { + memset(node_name, 0, sizeof(node_name)); + snprintf(node_name, sizeof(node_name), "intc_group%d", i); + + pr_debug("intc group[%d]: name: %s\n", i, node_name); + + grp_node = of_find_node_by_name(np, node_name); + if (!grp_node) { + pr_warn("%s not found\n", node_name); + ret = -EINVAL; + goto error; + } + + list = of_get_property(np, node_name, &size); + ret = of_sh_intc_parse_group(grp_node, &(*groups)[i]); + if (ret) { + pr_err("intc group not found\n"); + goto error; + } + } + + return ret; + +error: + kfree(*groups); + return ret; +} + +int __init of_sh_intc_get_intevtsa_vect(struct device_node *np, + unsigned short *vect) +{ + int size; + const __be32 *list; + struct device_node *node; + phandle phandle; + + node = of_find_node_by_name(np, "intc_intevtsa"); + if (!node) + return -ENOENT; + + /* Retrieve the phandle list property */ + list = of_get_property(node, "vector", &size); + if (!list) + return -ENOENT; + + phandle = be32_to_cpup(list); + if (phandle) { + uint32_t tmp; + struct device_node *vect_node = + of_find_node_by_phandle(phandle); + + if (!of_sh_intc_parse_vector(vect_node, &tmp)) + *vect = tmp; + else + return -ENOENT; + } else { + pr_debug("intc_intevtsa data not found\n"); + return -ENOENT; + } + return 0; +} + +static int of_sh_intc_get_force_flags(struct device_node *np, + const char *node_name) +{ + int size; + const __be32 *list = of_get_property(np, node_name, &size); + if (list) + return be32_to_cpup(list); + + return 0; +} + +void __init of_sh_intc_get_force_enable(struct device_node *np, + struct intc_desc *d) +{ + d->force_enable = of_sh_intc_get_force_flags(np, "force_enable"); +} + +void __init of_sh_intc_get_force_disable(struct device_node *np, + struct intc_desc *d) +{ + d->force_disable = of_sh_intc_get_force_flags(np, "force_disable"); +} + +void __init of_sh_intc_get_skip_syscore_suspend(struct device_node *np, + struct intc_desc *d) +{ + if (of_find_property(np, "skip_syscore_suspend", NULL)) + d->skip_syscore_suspend = true; + else + d->skip_syscore_suspend = false; +} + +int __init of_sh_intc_get_intc(struct device_node *np, struct intc_desc *d) +{ + int ret = of_sh_intc_get_vector(np, &d->hw.vectors, &d->hw.nr_vectors); + if (ret) + return ret; + + ret = of_sh_intc_get_group(np, &d->hw.groups, &d->hw.nr_groups); + /* INTC may not need groups. */ + if (ret && ret != -ENOENT) + return ret; + + ret = of_sh_intc_get_mask(np, &d->hw.mask_regs, &d->hw.nr_mask_regs); + if (ret) + return ret; + + ret = of_sh_intc_get_prio(np, &d->hw.prio_regs, &d->hw.nr_prio_regs); + if (ret) + return ret; + + ret = of_sh_intc_get_sense(np, &d->hw.sense_regs, &d->hw.nr_sense_regs); + /* INTC may not need Sense register. */ + if (ret && ret != -ENOENT) + return ret; + + ret = of_sh_intc_get_ack(np, &d->hw.ack_regs, &d->hw.nr_ack_regs); + /* INTC may not need Ack register. */ + if (ret && ret != -ENOENT) + return ret; + + d->of_node = np; + + return 0; +} diff --git a/include/linux/sh_intc.h b/include/linux/sh_intc.h index 3238328..c7954ee 100644 --- a/include/linux/sh_intc.h +++ b/include/linux/sh_intc.h @@ -2,6 +2,10 @@ #define __SH_INTC_H #include <linux/ioport.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> +#include <linux/of_address.h> #ifdef CONFIG_SUPERH #define INTC_NR_IRQS 512 @@ -114,6 +118,7 @@ struct intc_desc { intc_enum force_disable; bool skip_syscore_suspend; struct intc_hw_desc hw; + struct device_node *of_node; }; #define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \ @@ -146,4 +151,55 @@ static inline int register_intc_userimask(unsigned long addr) } #endif +/* + * of_sh_initc_get_intc() - Get INTC table. + * @np: device node to get INTC from + * @d: a pointer of intc table + * + * Return: one of the errno value on the error condition + */ +int of_sh_intc_get_intc(struct device_node *np, struct intc_desc *d); + +/* + * of_sh_intc_get_force_enable - Get and set force_enable vector in + * struct intc_desc. + * @np: device node to get INTC from + * @d: a pointer of struct intc_desc + * + * Return: none + */ +void of_sh_intc_get_force_enable(struct device_node *np, + struct intc_desc *d); + +/* + * of_sh_intc_get_force_disable - Get and set force_disable vector in + * struct intc_desc. + * @np: device node to get INTC from + * @d: a pointer of struct intc_desc + * + * Return: none + */ +void of_sh_intc_get_force_disable(struct device_node *np, + struct intc_desc *d); + +/* + * of_sh_intc_get_skip_syscore_suspend - Get and set skip_syscore_suspend + * flag in struct intc_desc. + * @np: device node to get INTC from + * @d: a pointer of struct intc_desc + * + * Return: none + */ +void of_sh_intc_get_skip_syscore_suspend(struct device_node *np, + struct intc_desc *d); + +/* + * of_sh_intc_get_intevtsa_vect - Get using vector by intevtsa + * @np: device node to get INTC from + * @vect:a pointer of value for vector + * + * Return: one of the errno value on the error condition + */ +int of_sh_intc_get_intevtsa_vect(struct device_node *np, unsigned short *vect); + #endif /* __SH_INTC_H */ -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 1/8] SH: intc: Add support OF for INTC 2013-01-09 6:30 ` [PATCH 1/8] SH: intc: Add support OF for INTC Simon Horman @ 2013-01-09 11:53 ` Mark Rutland 2013-01-09 19:11 ` Arnd Bergmann ` (2 more replies) 0 siblings, 3 replies; 17+ messages in thread From: Mark Rutland @ 2013-01-09 11:53 UTC (permalink / raw) To: linux-arm-kernel Hi, Thanks for updating the text, this is far easier to read than previously. However, I'm still concerned by how complex the binding seems. As I don't have any familiarity with the device, I don't know whether that's just an artifact of the hardware or something that can be cleared up. I think the approach used by the binding needs some serious review before this should be merged. It seems far more complex than any existing interrupt controller binding. Without a dts example for a complete board (complete with devices wired up to the interrupt controller), it's difficult to judge how this will work in practice. I've added Arnd to Cc in case he has any thoughts on the matter. On Wed, Jan 09, 2013 at 06:30:00AM +0000, Simon Horman wrote: > From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> > > This provides OF support of SH/INTC. > > The SH/INTC driver is used by SuperH and ARM/SH-MOBILE. > At the moment, SuperH does not have the plan corresponding to DT. > DT of SH/INTC has taken the form where the table data of the C > is managed by DT, in order to maintain compatibility. This doesn't sound good. To me it looks like the C data structures have just been converted to lists in dt, without any thought as to whether or not this is a clean representation of the hardware. > > Cc: Magnus Damm <damm@opensource.se> > Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > > --- > > v9 > * As suggested by Mark Rutland > - Update compatible string to use '-' instead of '_' > - Enhance documentation > - Remove group_size, it can be calculated > - Allow missing traling reg > * Add intc_groups and remove group_size. > The number of groups can be calculated by > containing them in a intc_groups node. > > v8 > * Squash "SH: intc: Add support OF of IRQ" into this patch > * Change patch title from "ARM: shmobile: Add support OF for INTC of shmobile" > to "SH: intc: Add support OF for INTC" > > v7 > * Delete "renesas,sh_intcs" and "renesas,sh_intca_irq_pins" as compatible. > Update their documentation. > * Remove of_sh_intc_get_meminfo() and of_sh_intc_get_pint and > of_sh_intc_get_intc(). They are not used. > > v2 - v6 > * No change > --- > Documentation/devicetree/bindings/sh/intc.txt | 191 ++++++++ > drivers/sh/intc/Makefile | 1 + > drivers/sh/intc/core.c | 2 +- > drivers/sh/intc/internals.h | 3 +- > drivers/sh/intc/irqdomain.c | 6 +- > drivers/sh/intc/of_intc.c | 577 +++++++++++++++++++++++++ > include/linux/sh_intc.h | 56 +++ > 7 files changed, 831 insertions(+), 5 deletions(-) > create mode 100644 Documentation/devicetree/bindings/sh/intc.txt > create mode 100644 drivers/sh/intc/of_intc.c > > diff --git a/Documentation/devicetree/bindings/sh/intc.txt b/Documentation/devicetree/bindings/sh/intc.txt > new file mode 100644 > index 0000000..eb605ce > --- /dev/null > +++ b/Documentation/devicetree/bindings/sh/intc.txt > @@ -0,0 +1,191 @@ > +* Renesas SuperH / SH-MOBILE Interrupt Controller > + > +The SH/INTC driver is used by SuperH and ARM/SH-MOBILE. > +At the moment, SuperH does not have the plan corresponding to DT. > +DT of SH/INTC has taken the form where the table data of the C > +is managed by DT, in order to maintain compatibility. > + > +The main node requires the following properties: > + > +- compatible : "renesas,sh-intc" > + > +- interrupt-controller : Identifies the node as an interrupt controller > +- #interrupt-cells : Must be 1 > +- #address-cells : Must be 1 > +- #size-cells : Must be 1 > +- ranges : Empty as we have a 1-1 mapping to parent's > + address space > +- reg : Specifies base physical address(s) and size of > + the INTC registers > +- intsrc* : Interrupt source > + Associate an interrupt source with its vector > + > +- *_registers : These describe the vector table, mask, priority, ack, > + and sense registers. It must contain the following: > + > + -- intc_vectors : This describes the interrupt sources > + This node requires the following property: > + *vector_table : List of interrupt sources > + > + -- intc_mask_registers : This specifies the contents of the mask registers > + This node requires the following properties: > + * address-cells : Must be 1 > + * size-cells : Must be 1 > + * ranges : Empty as we have a 1-1 mapping to parent's > + address space > + * intc_mask* : A mask register > + This node requires the following properties: > + ** reg : This specifies the address of mask registers. > + The first entry specifies the mask register and > + the second entry specifies the mask clear > + register. The first cell is the register's > + address, and the second cell is the register's size > + which must be 1, 2 or 4 bytes. > + ** reginfo : This specifies the interrupt sources controlled by > + the mask. The list entries correspond to bits of > + the mask from most to least significant. A value > + of 0 may be used for unused bits in the mask. > + Trailing list entries may be omitted in which > + case they will be treated as 0. > + > + -- intc_prio_registers : This sets up the contents of the priority registers > + This node requires the following properties: > + * address-cells : Must be 1 > + * size-cells : Must be 1 > + * ranges : Empty as we have a 1-1 mapping to parent's > + address space > + * intc_prio* : A sense register > + This node requires the following properties: > + ** reg : This specifies the address of the priority register. > + The first entry specifies the priority set > + register and the second entry specifies priority > + clear register. The first cell is the register's > + address, and the second cell is the register's > + size which must be 1, 2 or 4 bytes. If there is > + not priority clear register then they entry may > + be omitted or 0 used as the register's address. > + ** field-width: Width of each group in the register in bits. > + A group contains the priority for a single > + interrupt vector. Thus a 16 bit register with > + a field-width of 4 may control the priority for > + 4 (16 / 4) interrupt sources. > + ** reginfo : This specifies the interrupt sources or interrupt > + source groups controlled by the priority register. > + The list entries correspond to the groups of the > + priority register from least to most significant. > + A value of 0 may be used for unused groups. > + Trailing list entries may be omitted in which > + case they will be treated as 0. > + > + -- intc_sense_registers : This sets up the contents of the sense registers > + This node requires the following properties: > + * address-cells : Must be 1 > + * size-cells : Must be 1 > + * ranges : Empty as we have a 1-1 mapping to parent's > + address space > + * intc_prio* : A sense register > + This node requires the following properties: > + ** reg : This specifies the address of the sense register. > + The first cell is the register's address, and the > + second cell is the register's size which must be > + 1, 2 or 4 bytes. > + ** field-width: Width of each group in the register in bits. > + A group contains the priority for a single > + interrupt vector. Thus a 16 bit register with > + a field-width of 4 may control the priority for > + 4 (16 / 4) interrupt sources. > + ** reginfo : This specifies the interrupt sources controlled by > + the sense register. The list entries correspond > + to the groups of the priority register from least > + to most significant. A value of 0 may be used > + for unused groups. Trailing list entries may be > + omitted in which case they will be treated as 0. > + > + -- intc_ack_registers : This sets up the contents of the ACK registers > + This node requires the following properties: > + * address-cells : Must be 1 > + * size-cells : Must be 1 > + * ranges : Empty as we have a 1-1 mapping to parent's > + address space > + * intc_ack* : An ACK registers > + This node requires the following properties: > + ** reg : This specifies the address of the ACK register. > + The first cell is the register's address, and the > + second cell is the register's size which must be > + 1, 2 or 4 bytes. > + ** reginfo : This specifies the interrupt sources controlled by > + the ACK register. The list entries correspond to > + bits of the ACK register from most to least > + significant. A value of 0 may be used for unused > + bits in the mask. Trailing list entries may be > + omitted in which case they will be treated as 0. > + > +Optional: > + > +- intc_groups : The interrupt source groups > + Interrupt sources may be grouped with a group > + sharing the same bits of an interrupt priority > + register. > + This node requires the following property: > + * intc_group* : An interrupt source group > + This node requires the following property: > + ** group : The list of interrupt sources that > + belong to the group. > + > +- intc_intevtsa : This sets up the contents of INTEVTSA. > + This node requires the following properties: > + * vector : This specifies the interrupt source > + > +Example: > + > + intca: interrupt-controller at 0 { > + compatible = "renesas,sh_intc"; > + interrupt-controller; > + #address-cells = <1>; > + #size-cells = <1>; > + #interrupt-cells = <1>; > + ranges; > + > + reg = <0xe6940000 0x200>, <0xe6950000 0x200>; > + group_size = <19>; > + > + DIRC: intsrc1 { vector = <0x0560>; }; > + ATAPI: intsrc2 { vector = <0x05E0>; }; This looks suspiciously like a way of encoding a device's interrupt information into the interrupt controller's device node. That strikes me as being the wrong way round. > + .... > + > + DMAC1_1: intc_group0 { group = <&DMAC1_1_DEI0 &DMAC1_1_DEI1 > + &DMAC1_1_DEI2 &DMAC1_1_DEI3>; }; > + DMAC1_2: intc_group1 { group = <&DMAC1_2_DEI4 &DMAC1_2_DEI5 > + &DMAC1_2_DADERR>; }; > + .... > + intc_vectors { > + vector_table = <&DIRC &ATAPI &IIC1_ALI &IIC1_TACKI &IIC1_WAITI, > + .... > + }; > + > + intc_mask_registers { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + intc_mask0 { > + reg = <0xe6940080 1>, <0xe69400c0 1>; > + reginfo = <&DMAC2_1_DEI3 &DMAC2_1_DEI2 &DMAC2_1_DEI1 > + &DMAC2_1_DEI0 0 0 &AP_ARM_COMMTX &AP_ARM_COMMRX>; > + }; > + .... > + }; > + > + intc_prio_registers { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + intc_prio0 { > + reg = <0xe6940000 2>; > + field-width = <4>; > + reginfo = <&DMAC3_1 &DMAC3_2 &CMT2 &ICBS0>; > + }; > + .... > + }; > + }; [...] I've not reviewed the code in this patch. I think we should focus on ensuring the binding make sense first; once it's in we're stuck with it. Thanks, Mark. ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/8] SH: intc: Add support OF for INTC 2013-01-09 11:53 ` Mark Rutland @ 2013-01-09 19:11 ` Arnd Bergmann 2013-01-10 1:56 ` Simon Horman 2013-01-10 1:58 ` Simon Horman 2013-01-10 8:42 ` Magnus Damm 2 siblings, 1 reply; 17+ messages in thread From: Arnd Bergmann @ 2013-01-09 19:11 UTC (permalink / raw) To: linux-arm-kernel On Wednesday 09 January 2013, Mark Rutland wrote: > Hi, > > Thanks for updating the text, this is far easier to read than previously. > > However, I'm still concerned by how complex the binding seems. As I don't have > any familiarity with the device, I don't know whether that's just an artifact > of the hardware or something that can be cleared up. > > I think the approach used by the binding needs some serious review before this > should be merged. It seems far more complex than any existing interrupt > controller binding. Without a dts example for a complete board (complete with > devices wired up to the interrupt controller), it's difficult to judge how this > will work in practice. > > I've added Arnd to Cc in case he has any thoughts on the matter. Sorry for having been absent from this discussion for so long. I didn't realize there were 9 versions of this patch set. I tend to agree with your interpretation above, but I may be missing important facts from the previous review rounds. For all I can tell, the binding is an attempt to describe the entire drivers/sh/intc capabilities, which is probably not the best way to approach things. The sh intc driver is not just an irqchip driver, but rather a framework to describe arbitrary irqchips, which is what makes this so hard. When I first looked at the situation last year, I suggested doing a new irqchip driver with a much simpler binding that can only handle the irq chips from shmobile, rather than the whole thing. I am not sure if the binding in the current form is already the "simplified" version, or if it actually implements all the capabilities of the intc driver. > > + intca: interrupt-controller at 0 { > > + compatible = "renesas,sh_intc"; > > + interrupt-controller; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + #interrupt-cells = <1>; > > + ranges; > > + > > + reg = <0xe6940000 0x200>, <0xe6950000 0x200>; > > + group_size = <19>; > > + > > + DIRC: intsrc1 { vector = <0x0560>; }; > > + ATAPI: intsrc2 { vector = <0x05E0>; }; > > This looks suspiciously like a way of encoding a device's interrupt information > into the interrupt controller's device node. That strikes me as being the wrong > way round. Agreed, it would be simpler to have e.g. #interrupt-cells = <4>, to describe the various offsets when needed (I forgot how many are actually required in practice, rather than being computable from the other numbers), and possibly a global interrupt-map/interrupt-map-mask property pair to map this into a flat number space. I need to take some more time to understand the actual requirements again, but IIRC it would be possible to do something much simpler than the proposed binding. Arnd ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/8] SH: intc: Add support OF for INTC 2013-01-09 19:11 ` Arnd Bergmann @ 2013-01-10 1:56 ` Simon Horman 2013-01-17 6:20 ` Simon Horman 0 siblings, 1 reply; 17+ messages in thread From: Simon Horman @ 2013-01-10 1:56 UTC (permalink / raw) To: linux-arm-kernel On Wed, Jan 09, 2013 at 07:11:04PM +0000, Arnd Bergmann wrote: > On Wednesday 09 January 2013, Mark Rutland wrote: > > Hi, > > > > Thanks for updating the text, this is far easier to read than previously. > > > > However, I'm still concerned by how complex the binding seems. As I don't have > > any familiarity with the device, I don't know whether that's just an artifact > > of the hardware or something that can be cleared up. > > > > I think the approach used by the binding needs some serious review before this > > should be merged. It seems far more complex than any existing interrupt > > controller binding. Without a dts example for a complete board (complete with > > devices wired up to the interrupt controller), it's difficult to judge how this > > will work in practice. > > > > I've added Arnd to Cc in case he has any thoughts on the matter. > > Sorry for having been absent from this discussion for so long. I didn't > realize there were 9 versions of this patch set. > > I tend to agree with your interpretation above, but I may be missing > important facts from the previous review rounds. > > For all I can tell, the binding is an attempt to describe the > entire drivers/sh/intc capabilities, which is probably not the > best way to approach things. The sh intc driver is not just an > irqchip driver, but rather a framework to describe arbitrary > irqchips, which is what makes this so hard. > > When I first looked at the situation last year, I suggested doing > a new irqchip driver with a much simpler binding that can only > handle the irq chips from shmobile, rather than the whole thing. > > I am not sure if the binding in the current form is already the > "simplified" version, or if it actually implements all the > capabilities of the intc driver. I think its more on the side of implementing the capabilities of the intc driver than being simplified. Although some effort has gone into this patchset my primary aim is to provide something that provides the basis for supporting the INTC controller on all existing boards. I more than open to concrete ideas of how this can be achieved in agreeable way. > > > + intca: interrupt-controller at 0 { > > > + compatible = "renesas,sh_intc"; > > > + interrupt-controller; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + #interrupt-cells = <1>; > > > + ranges; > > > + > > > + reg = <0xe6940000 0x200>, <0xe6950000 0x200>; > > > + group_size = <19>; > > > + > > > + DIRC: intsrc1 { vector = <0x0560>; }; > > > + ATAPI: intsrc2 { vector = <0x05E0>; }; > > > > This looks suspiciously like a way of encoding a device's interrupt information > > into the interrupt controller's device node. That strikes me as being the wrong > > way round. > > Agreed, it would be simpler to have e.g. #interrupt-cells = <4>, to describe > the various offsets when needed (I forgot how many are actually required > in practice, rather than being computable from the other numbers), and > possibly a global interrupt-map/interrupt-map-mask property pair to map > this into a flat number space. I'm not sure that I see what you are getting at here. > I need to take some more time to understand the actual requirements again, > but IIRC it would be possible to do something much simpler than the > proposed binding. > > Arnd > -- > To unsubscribe from this list: send the line "unsubscribe linux-sh" in > the body of a message to majordomo at vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/8] SH: intc: Add support OF for INTC 2013-01-10 1:56 ` Simon Horman @ 2013-01-17 6:20 ` Simon Horman 0 siblings, 0 replies; 17+ messages in thread From: Simon Horman @ 2013-01-17 6:20 UTC (permalink / raw) To: linux-arm-kernel On Thu, Jan 10, 2013 at 10:56:51AM +0900, Simon Horman wrote: > On Wed, Jan 09, 2013 at 07:11:04PM +0000, Arnd Bergmann wrote: > > On Wednesday 09 January 2013, Mark Rutland wrote: > > > Hi, > > > > > > Thanks for updating the text, this is far easier to read than previously. > > > > > > However, I'm still concerned by how complex the binding seems. As I don't have > > > any familiarity with the device, I don't know whether that's just an artifact > > > of the hardware or something that can be cleared up. > > > > > > I think the approach used by the binding needs some serious review before this > > > should be merged. It seems far more complex than any existing interrupt > > > controller binding. Without a dts example for a complete board (complete with > > > devices wired up to the interrupt controller), it's difficult to judge how this > > > will work in practice. > > > > > > I've added Arnd to Cc in case he has any thoughts on the matter. > > > > Sorry for having been absent from this discussion for so long. I didn't > > realize there were 9 versions of this patch set. > > > > I tend to agree with your interpretation above, but I may be missing > > important facts from the previous review rounds. > > > > For all I can tell, the binding is an attempt to describe the > > entire drivers/sh/intc capabilities, which is probably not the > > best way to approach things. The sh intc driver is not just an > > irqchip driver, but rather a framework to describe arbitrary > > irqchips, which is what makes this so hard. > > > > When I first looked at the situation last year, I suggested doing > > a new irqchip driver with a much simpler binding that can only > > handle the irq chips from shmobile, rather than the whole thing. > > > > I am not sure if the binding in the current form is already the > > "simplified" version, or if it actually implements all the > > capabilities of the intc driver. > > I think its more on the side of implementing the capabilities of > the intc driver than being simplified. > > Although some effort has gone into this patchset my primary > aim is to provide something that provides the basis for supporting > the INTC controller on all existing boards. > > I more than open to concrete ideas of how this can be achieved in agreeable way. > > > > > + intca: interrupt-controller at 0 { > > > > + compatible = "renesas,sh_intc"; > > > > + interrupt-controller; > > > > + #address-cells = <1>; > > > > + #size-cells = <1>; > > > > + #interrupt-cells = <1>; > > > > + ranges; > > > > + > > > > + reg = <0xe6940000 0x200>, <0xe6950000 0x200>; > > > > + group_size = <19>; > > > > + > > > > + DIRC: intsrc1 { vector = <0x0560>; }; > > > > + ATAPI: intsrc2 { vector = <0x05E0>; }; > > > > > > This looks suspiciously like a way of encoding a device's interrupt information > > > into the interrupt controller's device node. That strikes me as being the wrong > > > way round. > > > > Agreed, it would be simpler to have e.g. #interrupt-cells = <4>, to describe > > the various offsets when needed (I forgot how many are actually required > > in practice, rather than being computable from the other numbers), and > > possibly a global interrupt-map/interrupt-map-mask property pair to map > > this into a flat number space. > > I'm not sure that I see what you are getting at here. > > > I need to take some more time to understand the actual requirements again, > > but IIRC it would be possible to do something much simpler than the > > proposed binding. Ping ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/8] SH: intc: Add support OF for INTC 2013-01-09 11:53 ` Mark Rutland 2013-01-09 19:11 ` Arnd Bergmann @ 2013-01-10 1:58 ` Simon Horman 2013-01-10 8:42 ` Magnus Damm 2 siblings, 0 replies; 17+ messages in thread From: Simon Horman @ 2013-01-10 1:58 UTC (permalink / raw) To: linux-arm-kernel On Wed, Jan 09, 2013 at 11:53:52AM +0000, Mark Rutland wrote: > Hi, > > Thanks for updating the text, this is far easier to read than previously. > > However, I'm still concerned by how complex the binding seems. As I don't have > any familiarity with the device, I don't know whether that's just an artifact > of the hardware or something that can be cleared up. The bindings may not be ideal but I believe that the complexity reflects the complexity of the HW. > I think the approach used by the binding needs some serious review before this > should be merged. It seems far more complex than any existing interrupt > controller binding. Without a dts example for a complete board (complete with > devices wired up to the interrupt controller), it's difficult to judge how this > will work in practice. The series includes dtsi files for the sh7372 and r8a7740 SoCs. These illustrate how the bindings may be used to describe the INTCA controller of SoCs. Below is a patch to make use of INTCA on the mackerel board which uses the sh7372 SoC. commit 1e89273655be10a44457d130bcc4a4b0dc4a4956 Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Date: Mon Dec 31 12:23:54 2012 +0100 ARM: shmobile: add a reference DT implementation for mackerel Add a DT-only mackerel implementation. So far it only contains a limited set of devices, already implementing DT support. As more drivers are extended with DT initialisation option, respective devices shall be added to sh7372-mackerel-reference.dts. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e44da40..7fb4696 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -123,7 +123,8 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ r8a7740-armadillo800eva.dtb \ sh73a0-kzm9g.dtb \ - sh7372-mackerel.dtb + sh7372-mackerel.dtb \ + sh7372-mackerel-reference.dtb dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ spear1340-evb.dtb dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ diff --git a/arch/arm/boot/dts/sh7372-mackerel-reference.dts b/arch/arm/boot/dts/sh7372-mackerel-reference.dts new file mode 100644 index 0000000..2fd1eff --- /dev/null +++ b/arch/arm/boot/dts/sh7372-mackerel-reference.dts @@ -0,0 +1,131 @@ +/* + * Device Tree Source for the mackerel board + * + * Copyright (C) 2012 Renesas Solutions Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +/include/ "sh7372.dtsi" + +/ { + model = "Mackerel (AP4 EVM 2nd)"; + compatible = "renesas,mackerel-reference"; + + memory { + device_type = "memory"; + reg = <0x40000000 0x10000000>; + }; + + reg_1p8v: regulator at 0 { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator at 1 { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + lan9220 at 14000000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x14000000 0x2000000>; + phy-mode = "mii"; + interrupt-parent = <&intca_irq_pins_lo>; + interrupts = <0x2c0>; + reg-io-width = <4>; + smsc,irq-push-pull; + smsc,save-mac-address; + vddvario-supply = <®_1p8v>; + vdd33a-supply = <®_3p3v>; + }; + + i2c1: i2c at e6c20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; + reg = <0xe6c20000 0x1000>; + interrupt-parent = <&intca>; + interrupts = <0x780 0x7a0 0x7c0 0x7e0>; + + clock-frequency = <100000>; + + accelerometer at 53 { + compatible = "analog-devices,adxl34x"; + reg = <0x53>; + interrupt-parent = <&intca_irq_pins_hi>; + interrupts = <0x32a0>; + }; + }; + + mmcif0: mmcif at 0xe6bd0000 { + compatible = "renesas,sh-mmcif", "renesas,sh7372-mmcif"; + reg = <0xe6bd0000 0x100>; + interrupt-parent = <&intca>; + interrupts = <0x1ac0 0x1ae0>; + vmmc-supply = <®_1p8v>; + }; + + sdhi0: sdhi at 0xe6850000 { + compatible = "renesas,shmobile-sdhi"; + reg = <0xe6850000 0x100>; + interrupt-parent = <&intca>; + interrupts = <0x0e00 0x0e20 0x0e40>; + vmmc-supply = <®_3p3v>; + }; + + sdhi1: sdhi at 0xe6860000 { + compatible = "renesas,shmobile-sdhi"; + reg = <0xe6860000 0x100>; + interrupt-parent = <&intca>; + interrupts = <0x0e80 0x0ea0 0x0ec0>; + vmmc-supply = <®_1p8v>; + }; + + sdhi2: sdhi at 0xe6870000 { + compatible = "renesas,shmobile-sdhi"; + reg = <0xe6870000 0x100>; + interrupt-parent = <&intca>; + interrupts = <0x1200 0x1220 0x1240>; + vmmc-supply = <®_3p3v>; + }; + + flash at 2000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x20000000 0x8000000>; + bank-width = <2>; + partition at 0 { + label = "loader"; + reg = <0 0x80000>; + }; + partition at 1 { + label = "bootenv"; + reg = <0x80000 0x80000>; + }; + partition at 2 { + label = "kernel_ro"; + reg = <0x100000 0x800000>; + }; + partition at 3 { + label = "kernel"; + reg = <0x900000 0x800000>; + }; + partition at 4 { + label = "data"; + reg = <0x1100000 0x6f00000>; + }; + }; +}; diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 9255546..c25784b 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -76,6 +76,14 @@ config MACH_MACKEREL select SND_SOC_AK4642 if SND_SIMPLE_CARD select USE_OF +config MACH_MACKEREL_REFERENCE + bool "mackerel board - Reference Device Tree Implementation" + depends on ARCH_SH7372 + select ARCH_REQUIRE_GPIOLIB + select REGULATOR_FIXED_VOLTAGE if REGULATOR + select SND_SOC_AK4642 if SND_SIMPLE_CARD + select USE_OF + config MACH_KOTA2 bool "KOTA2 board" depends on ARCH_SH73A0 diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index e1fac57..7723a8f 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o +obj-$(CONFIG_MACH_MACKEREL_REFERENCE) += board-mackerel-reference.o obj-$(CONFIG_MACH_KOTA2) += board-kota2.o obj-$(CONFIG_MACH_BONITO) += board-bonito.o obj-$(CONFIG_MACH_MARZEN) += board-marzen.o diff --git a/arch/arm/mach-shmobile/board-mackerel-reference.c b/arch/arm/mach-shmobile/board-mackerel-reference.c new file mode 100644 index 0000000..1d83653 --- /dev/null +++ b/arch/arm/mach-shmobile/board-mackerel-reference.c @@ -0,0 +1,122 @@ +/* + * mackerel board support - Reference Device Tree Implementation + * + * Copyright (C) 2012 Renesas Solutions Corp. + * + * Copyright (C) 2010 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * + * based on ap4evb + * Copyright (C) 2010 Magnus Damm + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/gpio.h> + +#include <mach/common.h> +#include <mach/irqs.h> +#include <mach/sh7372.h> + +#include <asm/mach/arch.h> + +#define IRQ7 evt2irq(0x02e0) +#define IRQ21 evt2irq(0x32a0) + +static void __init mackerel_init(void) +{ + sh7372_add_standard_devices_dt(); + + /* External clock source */ + clk_set_rate(&sh7372_dv_clki_clk, 27000000); + + sh7372_pinmux_init(); + + /* enable SCIFA0 */ + gpio_request(GPIO_FN_SCIFA0_TXD, NULL); + gpio_request(GPIO_FN_SCIFA0_RXD, NULL); + + /* enable SMSC911X */ + gpio_request(GPIO_FN_CS5A, NULL); + gpio_request(GPIO_FN_IRQ6_39, NULL); + + /* enable Touchscreen */ + gpio_request(GPIO_FN_IRQ7_40, NULL); + irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); + + /* enable Accelerometer */ + gpio_request(GPIO_FN_IRQ21, NULL); + irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); + + /* enable SDHI0 */ + gpio_request(GPIO_FN_SDHIWP0, NULL); + gpio_request(GPIO_FN_SDHICMD0, NULL); + gpio_request(GPIO_FN_SDHICLK0, NULL); + gpio_request(GPIO_FN_SDHID0_3, NULL); + gpio_request(GPIO_FN_SDHID0_2, NULL); + gpio_request(GPIO_FN_SDHID0_1, NULL); + gpio_request(GPIO_FN_SDHID0_0, NULL); + + /* SDHI0 PORT172 card-detect IRQ26 */ + gpio_request(GPIO_FN_IRQ26_172, NULL); + + /* enable SDHI1 */ + gpio_request(GPIO_FN_SDHICMD1, NULL); + gpio_request(GPIO_FN_SDHICLK1, NULL); + gpio_request(GPIO_FN_SDHID1_3, NULL); + gpio_request(GPIO_FN_SDHID1_2, NULL); + gpio_request(GPIO_FN_SDHID1_1, NULL); + gpio_request(GPIO_FN_SDHID1_0, NULL); + + /* enable SDHI2 */ + gpio_request(GPIO_FN_SDHICMD2, NULL); + gpio_request(GPIO_FN_SDHICLK2, NULL); + gpio_request(GPIO_FN_SDHID2_3, NULL); + gpio_request(GPIO_FN_SDHID2_2, NULL); + gpio_request(GPIO_FN_SDHID2_1, NULL); + gpio_request(GPIO_FN_SDHID2_0, NULL); + + /* card detect pin for microSD slot (CN23) */ + gpio_request(GPIO_PORT162, NULL); + gpio_direction_input(GPIO_PORT162); + + /* MMCIF */ + gpio_request(GPIO_FN_MMCD0_0, NULL); + gpio_request(GPIO_FN_MMCD0_1, NULL); + gpio_request(GPIO_FN_MMCD0_2, NULL); + gpio_request(GPIO_FN_MMCD0_3, NULL); + gpio_request(GPIO_FN_MMCD0_4, NULL); + gpio_request(GPIO_FN_MMCD0_5, NULL); + gpio_request(GPIO_FN_MMCD0_6, NULL); + gpio_request(GPIO_FN_MMCD0_7, NULL); + gpio_request(GPIO_FN_MMCCMD0, NULL); + gpio_request(GPIO_FN_MMCCLK0, NULL); +} + +static const char *mackerel_compat_dt[] __initdata = { + "renesas,mackerel-reference", + NULL, +}; + +DT_MACHINE_START(MACKEREL, "mackerel-reference") + .map_io = sh7372_map_io, + .init_early = sh7372_add_early_devices_dt, + .init_irq = sh7372_init_irq_of, + .handle_irq = shmobile_handle_irq_intc, + .init_machine = mackerel_init, + .init_late = sh7372_pm_init_late, + .timer = &shmobile_timer, + .dt_compat = mackerel_compat_dt, +MACHINE_END ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 1/8] SH: intc: Add support OF for INTC 2013-01-09 11:53 ` Mark Rutland 2013-01-09 19:11 ` Arnd Bergmann 2013-01-10 1:58 ` Simon Horman @ 2013-01-10 8:42 ` Magnus Damm 2 siblings, 0 replies; 17+ messages in thread From: Magnus Damm @ 2013-01-10 8:42 UTC (permalink / raw) To: linux-arm-kernel Hi Mark, On Wed, Jan 9, 2013 at 8:53 PM, Mark Rutland <mark.rutland@arm.com> wrote: > Hi, > > Thanks for updating the text, this is far easier to read than previously. > > However, I'm still concerned by how complex the binding seems. As I don't have > any familiarity with the device, I don't know whether that's just an artifact > of the hardware or something that can be cleared up. Iwamatsu-san wrote this binding based on our C version of the INTC tables. And I wrote the original INTC table code based on perhaps 30+ data sheet. They code was initially designed to allow people to input data straight off the data sheet - this so we could support a wide range of slightly different interrupt controllers. > I think the approach used by the binding needs some serious review before this > should be merged. It seems far more complex than any existing interrupt > controller binding. Without a dts example for a complete board (complete with > devices wired up to the interrupt controller), it's difficult to judge how this > will work in practice. Feel free to review the code, but I am not sure why anyone would case about this Renesas specific legacy interrupt controller. If I were to chose how cycles should be spent then I think it is better to try to come up with power domain DT bindings for all SoC vendors. Also, there are the DT board code queued up that makes use of this controller. Thanks, / magnus ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/8] ARM: shmobile: Add support OF of INTC for r8a7740 2013-01-09 6:29 [RFC v9 0/8] ARM: shmobile: DT initialisation of INTC Simon Horman 2013-01-09 6:30 ` [PATCH 1/8] SH: intc: Add support OF for INTC Simon Horman @ 2013-01-09 6:30 ` Simon Horman 2013-01-09 6:30 ` [PATCH 3/8] ARM: shmobile: Add support OF of INTC for sh7372 Simon Horman ` (5 subsequent siblings) 7 siblings, 0 replies; 17+ messages in thread From: Simon Horman @ 2013-01-09 6:30 UTC (permalink / raw) To: linux-arm-kernel From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> This CPU has three interrupt controllers (INTCA and INTCA IRQ pins). This supports these. NOTE: This supports DT of INTCA only. Cc: Magnus Damm <damm@opensource.se> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- v9 * Update compatible string to use '-' instead of '_' --- arch/arm/mach-shmobile/include/mach/common.h | 1 + arch/arm/mach-shmobile/intc-r8a7740.c | 70 +++++++++++++++++++++++--- 2 files changed, 65 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 5f2870e..d0a5790 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -46,6 +46,7 @@ extern struct clk sh73a0_extal2_clk; extern struct clk sh73a0_extcki_clk; extern struct clk sh73a0_extalr_clk; +extern void r8a7740_init_irq_of(void); extern void r8a7740_init_irq(void); extern void r8a7740_map_io(void); extern void r8a7740_add_early_devices(void); diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c index 9a69a31..46dca1f 100644 --- a/arch/arm/mach-shmobile/intc-r8a7740.c +++ b/arch/arm/mach-shmobile/intc-r8a7740.c @@ -1,8 +1,9 @@ /* * R8A7740 processor support * - * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011, 2012 Renesas Solutions Corp. * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu@renesas.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +18,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#define pr_fmt(fmt) "intc: " fmt #include <linux/kernel.h> #include <linux/init.h> @@ -623,15 +625,71 @@ static void intcs_demux(unsigned int irq, struct irq_desc *desc) generic_handle_irq(intcs_evt2irq(evtcodeas)); } -void __init r8a7740_init_irq(void) +static void __init r8a7740_init_intc(resource_size_t intcs0_start, + unsigned short vect) +{ + void __iomem *intevtsa; + + /* demux using INTEVTSA */ + intevtsa = ioremap_nocache(intcs0_start + 0x100, PAGE_SIZE); + irq_set_handler_data(evt2irq(vect), (void *)intevtsa); + irq_set_chained_handler(evt2irq(vect), intcs_demux); +} + +#ifdef CONFIG_OF +static unsigned short intevtsa_vect; + +#define INTC_RES_MAX 2 +static struct { + struct intc_desc intc_desc; + struct resource intc_res[INTC_RES_MAX]; +} intc_data __initdata; + +static int __init intc_of_init(struct device_node *np, + struct device_node *parent) +{ + int ret, i; + + memset(&intc_data, 0, sizeof(intc_data)); + + for (i = 0; i < INTC_RES_MAX; i++) { + ret = of_address_to_resource(np, i, &intc_data.intc_res[i]); + if (ret < 0) + break; + } + + intc_data.intc_desc.name = (char *)of_node_full_name(np); + intc_data.intc_desc.resource = intc_data.intc_res; + intc_data.intc_desc.num_resources = i; + + ret = of_sh_intc_get_intc(np, &intc_data.intc_desc); + if (ret) + return ret; + + of_sh_intc_get_intevtsa_vect(np, &intevtsa_vect); + + register_intc_controller(&intc_data.intc_desc); + return 0; +} + +static const struct of_device_id irq_of_match[] __initconst = { + { .compatible = "renesas,sh-intc", .data = intc_of_init }, + { /*sentinel*/ } +}; + +void __init r8a7740_init_irq_of(void) { - void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); + of_irq_init(irq_of_match); + register_intc_controller(&intcs_desc); +} +#endif /* CONFIG_OF */ + +void __init r8a7740_init_irq(void) +{ register_intc_controller(&intca_desc); register_intc_controller(&intca_irq_pins_desc); register_intc_controller(&intcs_desc); - /* demux using INTEVTSA */ - irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); - irq_set_chained_handler(evt2irq(0xf80), intcs_demux); + r8a7740_init_intc(0xffd20000, 0xf80); } -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 3/8] ARM: shmobile: Add support OF of INTC for sh7372 2013-01-09 6:29 [RFC v9 0/8] ARM: shmobile: DT initialisation of INTC Simon Horman 2013-01-09 6:30 ` [PATCH 1/8] SH: intc: Add support OF for INTC Simon Horman 2013-01-09 6:30 ` [PATCH 2/8] ARM: shmobile: Add support OF of INTC for r8a7740 Simon Horman @ 2013-01-09 6:30 ` Simon Horman 2013-01-09 11:17 ` Mark Rutland 2013-01-09 6:30 ` [PATCH 4/8] ARM: shmobile: Add DT table " Simon Horman ` (4 subsequent siblings) 7 siblings, 1 reply; 17+ messages in thread From: Simon Horman @ 2013-01-09 6:30 UTC (permalink / raw) To: linux-arm-kernel From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> This CPU has four interrupt controllers (INTCA, pins-High and pins-Low). This supports these. Note: This supports DT of INTCA only. Cc: Magnus Damm <damm@opensource.se> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- v9 * Update compatible string to use '-' instead of '_' --- arch/arm/mach-shmobile/include/mach/common.h | 1 + arch/arm/mach-shmobile/intc-sh7372.c | 113 ++++++++++++++++++++------ 2 files changed, 89 insertions(+), 25 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index d0a5790..223250b 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -18,6 +18,7 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index); extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); +extern void sh7372_init_irq_of(void); extern void sh7372_init_irq(void); extern void sh7372_map_io(void); extern void sh7372_add_early_devices(void); diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c index a91caad..bbde18d 100644 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ b/arch/arm/mach-shmobile/intc-sh7372.c @@ -16,6 +16,8 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#define pr_fmt(fmt) "intc: " fmt + #include <linux/kernel.h> #include <linux/init.h> #include <linux/interrupt.h> @@ -551,23 +553,28 @@ static void intcs_demux(unsigned int irq, struct irq_desc *desc) static void __iomem *intcs_ffd2; static void __iomem *intcs_ffd5; - -void __init sh7372_init_irq(void) +static void __iomem *intca_e694; +static void __iomem *intca_e695; + +static void __init sh7372_init_intc(resource_size_t intca0_start, + resource_size_t intca1_start, + resource_size_t intcs0_start, + resource_size_t intcs1_start, + unsigned short vect) { void __iomem *intevtsa; int n; - intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE); - intevtsa = intcs_ffd2 + 0x100; - intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE); + intca_e694 = IOMEM(intca0_start); + intca_e695 = IOMEM(intca1_start); - register_intc_controller(&intca_desc); - register_intc_controller(&intca_irq_pins_lo_desc); - register_intc_controller(&intca_irq_pins_hi_desc); - register_intc_controller(&intcs_desc); + intcs_ffd2 = ioremap_nocache(intcs0_start, PAGE_SIZE); + intevtsa = intcs_ffd2 + 0x100; + intcs_ffd5 = ioremap_nocache(intcs1_start, PAGE_SIZE); /* setup dummy cascade chip for INTCS */ - n = evt2irq(0xf80); + n = evt2irq(vect); + irq_alloc_desc_at(n, numa_node_id()); irq_set_chip_and_handler_name(n, &dummy_irq_chip, handle_level_irq, "level"); @@ -581,6 +588,65 @@ void __init sh7372_init_irq(void) iowrite16(0, intcs_ffd2 + 0x104); } +#ifdef CONFIG_OF +static unsigned short intevtsa_vect; + +#define INTC_RES_MAX 2 +static struct { + struct intc_desc intc_desc; + struct resource intc_res[INTC_RES_MAX]; +} intc_data __initdata; + +static int __init intc_of_init(struct device_node *np, + struct device_node *parent) +{ + int ret, i; + + memset(&intc_data, 0, sizeof(intc_data)); + + for (i = 0; i < INTC_RES_MAX; i++) { + ret = of_address_to_resource(np, i, &intc_data.intc_res[i]); + if (ret < 0) + break; + } + + intc_data.intc_desc.name = (char *)of_node_full_name(np); + intc_data.intc_desc.resource = intc_data.intc_res; + intc_data.intc_desc.num_resources = i; + + ret = of_sh_intc_get_intc(np, &intc_data.intc_desc); + if (ret) + return ret; + + of_sh_intc_get_intevtsa_vect(np, &intevtsa_vect); + + register_intc_controller(&intc_data.intc_desc); + return 0; +} + +static const struct of_device_id irq_of_match[] __initconst = { + { .compatible = "renesas,sh-intc", .data = intc_of_init }, + { /*sentinel*/ } +}; + +void __init sh7372_init_irq_of(void) +{ + of_irq_init(irq_of_match); + + register_intc_controller(&intcs_desc); +} +#endif /* CONFIG_OF */ + +void __init sh7372_init_irq(void) +{ + register_intc_controller(&intca_desc); + register_intc_controller(&intca_irq_pins_lo_desc); + register_intc_controller(&intca_irq_pins_hi_desc); + register_intc_controller(&intcs_desc); + + sh7372_init_intc(0xe6940000, 0xe6950000, 0xffd20000, 0xffd50000, 0xf80); +} + static unsigned short ffd2[0x200]; static unsigned short ffd5[0x100]; @@ -624,9 +690,6 @@ void sh7372_intcs_resume(void) __raw_writeb(ffd5[k], intcs_ffd5 + k); } -#define E694_BASE IOMEM(0xe6940000) -#define E695_BASE IOMEM(0xe6950000) - static unsigned short e694[0x200]; static unsigned short e695[0x200]; @@ -635,22 +698,22 @@ void sh7372_intca_suspend(void) int k; for (k = 0x00; k <= 0x38; k += 4) - e694[k] = __raw_readw(E694_BASE + k); + e694[k] = __raw_readw(intca_e694 + k); for (k = 0x80; k <= 0xb4; k += 4) - e694[k] = __raw_readb(E694_BASE + k); + e694[k] = __raw_readb(intca_e694 + k); for (k = 0x180; k <= 0x1b4; k += 4) - e694[k] = __raw_readb(E694_BASE + k); + e694[k] = __raw_readb(intca_e694 + k); for (k = 0x00; k <= 0x50; k += 4) - e695[k] = __raw_readw(E695_BASE + k); + e695[k] = __raw_readw(intca_e695 + k); for (k = 0x80; k <= 0xa8; k += 4) - e695[k] = __raw_readb(E695_BASE + k); + e695[k] = __raw_readb(intca_e695 + k); for (k = 0x180; k <= 0x1a8; k += 4) - e695[k] = __raw_readb(E695_BASE + k); + e695[k] = __raw_readb(intca_e695 + k); } void sh7372_intca_resume(void) @@ -658,20 +721,20 @@ void sh7372_intca_resume(void) int k; for (k = 0x00; k <= 0x38; k += 4) - __raw_writew(e694[k], E694_BASE + k); + __raw_writew(e694[k], intca_e694 + k); for (k = 0x80; k <= 0xb4; k += 4) - __raw_writeb(e694[k], E694_BASE + k); + __raw_writeb(e694[k], intca_e694 + k); for (k = 0x180; k <= 0x1b4; k += 4) - __raw_writeb(e694[k], E694_BASE + k); + __raw_writeb(e694[k], intca_e694 + k); for (k = 0x00; k <= 0x50; k += 4) - __raw_writew(e695[k], E695_BASE + k); + __raw_writew(e695[k], intca_e695 + k); for (k = 0x80; k <= 0xa8; k += 4) - __raw_writeb(e695[k], E695_BASE + k); + __raw_writeb(e695[k], intca_e695 + k); for (k = 0x180; k <= 0x1a8; k += 4) - __raw_writeb(e695[k], E695_BASE + k); + __raw_writeb(e695[k], intca_e695 + k); } -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 3/8] ARM: shmobile: Add support OF of INTC for sh7372 2013-01-09 6:30 ` [PATCH 3/8] ARM: shmobile: Add support OF of INTC for sh7372 Simon Horman @ 2013-01-09 11:17 ` Mark Rutland 2013-01-10 8:34 ` Magnus Damm 0 siblings, 1 reply; 17+ messages in thread From: Mark Rutland @ 2013-01-09 11:17 UTC (permalink / raw) To: linux-arm-kernel On Wed, Jan 09, 2013 at 06:30:02AM +0000, Simon Horman wrote: > From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> > > This CPU has four interrupt controllers (INTCA, pins-High and pins-Low). > This supports these. > Note: This supports DT of INTCA only. > > Cc: Magnus Damm <damm@opensource.se> > Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > > --- > > v9 > * Update compatible string to use '-' instead of '_' > --- > arch/arm/mach-shmobile/include/mach/common.h | 1 + > arch/arm/mach-shmobile/intc-sh7372.c | 113 ++++++++++++++++++++------ > 2 files changed, 89 insertions(+), 25 deletions(-) > > diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h > index d0a5790..223250b 100644 > --- a/arch/arm/mach-shmobile/include/mach/common.h > +++ b/arch/arm/mach-shmobile/include/mach/common.h > @@ -18,6 +18,7 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev, > struct cpuidle_driver *drv, int index); > extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); > > +extern void sh7372_init_irq_of(void); > extern void sh7372_init_irq(void); > extern void sh7372_map_io(void); > extern void sh7372_add_early_devices(void); > diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c > index a91caad..bbde18d 100644 > --- a/arch/arm/mach-shmobile/intc-sh7372.c > +++ b/arch/arm/mach-shmobile/intc-sh7372.c > @@ -16,6 +16,8 @@ > * along with this program; if not, write to the Free Software > * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > */ > +#define pr_fmt(fmt) "intc: " fmt > + > #include <linux/kernel.h> > #include <linux/init.h> > #include <linux/interrupt.h> > @@ -551,23 +553,28 @@ static void intcs_demux(unsigned int irq, struct irq_desc *desc) > > static void __iomem *intcs_ffd2; > static void __iomem *intcs_ffd5; > - > -void __init sh7372_init_irq(void) > +static void __iomem *intca_e694; > +static void __iomem *intca_e695; > + > +static void __init sh7372_init_intc(resource_size_t intca0_start, > + resource_size_t intca1_start, > + resource_size_t intcs0_start, > + resource_size_t intcs1_start, > + unsigned short vect) > { > void __iomem *intevtsa; > int n; > > - intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE); > - intevtsa = intcs_ffd2 + 0x100; > - intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE); > + intca_e694 = IOMEM(intca0_start); > + intca_e695 = IOMEM(intca1_start); > > - register_intc_controller(&intca_desc); > - register_intc_controller(&intca_irq_pins_lo_desc); > - register_intc_controller(&intca_irq_pins_hi_desc); > - register_intc_controller(&intcs_desc); > + intcs_ffd2 = ioremap_nocache(intcs0_start, PAGE_SIZE); > + intevtsa = intcs_ffd2 + 0x100; > + intcs_ffd5 = ioremap_nocache(intcs1_start, PAGE_SIZE); I think you need to check the return value of ioremap_nocache (it looks like it could return NULL), but I'm not certain of its semantics. > > /* setup dummy cascade chip for INTCS */ > - n = evt2irq(0xf80); > + n = evt2irq(vect); > + > irq_alloc_desc_at(n, numa_node_id()); > irq_set_chip_and_handler_name(n, &dummy_irq_chip, > handle_level_irq, "level"); > @@ -581,6 +588,65 @@ void __init sh7372_init_irq(void) > iowrite16(0, intcs_ffd2 + 0x104); > } > > +#ifdef CONFIG_OF > +static unsigned short intevtsa_vect; > + > +#define INTC_RES_MAX 2 > +static struct { > + struct intc_desc intc_desc; > + struct resource intc_res[INTC_RES_MAX]; > +} intc_data __initdata; > + > +static int __init intc_of_init(struct device_node *np, > + struct device_node *parent) > +{ > + int ret, i; > + > + memset(&intc_data, 0, sizeof(intc_data)); > + > + for (i = 0; i < INTC_RES_MAX; i++) { > + ret = of_address_to_resource(np, i, &intc_data.intc_res[i]); > + if (ret < 0) > + break; > + } > + > + intc_data.intc_desc.name = (char *)of_node_full_name(np); > + intc_data.intc_desc.resource = intc_data.intc_res; > + intc_data.intc_desc.num_resources = i; > + > + ret = of_sh_intc_get_intc(np, &intc_data.intc_desc); > + if (ret) > + return ret; > + > + of_sh_intc_get_intevtsa_vect(np, &intevtsa_vect); > + > + register_intc_controller(&intc_data.intc_desc); > + return 0; > +} You seem to have the same code for r8a7740. They should be consolidated. > + > +static const struct of_device_id irq_of_match[] __initconst = { > + { .compatible = "renesas,sh-intc", .data = intc_of_init }, > + { /*sentinel*/ } > +}; > + > +void __init sh7372_init_irq_of(void) > +{ > + of_irq_init(irq_of_match); > + > + register_intc_controller(&intcs_desc); What if of_irq_init fails? > +} > +#endif /* CONFIG_OF */ > + > +void __init sh7372_init_irq(void) > +{ > + register_intc_controller(&intca_desc); > + register_intc_controller(&intca_irq_pins_lo_desc); > + register_intc_controller(&intca_irq_pins_hi_desc); > + register_intc_controller(&intcs_desc); > + > + sh7372_init_intc(0xe6940000, 0xe6950000, 0xffd20000, 0xffd50000, 0xf80); It might be better if these magic numbers were macro'd out for legibility. > +} > + > static unsigned short ffd2[0x200]; > static unsigned short ffd5[0x100]; > > @@ -624,9 +690,6 @@ void sh7372_intcs_resume(void) > __raw_writeb(ffd5[k], intcs_ffd5 + k); > } > > -#define E694_BASE IOMEM(0xe6940000) > -#define E695_BASE IOMEM(0xe6950000) > - > static unsigned short e694[0x200]; > static unsigned short e695[0x200]; > > @@ -635,22 +698,22 @@ void sh7372_intca_suspend(void) > int k; > > for (k = 0x00; k <= 0x38; k += 4) > - e694[k] = __raw_readw(E694_BASE + k); > + e694[k] = __raw_readw(intca_e694 + k); > > for (k = 0x80; k <= 0xb4; k += 4) > - e694[k] = __raw_readb(E694_BASE + k); > + e694[k] = __raw_readb(intca_e694 + k); > > for (k = 0x180; k <= 0x1b4; k += 4) > - e694[k] = __raw_readb(E694_BASE + k); > + e694[k] = __raw_readb(intca_e694 + k); > > for (k = 0x00; k <= 0x50; k += 4) > - e695[k] = __raw_readw(E695_BASE + k); > + e695[k] = __raw_readw(intca_e695 + k); > > for (k = 0x80; k <= 0xa8; k += 4) > - e695[k] = __raw_readb(E695_BASE + k); > + e695[k] = __raw_readb(intca_e695 + k); > > for (k = 0x180; k <= 0x1a8; k += 4) > - e695[k] = __raw_readb(E695_BASE + k); > + e695[k] = __raw_readb(intca_e695 + k); > } I'm unfamiliar with the hardware, what are these registers being iterated over? How do they correspond to entries in the binding? > > void sh7372_intca_resume(void) > @@ -658,20 +721,20 @@ void sh7372_intca_resume(void) > int k; > > for (k = 0x00; k <= 0x38; k += 4) > - __raw_writew(e694[k], E694_BASE + k); > + __raw_writew(e694[k], intca_e694 + k); > > for (k = 0x80; k <= 0xb4; k += 4) > - __raw_writeb(e694[k], E694_BASE + k); > + __raw_writeb(e694[k], intca_e694 + k); > > for (k = 0x180; k <= 0x1b4; k += 4) > - __raw_writeb(e694[k], E694_BASE + k); > + __raw_writeb(e694[k], intca_e694 + k); > > for (k = 0x00; k <= 0x50; k += 4) > - __raw_writew(e695[k], E695_BASE + k); > + __raw_writew(e695[k], intca_e695 + k); > > for (k = 0x80; k <= 0xa8; k += 4) > - __raw_writeb(e695[k], E695_BASE + k); > + __raw_writeb(e695[k], intca_e695 + k); > > for (k = 0x180; k <= 0x1a8; k += 4) > - __raw_writeb(e695[k], E695_BASE + k); > + __raw_writeb(e695[k], intca_e695 + k); > } > -- > 1.7.10.4 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel at lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > Thanks, Mark. ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/8] ARM: shmobile: Add support OF of INTC for sh7372 2013-01-09 11:17 ` Mark Rutland @ 2013-01-10 8:34 ` Magnus Damm 0 siblings, 0 replies; 17+ messages in thread From: Magnus Damm @ 2013-01-10 8:34 UTC (permalink / raw) To: linux-arm-kernel Hi Mark, Thanks for your feedback! On Wed, Jan 9, 2013 at 8:17 PM, Mark Rutland <mark.rutland@arm.com> wrote: > On Wed, Jan 09, 2013 at 06:30:02AM +0000, Simon Horman wrote: >> From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> >> >> This CPU has four interrupt controllers (INTCA, pins-High and pins-Low). >> This supports these. >> Note: This supports DT of INTCA only. >> >> Cc: Magnus Damm <damm@opensource.se> >> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> >> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> >> >> --- >> >> v9 >> * Update compatible string to use '-' instead of '_' >> --- >> arch/arm/mach-shmobile/include/mach/common.h | 1 + >> arch/arm/mach-shmobile/intc-sh7372.c | 113 ++++++++++++++++++++------ >> 2 files changed, 89 insertions(+), 25 deletions(-) >> >> diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h >> index d0a5790..223250b 100644 >> --- a/arch/arm/mach-shmobile/include/mach/common.h >> +++ b/arch/arm/mach-shmobile/include/mach/common.h >> @@ -18,6 +18,7 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev, >> struct cpuidle_driver *drv, int index); >> extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); >> >> +extern void sh7372_init_irq_of(void); >> extern void sh7372_init_irq(void); >> extern void sh7372_map_io(void); >> extern void sh7372_add_early_devices(void); >> diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c >> index a91caad..bbde18d 100644 >> --- a/arch/arm/mach-shmobile/intc-sh7372.c >> +++ b/arch/arm/mach-shmobile/intc-sh7372.c >> @@ -16,6 +16,8 @@ >> * along with this program; if not, write to the Free Software >> * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA >> */ >> +#define pr_fmt(fmt) "intc: " fmt >> + >> #include <linux/kernel.h> >> #include <linux/init.h> >> #include <linux/interrupt.h> >> @@ -551,23 +553,28 @@ static void intcs_demux(unsigned int irq, struct irq_desc *desc) >> >> static void __iomem *intcs_ffd2; >> static void __iomem *intcs_ffd5; >> - >> -void __init sh7372_init_irq(void) >> +static void __iomem *intca_e694; >> +static void __iomem *intca_e695; >> + >> +static void __init sh7372_init_intc(resource_size_t intca0_start, >> + resource_size_t intca1_start, >> + resource_size_t intcs0_start, >> + resource_size_t intcs1_start, >> + unsigned short vect) >> { >> void __iomem *intevtsa; >> int n; >> >> - intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE); >> - intevtsa = intcs_ffd2 + 0x100; >> - intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE); >> + intca_e694 = IOMEM(intca0_start); >> + intca_e695 = IOMEM(intca1_start); >> >> - register_intc_controller(&intca_desc); >> - register_intc_controller(&intca_irq_pins_lo_desc); >> - register_intc_controller(&intca_irq_pins_hi_desc); >> - register_intc_controller(&intcs_desc); >> + intcs_ffd2 = ioremap_nocache(intcs0_start, PAGE_SIZE); >> + intevtsa = intcs_ffd2 + 0x100; >> + intcs_ffd5 = ioremap_nocache(intcs1_start, PAGE_SIZE); > > I think you need to check the return value of ioremap_nocache (it looks like it > could return NULL), but I'm not certain of its semantics. I guess we could, but I suppose it is somewhat unclear how we shall proceed in the case of failure. But regardless, this is not really changing any logic in the current code. >> >> /* setup dummy cascade chip for INTCS */ >> - n = evt2irq(0xf80); >> + n = evt2irq(vect); >> + >> irq_alloc_desc_at(n, numa_node_id()); >> irq_set_chip_and_handler_name(n, &dummy_irq_chip, >> handle_level_irq, "level"); >> @@ -581,6 +588,65 @@ void __init sh7372_init_irq(void) >> iowrite16(0, intcs_ffd2 + 0x104); >> } >> >> +#ifdef CONFIG_OF >> +static unsigned short intevtsa_vect; >> + >> +#define INTC_RES_MAX 2 >> +static struct { >> + struct intc_desc intc_desc; >> + struct resource intc_res[INTC_RES_MAX]; >> +} intc_data __initdata; >> + >> +static int __init intc_of_init(struct device_node *np, >> + struct device_node *parent) >> +{ >> + int ret, i; >> + >> + memset(&intc_data, 0, sizeof(intc_data)); >> + >> + for (i = 0; i < INTC_RES_MAX; i++) { >> + ret = of_address_to_resource(np, i, &intc_data.intc_res[i]); >> + if (ret < 0) >> + break; >> + } >> + >> + intc_data.intc_desc.name = (char *)of_node_full_name(np); >> + intc_data.intc_desc.resource = intc_data.intc_res; >> + intc_data.intc_desc.num_resources = i; >> + >> + ret = of_sh_intc_get_intc(np, &intc_data.intc_desc); >> + if (ret) >> + return ret; >> + >> + of_sh_intc_get_intevtsa_vect(np, &intevtsa_vect); >> + >> + register_intc_controller(&intc_data.intc_desc); >> + return 0; >> +} > > You seem to have the same code for r8a7740. They should be consolidated. The plan is to consolidate part of this code. There is also a chained interrupt handler that needs a bit more work, so we prefer to figure out how to tie in GIC platforms first then merge code together. >> + >> +static const struct of_device_id irq_of_match[] __initconst = { >> + { .compatible = "renesas,sh-intc", .data = intc_of_init }, >> + { /*sentinel*/ } >> +}; >> + >> +void __init sh7372_init_irq_of(void) >> +{ >> + of_irq_init(irq_of_match); >> + >> + register_intc_controller(&intcs_desc); > > What if of_irq_init fails? Good question. Perhaps Iwamatsu-san can answer that. =) >> +} >> +#endif /* CONFIG_OF */ >> + >> +void __init sh7372_init_irq(void) >> +{ >> + register_intc_controller(&intca_desc); >> + register_intc_controller(&intca_irq_pins_lo_desc); >> + register_intc_controller(&intca_irq_pins_hi_desc); >> + register_intc_controller(&intcs_desc); >> + >> + sh7372_init_intc(0xe6940000, 0xe6950000, 0xffd20000, 0xffd50000, 0xf80); > > It might be better if these magic numbers were macro'd out for legibility. Sure, why not? >> +} >> + >> static unsigned short ffd2[0x200]; >> static unsigned short ffd5[0x100]; >> >> @@ -624,9 +690,6 @@ void sh7372_intcs_resume(void) >> __raw_writeb(ffd5[k], intcs_ffd5 + k); >> } >> >> -#define E694_BASE IOMEM(0xe6940000) >> -#define E695_BASE IOMEM(0xe6950000) >> - >> static unsigned short e694[0x200]; >> static unsigned short e695[0x200]; >> >> @@ -635,22 +698,22 @@ void sh7372_intca_suspend(void) >> int k; >> >> for (k = 0x00; k <= 0x38; k += 4) >> - e694[k] = __raw_readw(E694_BASE + k); >> + e694[k] = __raw_readw(intca_e694 + k); >> >> for (k = 0x80; k <= 0xb4; k += 4) >> - e694[k] = __raw_readb(E694_BASE + k); >> + e694[k] = __raw_readb(intca_e694 + k); >> >> for (k = 0x180; k <= 0x1b4; k += 4) >> - e694[k] = __raw_readb(E694_BASE + k); >> + e694[k] = __raw_readb(intca_e694 + k); >> >> for (k = 0x00; k <= 0x50; k += 4) >> - e695[k] = __raw_readw(E695_BASE + k); >> + e695[k] = __raw_readw(intca_e695 + k); >> >> for (k = 0x80; k <= 0xa8; k += 4) >> - e695[k] = __raw_readb(E695_BASE + k); >> + e695[k] = __raw_readb(intca_e695 + k); >> >> for (k = 0x180; k <= 0x1a8; k += 4) >> - e695[k] = __raw_readb(E695_BASE + k); >> + e695[k] = __raw_readb(intca_e695 + k); >> } > > I'm unfamiliar with the hardware, what are these registers being iterated over? > > How do they correspond to entries in the binding? This is rather crude code to save and restore various registers that will be reset when the power domain is turned off. Ideally we want something more generic, but at this point the code exists and works. Perhaps in the long run we should follow the same style as the GIC. I hope that Iwamatsu-san (the original author) will follow up on this and post an incremental patch to fix things. Thanks, / magnus ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 4/8] ARM: shmobile: Add DT table of INTC for sh7372 2013-01-09 6:29 [RFC v9 0/8] ARM: shmobile: DT initialisation of INTC Simon Horman ` (2 preceding siblings ...) 2013-01-09 6:30 ` [PATCH 3/8] ARM: shmobile: Add support OF of INTC for sh7372 Simon Horman @ 2013-01-09 6:30 ` Simon Horman 2013-01-09 6:30 ` [PATCH 5/8] ARM: shmobile: Add DT table of INTC for r8a7740 Simon Horman ` (3 subsequent siblings) 7 siblings, 0 replies; 17+ messages in thread From: Simon Horman @ 2013-01-09 6:30 UTC (permalink / raw) To: linux-arm-kernel From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Cc: Magnus Damm <damm@opensource.se> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- v9 * Update compatible string to use '-' instead of '_' * Remove group_size and add intc_groups to reflect updated bindings * Remove trailing 0 entries in regs lists, they are not needed. --- arch/arm/boot/dts/sh7372.dtsi | 783 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 783 insertions(+) diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi index 677fc60..582fdec 100644 --- a/arch/arm/boot/dts/sh7372.dtsi +++ b/arch/arm/boot/dts/sh7372.dtsi @@ -18,4 +18,787 @@ compatible = "arm,cortex-a8"; }; }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intca: interrupt-controller at 0 { + compatible = "renesas,sh-intc"; + interrupt-controller; + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + reg = <0xe6940000 0x200>, <0xe6950000 0x200>; + + DIRC: intsrc1 { vector = <0x0560>; }; + CRYPT_STD: intsrc2 { vector = <0x0700>; }; + IIC1_ALI1: intsrc3 { vector = <0x0780>; }; + IIC1_TACKI1:intsrc4 { vector = <0x07a0>; }; + IIC1_WAITI1:intsrc5 { vector = <0x07c0>; }; + IIC1_DTEI1: intsrc6 { vector = <0x07e0>; }; + AP_ARM_IRQPMU: intsrc7 { vector = <0x0800>; }; + AP_ARM_COMMTX: intsrc8 { vector = <0x0840>; }; + AP_ARM_COMMRX: intsrc9 { vector = <0x0860>; }; + MFI_MFIM: intsrc10 { vector = <0x0900>; }; + MFI_MFIS: intsrc11 { vector = <0x0920>; }; + BBIF1: intsrc12 { vector = <0x0940>; }; + BBIF2: intsrc13 { vector = <0x0960>; }; + USBHSDMAC0_USHDMI: intsrc14 { vector = <0x0a00>; }; + _3DG_SGX540: intsrc15 { vector = <0x0a60>; }; + CMT1_CMT10: intsrc16 { vector = <0x0b00>; }; + CMT1_CMT11: intsrc17 { vector = <0x0b20>; }; + CMT1_CMT12: intsrc18 { vector = <0x0b40>; }; + CMT1_CMT13: intsrc19 { vector = <0x0b60>; }; + CMT2: intsrc20 { vector = <0x0b80>; }; + CMT3: intsrc21 { vector = <0x0ba0>; }; + KEYSC_KEY: intsrc22 { vector = <0x0be0>; }; + SCIFA0: intsrc23 { vector = <0x0c00>; }; + SCIFA1: intsrc24 { vector = <0x0c20>; }; + SCIFA2: intsrc25 { vector = <0x0c40>; }; + SCIFA3: intsrc26 { vector = <0x0c60>; }; + MSIOF2: intsrc27 { vector = <0x0c80>; }; + MSIOF1: intsrc28 { vector = <0x0d00>; }; + SCIFA4: intsrc29 { vector = <0x0d20>; }; + SCIFA5: intsrc30 { vector = <0x0d40>; }; + SCIFB: intsrc31 { vector = <0x0d60>; }; + FLCTL_FLSTEI: intsrc32 { vector = <0x0d80>; }; + FLCTL_FLTENDI: intsrc33 { vector = <0x0da0>; }; + FLCTL_FLTREQ0I: intsrc34 { vector = <0x0dc0>; }; + FLCTL_FLTREQ1I: intsrc35 { vector = <0x0de0>; }; + SDHI0_SDHI0I0: intsrc36 { vector = <0x0e00>; }; + SDHI0_SDHI0I1: intsrc37 { vector = <0x0e20>; }; + SDHI0_SDHI0I2: intsrc38 { vector = <0x0e40>; }; + SDHI0_SDHI0I3: intsrc39 { vector = <0x0e60>; }; + SDHI1_SDHI1I0: intsrc40 { vector = <0x0e80>; }; + SDHI1_SDHI1I1: intsrc41 { vector = <0x0ea0>; }; + SDHI1_SDHI1I2: intsrc42 { vector = <0x0ec0>; }; + IRREM: intsrc43 { vector = <0x0f60>; }; + IRDA: intsrc44 { vector = <0x0480>; }; + TPU0: intsrc45 { vector = <0x04a0>; }; + TTI20: intsrc46 { vector = <0x1100>; }; + DDM: intsrc47 { vector = <0x1140>; }; + SDHI2_SDHI2I0: intsrc48 { vector = <0x1200>; }; + SDHI2_SDHI2I1: intsrc49 { vector = <0x1220>; }; + SDHI2_SDHI2I2: intsrc50 { vector = <0x1240>; }; + SDHI2_SDHI2I3: intsrc51 { vector = <0x1260>; }; + RWDT0: intsrc52 { vector = <0x1280>; }; + DMAC1_1_DEI0: intsrc53 { vector = <0x2000>; }; + DMAC1_1_DEI1: intsrc54 { vector = <0x2020>; }; + DMAC1_1_DEI2: intsrc55 { vector = <0x2040>; }; + DMAC1_1_DEI3: intsrc56 { vector = <0x2060>; }; + DMAC1_2_DEI4: intsrc57 { vector = <0x2080>; }; + DMAC1_2_DEI5: intsrc58 { vector = <0x20a0>; }; + DMAC1_2_DADERR: intsrc59 { vector = <0x20c0>; }; + DMAC2_1_DEI0: intsrc60 { vector = <0x2100>; }; + DMAC2_1_DEI1: intsrc61 { vector = <0x2120>; }; + DMAC2_1_DEI2: intsrc62 { vector = <0x2140>; }; + DMAC2_1_DEI3: intsrc63 { vector = <0x2160>; }; + DMAC2_2_DEI4: intsrc64 { vector = <0x2180>; }; + DMAC2_2_DEI5: intsrc65 { vector = <0x21a0>; }; + DMAC2_2_DADERR: intsrc66 { vector = <0x21c0>; }; + DMAC3_1_DEI0: intsrc67 { vector = <0x2200>; }; + DMAC3_1_DEI1: intsrc68 { vector = <0x2220>; }; + DMAC3_1_DEI2: intsrc69 { vector = <0x2240>; }; + DMAC3_1_DEI3: intsrc70 { vector = <0x2260>; }; + DMAC3_2_DEI4: intsrc71 { vector = <0x2280>; }; + DMAC3_2_DEI5: intsrc72 { vector = <0x22a0>; }; + DMAC3_2_DADERR: intsrc73 { vector = <0x22c0>; }; + SHWYSTAT_RT: intsrc74 { vector = <0x1300>; }; + SHWYSTAT_HS: intsrc75 { vector = <0x1320>; }; + SHWYSTAT_COM: intsrc76 { vector = <0x1340>; }; + HDMI: intsrc77 { vector = <0x17e0>; }; + SPU2_SPU0: intsrc78 { vector = <0x1800>; }; + SPU2_SPU1: intsrc79 { vector = <0x1820>; }; + FSI: intsrc80 { vector = <0x1840>; }; + FMSI: intsrc81 { vector = <0x1860>; }; + MIPI_HSI: intsrc82 { vector = <0x18e0>; }; + IPMMU_IPMMUD: intsrc83 { vector = <0x1920>; }; + CEC_1: intsrc84 { vector = <0x1940>; }; + CEC_2: intsrc85 { vector = <0x1960>; }; + AP_ARM_CTIIRQ: intsrc86 { vector = <0x1980>; }; + AP_ARM_DMAEXTERRIRQ: intsrc87 { vector = <0x19a0>; }; + AP_ARM_DMAIRQ: intsrc88 { vector = <0x19c0>; }; + AP_ARM_DMASIRQ: intsrc89 { vector = <0x19e0>; }; + MFIS2: intsrc90 { vector = <0x1a00>; }; + CPORTR2S: intsrc91 { vector = <0x1a20>; }; + CMT14: intsrc92 { vector = <0x1a40>; }; + CMT15: intsrc93 { vector = <0x1a60>; }; + MMC_MMC_ERR: intsrc94 { vector = <0x1ac0>; }; + MMC_MMC_NOR: intsrc95 { vector = <0x1ae0>; }; + IIC4_ALI4: intsrc96 { vector = <0x1b00>; }; + IIC4_TACKI4: intsrc97 { vector = <0x1b20>; }; + IIC4_WAITI4: intsrc98 { vector = <0x1b40>; }; + IIC4_DTEI4: intsrc99 { vector = <0x1b60>; }; + IIC3_ALI3: intsrc100 { vector = <0x1b80>; }; + IIC3_TACKI3: intsrc101 { vector = <0x1ba0>; }; + IIC3_WAITI3: intsrc102 { vector = <0x1bc0>; }; + IIC3_DTEI3: intsrc103 { vector = <0x1be0>; }; + USB0_USB0I1: intsrc104 { vector = <0x1c80>; }; + USB0_USB0I0: intsrc105 { vector = <0x1ca0>; }; + USB1_USB1I1: intsrc106 { vector = <0x1cc0>; }; + USB1_USB1I0: intsrc107 { vector = <0x1ce0>; }; + USBHSDMAC1_USHDMI: intsrc108 { vector = <0x1d00>; }; + + intc_groups { + DMAC1_1: intc_group0 { + group = <&DMAC1_1_DEI0 &DMAC1_1_DEI1 + &DMAC1_1_DEI2 &DMAC1_1_DEI3>; + }; + + DMAC1_2: intc_group1 { + group = <&DMAC1_2_DEI4 &DMAC1_2_DEI5 + &DMAC1_2_DADERR>; + }; + + DMAC2_1: intc_group2 { + group = <&DMAC2_1_DEI0 &DMAC2_1_DEI1 + &DMAC2_1_DEI2 &DMAC2_1_DEI3>; + }; + + DMAC2_2: intc_group3 { + group = <&DMAC2_2_DEI4 &DMAC2_2_DEI5 + &DMAC2_2_DADERR>; + }; + + DMAC3_1: intc_group4 { + group = <&DMAC3_1_DEI0 &DMAC3_1_DEI1 + &DMAC3_1_DEI2 &DMAC3_1_DEI3>; + }; + + DMAC3_2: intc_group5 { + group = <&DMAC3_2_DEI4 &DMAC3_2_DEI5 + &DMAC3_2_DADERR>; + }; + + AP_ARM1: intc_group6 { + group = <&AP_ARM_IRQPMU &AP_ARM_COMMTX + &AP_ARM_COMMRX>; + }; + + AP_ARM2: intc_group7 { + group = <&AP_ARM_CTIIRQ &AP_ARM_DMAEXTERRIRQ + &AP_ARM_DMAIRQ &AP_ARM_DMASIRQ>; + }; + + SPU2: intc_group8 { + group = <&SPU2_SPU0 &SPU2_SPU1>; + }; + + FLCTL: intc_group9 { + group = <&FLCTL_FLSTEI &FLCTL_FLTENDI + &FLCTL_FLTREQ0I &FLCTL_FLTREQ1I>; + }; + + IIC1: intc_group10 { + group = <&IIC1_ALI1 &IIC1_TACKI1 &IIC1_WAITI1 + &IIC1_DTEI1>; + }; + + SDHI0: intc_group11 { + group = <&SDHI0_SDHI0I0 &SDHI0_SDHI0I1 + &SDHI0_SDHI0I2 &SDHI0_SDHI0I3>; + }; + + SDHI1: intc_group12 { + group = <&SDHI1_SDHI1I0 &SDHI1_SDHI1I1 + &SDHI1_SDHI1I2>; + }; + + SDHI2: intc_group13 { + group = <&SDHI2_SDHI2I0 &SDHI2_SDHI2I1 + &SDHI2_SDHI2I2 &SDHI2_SDHI2I3>; + }; + + SHWYSTAT: intc_group14 { + group = <&SHWYSTAT_RT &SHWYSTAT_HS &SHWYSTAT_COM>; + }; + }; + + intc_vectors { + vector_table = <&DIRC &CRYPT_STD + &IIC1_ALI1 &IIC1_TACKI1 &IIC1_WAITI1 &IIC1_DTEI1 + &AP_ARM_IRQPMU &AP_ARM_COMMTX &AP_ARM_COMMRX + &MFI_MFIM &MFI_MFIS &BBIF1 &BBIF2 + &USBHSDMAC0_USHDMI + &_3DG_SGX540 + &CMT1_CMT10 &CMT1_CMT11 &CMT1_CMT12 + &CMT1_CMT13 &CMT2 &CMT3 + &KEYSC_KEY + &SCIFA0 &SCIFA1 &SCIFA2 &SCIFA3 + &MSIOF2 &MSIOF1 + &SCIFA4 &SCIFA5 &SCIFB + &FLCTL_FLSTEI &FLCTL_FLTENDI &FLCTL_FLTREQ0I + &FLCTL_FLTREQ1I + &SDHI0_SDHI0I0 &SDHI0_SDHI0I1 &SDHI0_SDHI0I2 + &SDHI0_SDHI0I3 + &SDHI1_SDHI1I0 &SDHI1_SDHI1I1 &SDHI1_SDHI1I2 + &IRREM &IRDA &TPU0 &TTI20 &DDM + &SDHI2_SDHI2I0 &SDHI2_SDHI2I1 &SDHI2_SDHI2I2 + &SDHI2_SDHI2I3 + &RWDT0 + &DMAC1_1_DEI0 &DMAC1_1_DEI1 &DMAC1_1_DEI2 + &DMAC1_1_DEI3 + &DMAC1_2_DEI4 &DMAC1_2_DEI5 &DMAC1_2_DADERR + &DMAC2_1_DEI0 &DMAC2_1_DEI1 &DMAC2_1_DEI2 + &DMAC2_1_DEI3 + &DMAC2_2_DEI4 &DMAC2_2_DEI5 &DMAC2_2_DADERR + &DMAC3_1_DEI0 &DMAC3_1_DEI1 &DMAC3_1_DEI2 + &DMAC3_1_DEI3 + &DMAC3_2_DEI4 &DMAC3_2_DEI5 &DMAC3_2_DADERR + &SHWYSTAT_RT &SHWYSTAT_HS &SHWYSTAT_COM + &HDMI + &SPU2_SPU0 &SPU2_SPU1 + &FSI &FMSI + &MIPI_HSI + &IPMMU_IPMMUD + &CEC_1 &CEC_2 + &AP_ARM_CTIIRQ &AP_ARM_DMAEXTERRIRQ &AP_ARM_DMAIRQ + &AP_ARM_DMASIRQ + &MFIS2 + &CPORTR2S + &CMT14 &CMT15 + &MMC_MMC_ERR &MMC_MMC_NOR + &IIC4_ALI4 &IIC4_TACKI4 &IIC4_WAITI4 &IIC4_DTEI4 + &IIC3_ALI3 &IIC3_TACKI3 &IIC3_WAITI3 &IIC3_DTEI3 + &USB0_USB0I1 &USB0_USB0I0 + &USB1_USB1I1 &USB1_USB1I0 + &USBHSDMAC1_USHDMI>; + }; + + intc_mask_registers { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc_mask0 { + reg = <0xe6940080 1>, <0xe69400c0 1>; + reginfo = <&DMAC2_1_DEI3 &DMAC2_1_DEI2 &DMAC2_1_DEI1 + &DMAC2_1_DEI0 &AP_ARM_IRQPMU 0 &AP_ARM_COMMTX + &AP_ARM_COMMRX>; + }; + + intc_mask1 { + reg = <0xe6940084 1>, <0xe69400c4 1>; + reginfo = <0 &CRYPT_STD &DIRC 0 &DMAC1_1_DEI3 &DMAC1_1_DEI2 + &DMAC1_1_DEI1 &DMAC1_1_DEI0>; + }; + + intc_mask2 { + reg = <0xe6940088 1>, <0xe69400c8 1>; + reginfo = <0 0 0 0 &BBIF1 &BBIF2 &MFI_MFIS &MFI_MFIM>; + }; + + intc_mask3 { + reg = <0xe694008c 1>, <0xe69400cc 1>; + reginfo = <&DMAC3_1_DEI3 &DMAC3_1_DEI2 &DMAC3_1_DEI1 + &DMAC3_1_DEI0 &DMAC3_2_DADERR &DMAC3_2_DEI5 + &DMAC3_2_DEI4 &IRDA>; + }; + + intc_mask4 { + reg = <0xe6940090 1>, <0xe69400d0 1>; + reginfo = <&DDM>; + }; + + intc_mask5 { + reg = <0xe6940094 1>, <0xe69400d4 1>; + reginfo = <&KEYSC_KEY &DMAC1_2_DADERR &DMAC1_2_DEI5 + &DMAC1_2_DEI4 &SCIFA3 &SCIFA2 &SCIFA1 &SCIFA0>; + }; + + intc_mask6 { + reg = <0xe6940098 1>, <0xe69400d8 1>; + reginfo = <&SCIFB &SCIFA5 &SCIFA4 &MSIOF1 0 0 &MSIOF2>; + }; + + intc_mask7 { + reg = <0xe694009c 1>, <0xe69400dc 1>; + reginfo = <&SDHI0_SDHI0I3 &SDHI0_SDHI0I2 &SDHI0_SDHI0I1 + &SDHI0_SDHI0I0 &FLCTL_FLTREQ1I &FLCTL_FLTREQ0I + &FLCTL_FLTENDI &FLCTL_FLSTEI>; + }; + + intc_mask8 { + reg = <0xe69400a0 1>, <0xe69400e0 1>; + reginfo = <0 &SDHI1_SDHI1I2 &SDHI1_SDHI1I1 &SDHI1_SDHI1I0 + &TTI20 &USBHSDMAC0_USHDMI>; + }; + + intc_mask9 { + reg = <0xe69400a4 1>, <0xe69400e4 1>; + reginfo = <&CMT1_CMT13 &CMT1_CMT12 &CMT1_CMT11 &CMT1_CMT10 + &CMT2 0 0 &_3DG_SGX540>; + }; + + intc_mask10 { + reg = <0xe69400a8 1>, <0xe69400e8 1>; + reginfo = <0 &DMAC2_2_DADERR &DMAC2_2_DEI5 &DMAC2_2_DEI4>; + }; + + intc_mask11 { + reg = <0xe69400ac 1>, <0xe69400ec 1>; + reginfo = <&IIC1_DTEI1 &IIC1_WAITI1 &IIC1_TACKI1 + &IIC1_ALI1 0 0 &IRREM>; + }; + + intc_mask12 { + reg = <0xe69400b0 1>, <0xe69400f0 1>; + reginfo = <0 0 &TPU0>; + }; + + intc_mask13 { + reg = <0xe69400b4 1>, <0xe69400f4 1>; + reginfo = <&SDHI2_SDHI2I3 &SDHI2_SDHI2I2 &SDHI2_SDHI2I1 + &SDHI2_SDHI2I0 0 &CMT3 0 &RWDT0>; + }; + + intc_mask14 { + reg = <0xe6950080 1>, <0xe69500c0 1>; + reginfo = <&SHWYSTAT_RT &SHWYSTAT_HS &SHWYSTAT_COM>; + }; + + intc_mask15 { + reg = <0xe6950090 1>, <0xe69500d0 1>; + reginfo = <0 0 0 0 0 0 0 &HDMI>; + }; + + intc_mask16 { + reg = <0xe6950094 1>, <0xe69500d4 1>; + reginfo = <&SPU2_SPU0 &SPU2_SPU1 &FSI &FMSI + 0 0 0 &MIPI_HSI>; + }; + + intc_mask17 { + reg = <0xe6950098 1>, <0xe69500d8 1>; + reginfo = <0 &IPMMU_IPMMUD &CEC_1 &CEC_2 + &AP_ARM_CTIIRQ &AP_ARM_DMAEXTERRIRQ + &AP_ARM_DMAIRQ &AP_ARM_DMASIRQ>; + }; + + intc_mask18 { + reg = <0xe695009c 1>, <0xe69500dc 1>; + reginfo = <&MFIS2 &CPORTR2S &CMT14 &CMT15 + 0 0 &MMC_MMC_ERR &MMC_MMC_NOR>; + }; + + intc_mask19 { + reg = <0xe69500a0 1>, <0xe69500e0 1>; + reginfo = <&IIC4_ALI4 &IIC4_TACKI4 &IIC4_WAITI4 + &IIC4_DTEI4 &IIC3_ALI3 &IIC3_TACKI3 + &IIC3_WAITI3 &IIC3_DTEI3>; + }; + + intc_mask20 { + reg = <0xe69500a4 1>, <0xe69500e4 1>; + reginfo = <0 0 0 0 &USB0_USB0I1 &USB0_USB0I0 + &USB1_USB1I1 &USB1_USB1I0>; + }; + + intc_mask21 { + reg = <0xe69500a8 1>, <0xe69500e8 1>; + reginfo = <&USBHSDMAC1_USHDMI>; + }; + }; + + intc_prio_registers { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc_prio0 { + reg = <0xe6940000 2>; + field-width = <4>; + reginfo = <&DMAC3_1 &DMAC3_2 &CMT2>; + }; + + intc_prio1 { + reg = <0xe6940004 2>; + field-width = <4>; + reginfo = <&IRDA 0 &BBIF1 &BBIF2>; + }; + + intc_prio2 { + reg = <0xe6940008 2>; + field-width = <4>; + reginfo = <0 &CRYPT_STD &CMT1_CMT11 &AP_ARM1>; + }; + + intc_prio3 { + reg = <0xe694000c 2>; + field-width = <4>; + reginfo = <0 0 &CMT1_CMT12>; + }; + + intc_prio4 { + reg = <0xe6940010 2>; + field-width = <4>; + reginfo = <&DMAC1_1 &MFI_MFIS &MFI_MFIM>; + }; + + intc_prio5 { + reg = <0xe6940014 2>; + field-width = <4>; + reginfo = <&KEYSC_KEY &DMAC1_2 &_3DG_SGX540 &CMT1_CMT10>; + }; + + intc_prio6 { + reg = <0xe6940018 2>; + field-width = <4>; + reginfo = <&SCIFA0 &SCIFA1 &SCIFA2 &SCIFA3>; + }; + + intc_prio7 { + reg = <0xe694001c 2>; + field-width = <4>; + reginfo = <&MSIOF2 &USBHSDMAC0_USHDMI &FLCTL &SDHI0>; + }; + + intc_prio8 { + reg = <0xe6940020 2>; + field-width = <4>; + reginfo = <&MSIOF1 &SCIFA4 0 &IIC1>; + }; + + intc_prio9 { + reg = <0xe6940024 2>; + field-width = <4>; + reginfo = <&DMAC2_1 &DMAC2_2 0 &TTI20>; + }; + + intc_prio10 { + reg = <0xe6940028 2>; + field-width = <4>; + reginfo = <0 &CMT1_CMT13 &IRREM &SDHI1>; + }; + + intc_prio11 { + reg = <0xe694002c 2>; + field-width = <4>; + reginfo = <&TPU0>; + }; + + intc_prio12 { + reg = <0xe6940030 2>; + field-width = <4>; + reginfo = <0 &CMT3 0 &RWDT0>; + }; + + intc_prio13 { + reg = <0xe6940034 2>; + field-width = <4>; + reginfo = <&SCIFB &SCIFA5 0 &DDM>; + }; + + intc_prio14 { + reg = <0xe6940038 2>; + field-width = <4>; + reginfo = <0 0 &DIRC &SDHI2>; + }; + + intc_prio15 { + reg = <0xe6950000 2>; + field-width = <4>; + reginfo = <&SHWYSTAT>; + }; + + intc_prio16 { + reg = <0xe6950024 2>; + field-width = <4>; + reginfo = <0 0 0 &HDMI>; + }; + + intc_prio17 { + reg = <0xe6950028 2>; + field-width = <4>; + reginfo = <&SPU2 0 &FSI &FMSI>; + }; + + intc_prio18 { + reg = <0xe695002c 2>; + field-width = <4>; + reginfo = <0 0 0 &MIPI_HSI>; + }; + + intc_prio19 { + reg = <0xe6950030 2>; + field-width = <4>; + reginfo = <&IPMMU_IPMMUD 0 &CEC_1 &CEC_2>; + }; + + intc_prio20 { + reg = <0xe6950034 2>; + field-width = <4>; + reginfo = <&AP_ARM2>; + }; + + intc_prio21 { + reg = <0xe6950038 2>; + field-width = <4>; + reginfo = <&MFIS2 &CPORTR2S &CMT14 &CMT15>; + }; + + intc_prio22 { + reg = <0xe695003c 2>; + field-width = <4>; + reginfo = <0 0 &MMC_MMC_ERR &MMC_MMC_NOR>; + }; + + intc_prio23 { + reg = <0xe6950040 2>; + field-width = <4>; + reginfo = <&IIC4_ALI4 &IIC4_TACKI4 &IIC4_WAITI4 &IIC4_DTEI4>; + }; + + intc_prio24 { + reg = <0xe6950044 2>; + field-width = <4>; + reginfo = <&IIC3_ALI3 &IIC3_TACKI3 &IIC3_WAITI3 &IIC3_DTEI3>; + }; + + intc_prio25 { + reg = <0xe6950048 2>; + field-width = <4>; + reginfo = <>; + }; + + intc_prio26 { + reg = <0xe695004c 2>; + field-width = <4>; + reginfo = <&USB0_USB0I1 &USB0_USB0I0 &USB1_USB1I1 &USB1_USB1I0>; + }; + + intc_prio27 { + reg = <0xe6950050 2>; + field-width = <4>; + reginfo = <&USBHSDMAC1_USHDMI>; + }; + + }; + }; + + intca_irq_pins_lo: interrupt-controller at 1 { + compatible = "renesas,sh-intc"; + interrupt-controller; + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + reg = <0xe6900000 0x70>; + + IRQ0: intsrc1 { vector = <0x200>; }; + IRQ1: intsrc2 { vector = <0x220>; }; + IRQ2: intsrc3 { vector = <0x240>; }; + IRQ3: intsrc4 { vector = <0x260>; }; + IRQ4: intsrc5 { vector = <0x280>; }; + IRQ5: intsrc6 { vector = <0x2a0>; }; + IRQ6: intsrc7 { vector = <0x2c0>; }; + IRQ7: intsrc8 { vector = <0x2e0>; }; + IRQ8: intsrc9 { vector = <0x300>; }; + IRQ9: intsrc10 { vector = <0x320>; }; + IRQ10: intsrc11 { vector = <0x340>; }; + IRQ11: intsrc12 { vector = <0x360>; }; + IRQ12: intsrc13 { vector = <0x380>; }; + IRQ13: intsrc14 { vector = <0x3a0>; }; + IRQ14: intsrc15 { vector = <0x3c0>; }; + IRQ15: intsrc16 { vector = <0x3e0>; }; + + intc_vectors { + vector_table = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4 &IRQ5 + &IRQ6 &IRQ7 &IRQ8 &IRQ9 &IRQ10 + &IRQ11 &IRQ12 &IRQ13 &IRQ14 &IRQ15>; + }; + + intc_mask_registers { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc_mask0 { + reg = <0xe6900040 1>, <0xe6900060 1>; + reginfo = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4 + &IRQ5 &IRQ6 &IRQ7>; + }; + + intc_mask1 { + reg = <0xe6900044 1>, <0xe6900064 1>; + reginfo = <&IRQ8 &IRQ9 &IRQ10 &IRQ11 + &IRQ12 &IRQ13 &IRQ14 &IRQ15>; + }; + }; + + intc_prio_registers { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc_prio0 { + reg = <0xe6900010 4>; + field-width = <4>; + reginfo = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4 + &IRQ5 &IRQ6 &IRQ7>; + }; + + intc_prio1 { + reg = <0xe6900014 4>; + field-width = <4>; + reginfo = <&IRQ8 &IRQ9 &IRQ10 &IRQ11 + &IRQ12 &IRQ13 &IRQ14 &IRQ15>; + }; + }; + + intc_sense_registers { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc_sense0 { + reg = <0xe6900000 4>; + field-width = <4>; + reginfo = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4 + &IRQ5 &IRQ6 &IRQ7>; + }; + + intc_sense1 { + reg = <0xe6900004 4>; + field-width = <4>; + reginfo = <&IRQ8 &IRQ9 &IRQ10 &IRQ11 + &IRQ12 &IRQ13 &IRQ14 &IRQ15>; + }; + }; + + intc_ack_registers { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc_ack0 { + reg = <0xe6900020 1>; + reginfo = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4 + &IRQ5 &IRQ6 &IRQ7>; + }; + + intc_ack1 { + reg = <0xe6900024 1>; + reginfo = <&IRQ8 &IRQ9 &IRQ10 &IRQ11 + &IRQ12 &IRQ13 &IRQ14 &IRQ15>; + }; + }; + }; + + intca_irq_pins_hi: interrupt-controller at 2 { + compatible = "renesas,sh-intc"; + interrupt-controller; + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + reg = <0xe6900008 0x70>; + + IRQ16: intsrc1 { vector = <0x3200>; }; + IRQ17: intsrc2 { vector = <0x3220>; }; + IRQ18: intsrc3 { vector = <0x3240>; }; + IRQ19: intsrc4 { vector = <0x3260>; }; + IRQ20: intsrc5 { vector = <0x3280>; }; + IRQ21: intsrc6 { vector = <0x32a0>; }; + IRQ22: intsrc7 { vector = <0x32c0>; }; + IRQ23: intsrc8 { vector = <0x32e0>; }; + IRQ24: intsrc9 { vector = <0x3300>; }; + IRQ25: intsrc10 { vector = <0x3320>; }; + IRQ26: intsrc11 { vector = <0x3340>; }; + IRQ27: intsrc12 { vector = <0x3360>; }; + IRQ28: intsrc13 { vector = <0x3380>; }; + IRQ29: intsrc14 { vector = <0x33a0>; }; + IRQ30: intsrc15 { vector = <0x33c0>; }; + IRQ31: intsrc16 { vector = <0x33e0>; }; + + intc_vectors { + vector_table = <&IRQ16 &IRQ17 &IRQ18 &IRQ19 &IRQ20 &IRQ21 + &IRQ22 &IRQ23 &IRQ24 &IRQ25 &IRQ26 + &IRQ27 &IRQ28 &IRQ29 &IRQ30 &IRQ31>; + }; + + intc_mask_registers { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc_mask0 { + reg = <0xe6900048 1>, <0xe6900068 1>; + reginfo = <&IRQ16 &IRQ17 &IRQ18 &IRQ19 &IRQ20 + &IRQ21 &IRQ22 &IRQ23>; + }; + + intc_mask1 { + reg = <0xe690004c 1>, <0xe690006c 1>; + reginfo = <&IRQ24 &IRQ25 &IRQ26 &IRQ27 + &IRQ28 &IRQ29 &IRQ30 &IRQ31>; + }; + }; + + intc_prio_registers { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc_prio0 { + reg = <0xe6900018 4>; + field-width = <4>; + reginfo = <&IRQ16 &IRQ17 &IRQ18 &IRQ19 &IRQ20 + &IRQ21 &IRQ22 &IRQ23>; + }; + + intc_prio1 { + reg = <0xe690001c 4>; + field-width = <4>; + reginfo = <&IRQ24 &IRQ25 &IRQ26 &IRQ27 + &IRQ28 &IRQ29 &IRQ30 &IRQ31>; + }; + }; + + intc_sense_registers { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc_sense0 { + reg = <0xe6900008 4>; + field-width = <4>; + reginfo = <&IRQ16 &IRQ17 &IRQ18 &IRQ19 &IRQ20 + &IRQ21 &IRQ22 &IRQ23>; + }; + + intc_sense1 { + reg = <0xe690000c 4>; + field-width = <4>; + reginfo = <&IRQ24 &IRQ25 &IRQ26 &IRQ27 + &IRQ28 &IRQ29 &IRQ30 &IRQ31>; + }; + }; + + intc_ack_registers { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc_ack0 { + reg = <0xe6900028 1>; + reginfo = <&IRQ16 &IRQ17 &IRQ18 &IRQ19 &IRQ20 + &IRQ21 &IRQ22 &IRQ23>; + }; + + intc_ack1 { + reg = <0xe690002c 1>; + reginfo = <&IRQ24 &IRQ25 &IRQ26 &IRQ27 + &IRQ28 &IRQ29 &IRQ30 &IRQ31>; + }; + }; + }; + }; }; -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 5/8] ARM: shmobile: Add DT table of INTC for r8a7740 2013-01-09 6:29 [RFC v9 0/8] ARM: shmobile: DT initialisation of INTC Simon Horman ` (3 preceding siblings ...) 2013-01-09 6:30 ` [PATCH 4/8] ARM: shmobile: Add DT table " Simon Horman @ 2013-01-09 6:30 ` Simon Horman 2013-01-09 6:30 ` [PATCH 6/8] ARM: shmobile: r8a7740: Use DT initialisation of INTC Simon Horman ` (2 subsequent siblings) 7 siblings, 0 replies; 17+ messages in thread From: Simon Horman @ 2013-01-09 6:30 UTC (permalink / raw) To: linux-arm-kernel From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Cc: Magnus Damm <damm@opensource.se> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- v9 * Update compatible string to use '-' instead of '_' * Remove group_size and add intc_groups to reflect updated bindings * Remove trailing 0 entries in regs lists, they are not needed. --- arch/arm/boot/dts/r8a7740.dtsi | 743 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 742 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 2418278..9efc4f3 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -1,5 +1,5 @@ /* - * Device Tree Source for the r8a7740 SoC + * Device Tree Source for Renesas r8a7740 * * Copyright (C) 2012 Renesas Solutions Corp. * @@ -25,4 +25,745 @@ <0xe605800c 0x20>; #gpio-cells = <2>; }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intca: interrupt-controller at 0 { + compatible = "renesas,sh-intc"; + interrupt-controller; + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + reg = <0xe6940000 0x200>, <0xe6950000 0x200>; + + DIRC: intsrc1 { vector = <0x0560>; }; + ATAPI: intsrc2 { vector = <0x05E0>; }; + IIC1_ALI: intsrc3 { vector = <0x0780>; }; + IIC1_TACKI: intsrc4 { vector = <0x07A0>; }; + IIC1_WAITI: intsrc5 { vector = <0x07C0>; }; + IIC1_DTEI: intsrc6 { vector = <0x07E0>; }; + AP_ARM_COMMTX: intsrc7 { vector = <0x0840>; }; + AP_ARM_COMMRX: intsrc8 { vector = <0x0860>; }; + MFI: intsrc9 { vector = <0x0900>; }; + MFIS: intsrc10 { vector = <0x0920>; }; + BBIF1: intsrc11 { vector = <0x0940>; }; + BBIF2: intsrc12 { vector = <0x0960>; }; + USBHSDMAC: intsrc13 { vector = <0x0A00>; }; + USBF_OUL_SOF: intsrc14 { vector = <0x0A20>; }; + USBF_IXL_INT: intsrc15 { vector = <0x0A40>; }; + SGX540: intsrc16 { vector = <0x0A60>; }; + CMT1_0: intsrc17 { vector = <0x0B00>; }; + CMT1_1: intsrc18 { vector = <0x0B20>; }; + CMT1_2: intsrc19 { vector = <0x0B40>; }; + CMT1_3: intsrc20 { vector = <0x0B60>; }; + CMT2: intsrc21 { vector = <0x0B80>; }; + CMT3: intsrc22 { vector = <0x0BA0>; }; + KEYSC: intsrc23 { vector = <0x0BE0>; }; + SCIFA0: intsrc24 { vector = <0x0C00>; }; + SCIFA1: intsrc25 { vector = <0x0C20>; }; + SCIFA2: intsrc26 { vector = <0x0C40>; }; + SCIFA3: intsrc27 { vector = <0x0C60>; }; + MSIOF2: intsrc28 { vector = <0x0C80>; }; + MSIOF1: intsrc29 { vector = <0x0D00>; }; + SCIFA4: intsrc30 { vector = <0x0D20>; }; + SCIFA5: intsrc31 { vector = <0x0D40>; }; + SCIFB: intsrc32 { vector = <0x0D60>; }; + FLCTL_FLSTEI: intsrc33 { vector = <0x0D80>; }; + FLCTL_FLTENDI: intsrc34 { vector = <0x0DA0>; }; + FLCTL_FLTREQ0I: intsrc35 { vector = <0x0DC0>; }; + FLCTL_FLTREQ1I: intsrc36 { vector = <0x0DE0>; }; + SDHI0_0: intsrc37 { vector = <0x0E00>; }; + SDHI0_1: intsrc38 { vector = <0x0E20>; }; + SDHI0_2: intsrc39 { vector = <0x0E40>; }; + SDHI0_3: intsrc40 { vector = <0x0E60>; }; + SDHI1_0: intsrc41 { vector = <0x0E80>; }; + SDHI1_1: intsrc42 { vector = <0x0EA0>; }; + SDHI1_2: intsrc43 { vector = <0x0EC0>; }; + SDHI1_3: intsrc44 { vector = <0x0EE0>; }; + AP_ARM_L2CINT: intsrc45 { vector = <0x0FA0>; }; + IRDA: intsrc46 { vector = <0x0480>; }; + TPU0: intsrc47 { vector = <0x04A0>; }; + SCIFA6: intsrc48 { vector = <0x04C0>; }; + SCIFA7: intsrc49 { vector = <0x04E0>; }; + GETHER: intsrc50 { vector = <0x0500>; }; + ICBS0: intsrc51 { vector = <0x0540>; }; + DDM: intsrc52 { vector = <0x1140>; }; + SDHI2_0: intsrc53 { vector = <0x1200>; }; + SDHI2_1: intsrc54 { vector = <0x1220>; }; + SDHI2_2: intsrc55 { vector = <0x1240>; }; + SDHI2_3: intsrc56 { vector = <0x1260>; }; + RWDT0: intsrc57 { vector = <0x1280>; }; + DMAC1_1_DEI0: intsrc58 { vector = <0x2000>; }; + DMAC1_1_DEI1: intsrc59 { vector = <0x2020>; }; + DMAC1_1_DEI2: intsrc60 { vector = <0x2040>; }; + DMAC1_1_DEI3: intsrc61 { vector = <0x2060>; }; + DMAC1_2_DEI4: intsrc62 { vector = <0x2080>; }; + DMAC1_2_DEI5: intsrc63 { vector = <0x20A0>; }; + DMAC1_2_DADERR: intsrc64 { vector = <0x20C0>; }; + DMAC2_1_DEI0: intsrc65 { vector = <0x2100>; }; + DMAC2_1_DEI1: intsrc66 { vector = <0x2120>; }; + DMAC2_1_DEI2: intsrc67 { vector = <0x2140>; }; + DMAC2_1_DEI3: intsrc68 { vector = <0x2160>; }; + DMAC2_2_DEI4: intsrc69 { vector = <0x2180>; }; + DMAC2_2_DEI5: intsrc70 { vector = <0x21A0>; }; + DMAC2_2_DADERR: intsrc71 { vector = <0x21C0>; }; + DMAC3_1_DEI0: intsrc72 { vector = <0x2200>; }; + DMAC3_1_DEI1: intsrc73 { vector = <0x2220>; }; + DMAC3_1_DEI2: intsrc74 { vector = <0x2240>; }; + DMAC3_1_DEI3: intsrc75 { vector = <0x2260>; }; + DMAC3_2_DEI4: intsrc76 { vector = <0x2280>; }; + DMAC3_2_DEI5: intsrc77 { vector = <0x22A0>; }; + DMAC3_2_DADERR: intsrc78 { vector = <0x22C0>; }; + SHWYSTAT_RT: intsrc79 { vector = <0x1300>; }; + SHWYSTAT_HS: intsrc80 { vector = <0x1320>; }; + SHWYSTAT_COM: intsrc81 { vector = <0x1340>; }; + HDMI: intsrc82 { vector = <0x1700>; }; + USBH_INT: intsrc83 { vector = <0x1540>; }; + USBH_OHCI: intsrc84 { vector = <0x1560>; }; + USBH_EHCI: intsrc85 { vector = <0x1580>; }; + USBH_PME: intsrc86 { vector = <0x15A0>; }; + USBH_BIND: intsrc87 { vector = <0x15C0>; }; + RSPI_OVRF: intsrc88 { vector = <0x1780>; }; + RSPI_SPTEF: intsrc89 { vector = <0x17A0>; }; + RSPI_SPRF: intsrc90 { vector = <0x17C0>; }; + SPU2_0: intsrc91 { vector = <0x1800>; }; + SPU2_1: intsrc92 { vector = <0x1820>; }; + FSI: intsrc93 { vector = <0x1840>; }; + FMSI: intsrc94 { vector = <0x1860>; }; + HDMI_SSS: intsrc95 { vector = <0x18A0>; }; + HDMI_KEY: intsrc96 { vector = <0x18C0>; }; + IPMMU: intsrc97 { vector = <0x1920>; }; + AP_ARM_CTIIRQ: intsrc98 { vector = <0x1980>; }; + AP_ARM_PMURQ: intsrc99 { vector = <0x19A0>; }; + MFIS2: intsrc100 { vector = <0x1A00>; }; + CPORTR2S: intsrc101 { vector = <0x1A20>; }; + CMT14: intsrc102 { vector = <0x1A40>; }; + CMT15: intsrc103 { vector = <0x1A60>; }; + MMCIF_0: intsrc104 { vector = <0x1AA0>; }; + MMCIF_1: intsrc105 { vector = <0x1AC0>; }; + MMCIF_2: intsrc106 { vector = <0x1AE0>; }; + SIM_ERI: intsrc107 { vector = <0x1C00>; }; + SIM_RXI: intsrc108 { vector = <0x1C20>; }; + SIM_TXI: intsrc109 { vector = <0x1C40>; }; + SIM_TEI: intsrc110 { vector = <0x1C60>; }; + STPRO_0: intsrc111 { vector = <0x1C80>; }; + STPRO_1: intsrc112 { vector = <0x1CA0>; }; + STPRO_2: intsrc113 { vector = <0x1CC0>; }; + STPRO_3: intsrc114 { vector = <0x1CE0>; }; + STPRO_4: intsrc115 { vector = <0x1D00>; }; + + intc_groups { + DMAC1_1: intc_group0 { + group = <&DMAC1_1_DEI0 &DMAC1_1_DEI1 + &DMAC1_1_DEI2 &DMAC1_1_DEI3>; + }; + + DMAC1_2: intc_group1 { + group = <&DMAC1_2_DEI4 &DMAC1_2_DEI5 + &DMAC1_2_DADERR>; + }; + + DMAC2_1: intc_group2 { + group = <&DMAC2_1_DEI0 &DMAC2_1_DEI1 + &DMAC2_1_DEI2 &DMAC2_1_DEI3>; + }; + + DMAC2_2: intc_group3 { + group = <&DMAC2_2_DEI4 &DMAC2_2_DEI5 + &DMAC2_2_DADERR>; + }; + + DMAC3_1: intc_group4 { + group = <&DMAC3_1_DEI0 &DMAC3_1_DEI1 + &DMAC3_1_DEI2 &DMAC3_1_DEI3>; + }; + + DMAC3_2: intc_group5 { + group = <&DMAC3_2_DEI4 &DMAC3_2_DEI5 + &DMAC3_2_DADERR>; + }; + + AP_ARM1: intc_group6 { + group = <&AP_ARM_COMMTX &AP_ARM_COMMRX>; + }; + + AP_ARM2: intc_group7 { + group = <&AP_ARM_CTIIRQ &AP_ARM_PMURQ>; + }; + + USBF: intc_group8 { + group = <&USBF_OUL_SOF &USBF_IXL_INT>; + }; + + SDHI0: intc_group9 { + group = <&SDHI0_0 &SDHI0_1 &SDHI0_2 &SDHI0_3>; + }; + + SDHI1: intc_group10 { + group = <&SDHI1_0 &SDHI1_1 &SDHI1_2 &SDHI1_3>; + }; + + SDHI2: intc_group11 { + group = <&SDHI2_0 &SDHI2_1 &SDHI2_2 &SDHI2_3>; + }; + + SHWYSTAT: intc_group12 { + group = <&SHWYSTAT_RT &SHWYSTAT_HS &SHWYSTAT_COM>; + }; + + USBH1: intc_group13 { + group = <&USBH_INT &USBH_OHCI>; + }; + + USBH2: intc_group14 { + group = <&USBH_EHCI &USBH_PME &USBH_BIND>; + }; + + RSPI: intc_group15 { + group = <&RSPI_OVRF &RSPI_SPTEF &RSPI_SPRF>; + }; + + SPU2: intc_group16 { + group = <&SPU2_0 &SPU2_1>; + }; + + FLCTL: intc_group17 { + group = <&FLCTL_FLSTEI &FLCTL_FLTENDI &FLCTL_FLTREQ0I + &FLCTL_FLTREQ1I>; + }; + + IIC1: intc_group18 { + group = <&IIC1_ALI &IIC1_TACKI &IIC1_WAITI &IIC1_DTEI>; + }; + }; + + intc_vectors { + vector_table = <&DIRC &ATAPI &IIC1_ALI &IIC1_TACKI &IIC1_WAITI + &IIC1_DTEI &AP_ARM_COMMTX &AP_ARM_COMMRX &MFI &MFIS &BBIF1 + &BBIF2 &USBHSDMAC &USBF_OUL_SOF &USBF_IXL_INT &SGX540 &CMT1_0 + &CMT1_1 &CMT1_2 &CMT1_3 &CMT2 &CMT3 &KEYSC &SCIFA0 &SCIFA1 + &SCIFA2 &SCIFA3 &MSIOF2 &MSIOF1 &SCIFA4 &SCIFA5 &SCIFB + &FLCTL_FLSTEI &FLCTL_FLTENDI &FLCTL_FLTREQ0I &FLCTL_FLTREQ1I + &SDHI0_0 &SDHI0_1 &SDHI0_2 &SDHI0_3 + &SDHI1_0 &SDHI1_1 &SDHI1_2 &SDHI1_3 + &AP_ARM_L2CINT &IRDA &TPU0 &SCIFA6 &SCIFA7 + &GETHER &ICBS0 &DDM &SDHI2_0 &SDHI2_1 &SDHI2_2 &SDHI2_3 + &RWDT0 + &DMAC1_1_DEI0 &DMAC1_1_DEI1 &DMAC1_1_DEI2 &DMAC1_1_DEI3 + &DMAC1_2_DEI4 &DMAC1_2_DEI5 &DMAC1_2_DADERR + &DMAC2_1_DEI0 &DMAC2_1_DEI1 &DMAC2_1_DEI2 &DMAC2_1_DEI3 + &DMAC2_2_DEI4 &DMAC2_2_DEI5 &DMAC2_2_DADERR + &DMAC3_1_DEI0 &DMAC3_1_DEI1 &DMAC3_1_DEI2 &DMAC3_1_DEI3 + &DMAC3_2_DEI4 &DMAC3_2_DEI5 &DMAC3_2_DADERR + &SHWYSTAT_RT &SHWYSTAT_HS &SHWYSTAT_COM + &USBH_INT &USBH_OHCI &USBH_EHCI &USBH_PME &USBH_BIND + &HDMI + &RSPI_OVRF &RSPI_SPTEF &RSPI_SPRF + &SPU2_0 &SPU2_1 &FSI &FMSI &HDMI_SSS &HDMI_KEY + &IPMMU &AP_ARM_CTIIRQ &AP_ARM_PMURQ &MFIS2 + &CPORTR2S + &CMT14 &CMT15 &MMCIF_0 &MMCIF_1 &MMCIF_2 + &SIM_ERI &SIM_RXI &SIM_TXI &SIM_TEI + &STPRO_0 &STPRO_1 &STPRO_2 &STPRO_3 &STPRO_4>; + }; + + intc_mask_registers { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc_mask0 { + reg = <0xe6940080 1>, <0xe69400c0 1>; + reginfo = <&DMAC2_1_DEI3 &DMAC2_1_DEI2 &DMAC2_1_DEI1 + &DMAC2_1_DEI0 0 0 &AP_ARM_COMMTX &AP_ARM_COMMRX>; + }; + + intc_mask1 { + reg = <0xe6940084 1>, <0xe69400c4 1>; + reginfo = <&ATAPI 0 &DIRC 0 &DMAC1_1_DEI3 &DMAC1_1_DEI2 + &DMAC1_1_DEI1 &DMAC1_1_DEI0>; + }; + + intc_mask2 { + reg = <0xe6940088 1>, <0xe69400c8 1>; + reginfo = <0 0 0 0 &BBIF1 &BBIF2 &MFIS &MFI>; + }; + + intc_mask3 { + reg = <0xe694008c 1>, <0xe69400cc 1>; + reginfo = <&DMAC3_1_DEI3 &DMAC3_1_DEI2 &DMAC3_1_DEI1 + &DMAC3_1_DEI0 &DMAC3_2_DADERR &DMAC3_2_DEI5 + &DMAC3_2_DEI4 &IRDA>; + }; + + intc_mask4 { + reg = <0xe6940090 1>, <0xe69400d0 1>; + reginfo = <&DDM>; + }; + + intc_mask5 { + reg = <0xe6940094 1>, <0xe69400d4 1>; + reginfo = <&KEYSC &DMAC1_2_DADERR &DMAC1_2_DEI5 &DMAC1_2_DEI4 + &SCIFA3 &SCIFA2 &SCIFA1 &SCIFA0>; + }; + + intc_mask6 { + reg = <0xe6940098 1>, <0xe69400d8 1>; + reginfo = <&SCIFB &SCIFA5 &SCIFA4 &MSIOF1 0 0 &MSIOF2>; + }; + + intc_mask7 { + reg = <0xe694009c 1>, <0xe69400dc 1>; + reginfo = <&SDHI0_3 &SDHI0_2 &SDHI0_1 &SDHI0_0 &FLCTL_FLTREQ1I + &FLCTL_FLTREQ0I &FLCTL_FLTENDI &FLCTL_FLSTEI>; + }; + + intc_mask8 { + reg = <0xe69400a0 1>, <0xe69400e0 1>; + reginfo = <&SDHI1_3 &SDHI1_2 &SDHI1_1 &SDHI1_0 0 + &USBHSDMAC 0 &AP_ARM_L2CINT>; + }; + + intc_mask9 { + reg = <0xe69400a4 1>, <0xe69400e4 1>; + reginfo = <&CMT1_3 &CMT1_2 &CMT1_1 + &CMT1_0 &CMT2 &USBF_IXL_INT &USBF_OUL_SOF &SGX540>; + }; + + intc_mask10 { + reg = <0xe69400a8 1>, <0xe69400e8 1>; + reginfo = <0 &DMAC2_2_DADERR &DMAC2_2_DEI5 &DMAC2_2_DEI4>; + }; + + intc_mask11 { + reg = <0xe69400ac 1>, <0xe69400ec 1>; + reginfo = <&IIC1_DTEI &IIC1_WAITI + &IIC1_TACKI &IIC1_ALI &ICBS0>; + }; + + intc_mask12 { + reg = <0xe69400b0 1>, <0xe69400f0 1>; + reginfo = <0 0 &TPU0 &SCIFA6 &SCIFA7 &GETHER>; + }; + + intc_mask13 { + reg = <0xe69400b4 1>, <0xe69400f4 1>; + reginfo = <&SDHI2_3 &SDHI2_2 &SDHI2_1 + &SDHI2_0 0 &CMT3 0 &RWDT0>; + }; + + intc_mask14 { + reg = <0xe6950080 1>, <0xe69500c0 1>; + reginfo = <&SHWYSTAT_RT &SHWYSTAT_HS + &SHWYSTAT_COM>; + }; + + intc_mask15 { + reg = <0xe6950088 1>, <0xe69500c8 1>; + reginfo = <0 0 &USBH_INT &USBH_OHCI + &USBH_EHCI &USBH_PME &USBH_BIND>; + }; + + intc_mask16 { + reg = <0xe6950090 1>, <0xe69500d0 1>; + reginfo = <&HDMI 0 0 0 &RSPI_OVRF + &RSPI_SPTEF &RSPI_SPRF>; + }; + + intc_mask17 { + reg = <0xe6950094 1>, <0xe69500d4 1>; + reginfo = <&SPU2_0 &SPU2_1 &FSI &FMSI 0 + &HDMI_SSS &HDMI_KEY>; + }; + + intc_mask18 { + reg = <0xe6950098 1>, <0xe69500d8 1>; + reginfo = <0 &IPMMU 0 0 &AP_ARM_CTIIRQ + &AP_ARM_PMURQ>; + }; + + intc_mask19 { + reg = <0xe695009c 1>, <0xe69500dc 1>; + reginfo = <&MFIS2 &CPORTR2S &CMT14 &CMT15 + 0 &MMCIF_0 &MMCIF_1 &MMCIF_2>; + }; + + intc_mask20 { + reg = <0xe69500a4 1>, <0xe69500e4 1>; + reginfo = <&SIM_ERI &SIM_RXI &SIM_TXI + &SIM_TEI &STPRO_0 &STPRO_1 &STPRO_2 &STPRO_3>; + }; + + intc_mask21 { + reg = <0xe69500a8 1>, <0xe69500e8 1>; + reginfo = <&STPRO_4>; + }; + }; + + intc_prio_registers { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc_prio0 { + reg = <0xe6940000 2>; + field-width = <4>; + reginfo = <&DMAC3_1 &DMAC3_2 &CMT2 &ICBS0>; + }; + + intc_prio1 { + reg = <0xe6940004 2>; + field-width = <4>; + reginfo =<&IRDA 0 &BBIF1 &BBIF2>; + }; + + intc_prio2 { + reg = <0xe6940008 2>; + field-width = <4>; + reginfo = <&ATAPI 0 &CMT1_1 &AP_ARM1>; + }; + + intc_prio3 { + reg = <0xe694000c 2>; + field-width = <4>; + reginfo = <0 0 &CMT1_2>; + }; + + intc_prio4 { + reg = <0xe6940010 2>; + field-width = <4>; + reginfo = <&DMAC1_1 &MFIS &MFI &USBF>; + }; + + intc_prio5 { + reg = <0xe6940014 2>; + field-width = <4>; + reginfo = <&KEYSC &DMAC1_2 &SGX540 &CMT1_0>; + }; + + intc_prio6 { + reg = <0xe6940018 2>; + field-width = <4>; + reginfo = <&SCIFA0 &SCIFA1 &SCIFA2 &SCIFA3>; + }; + + intc_prio7 { + reg = <0xe694001c 2>; + field-width = <4>; + reginfo = <&MSIOF2 &USBHSDMAC &FLCTL &SDHI0>; + }; + + intc_prio8 { + reg = <0xe6940020 2>; + field-width = <4>; + reginfo = <&MSIOF1 &SCIFA4 0 &IIC1>; + }; + + intc_prio9 { + reg = <0xe6940024 2>; + field-width = <4>; + reginfo = <&DMAC2_1 &DMAC2_2 &AP_ARM_L2CINT>; + }; + + intc_prio10 { + reg = <0xe6940028 2>; + field-width = <4>; + reginfo = <0 &CMT1_3 0 &SDHI1>; + }; + + intc_prio11 { + reg = <0xe694002c 2>; + field-width = <4>; + reginfo = <&TPU0 &SCIFA6 &SCIFA7 &GETHER>; + }; + + intc_prio12 { + reg = <0xe6940030 2>; + field-width = <4>; + reginfo = <0 &CMT3 0 &RWDT0>; + }; + + intc_prio13 { + reg = <0xe6940034 2>; + field-width = <4>; + reginfo = <&SCIFB &SCIFA5 0 &DDM>; + }; + + intc_prio14 { + reg = <0xe6940038 2>; + field-width = <4>; + reginfo = <0 0 &DIRC &SDHI2>; + }; + + intc_prio15 { + reg = <0xe6950000 2>; + field-width = <4>; + reginfo = <&SHWYSTAT>; + }; + + intc_prio16 { + reg = <0xe6950010 2>; + field-width = <4>; + reginfo = <&USBH1>; + }; + + intc_prio17 { + reg = <0xe6950014 2>; + field-width = <4>; + reginfo = <&USBH2>; + }; + + intc_prio18 { + reg = <0xe6950020 2>; + field-width = <4>; + reginfo = <&HDMI>; + }; + + intc_prio19 { + reg = <0xe6950024 2>; + field-width = <4>; + reginfo = <&RSPI>; + }; + + intc_prio20 { + reg = <0xe6950028 2>; + field-width = <4>; + reginfo = <&SPU2 0 &FSI &FMSI>; + }; + + intc_prio21 { + reg = <0xe695002c 2>; + field-width = <4>; + reginfo = <0 &HDMI_SSS &HDMI_KEY>; + }; + + intc_prio22 { + reg = <0xe6950030 2>; + field-width = <4>; + reginfo = <&IPMMU>; + }; + + intc_prio23 { + reg = <0xe6950034 2>; + field-width = <4>; + reginfo = <&AP_ARM2>; + }; + + intc_prio24 { + reg = <0xe6950038 2>; + field-width = <4>; + reginfo = <&MFIS2 &CPORTR2S &CMT14 &CMT15>; + }; + + intc_prio25 { + reg = <0xe695003c 2>; + field-width = <4>; + reginfo = <0 &MMCIF_0 &MMCIF_1 &MMCIF_2>; + }; + + intc_prio26 { + reg = <0xe6950048 2>; + field-width = <4>; + reginfo = <&SIM_ERI &SIM_RXI &SIM_TXI &SIM_TEI>; + }; + + intc_prio27 { + reg = <0xe695004c 2>; + field-width = <4>; + reginfo = <&STPRO_0 &STPRO_1 &STPRO_2 &STPRO_3>; + }; + + intc_prio28 { + reg = <0xe6950050 2>; + field-width = <4>; + reginfo = <&STPRO_4>; + }; + }; + }; + + intca_irq_pins: interrupt-controller at 1{ + compatible = "renesas,sh-intc"; + interrupt-controller; + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + reg = <0xe6900000 0x6c>; + + IRQ0: intsrc1 { vector = <0x200>; }; + IRQ1: intsrc2 { vector = <0x220>; }; + IRQ2: intsrc3 { vector = <0x240>; }; + IRQ3: intsrc4 { vector = <0x260>; }; + IRQ4: intsrc5 { vector = <0x280>; }; + IRQ5: intsrc6 { vector = <0x2a0>; }; + IRQ6: intsrc7 { vector = <0x2c0>; }; + IRQ7: intsrc8 { vector = <0x2e0>; }; + IRQ8: intsrc9 { vector = <0x300>; }; + IRQ9: intsrc10 { vector = <0x320>; }; + IRQ10: intsrc11 { vector = <0x340>; }; + IRQ11: intsrc12 { vector = <0x360>; }; + IRQ12: intsrc13 { vector = <0x380>; }; + IRQ13: intsrc14 { vector = <0x3a0>; }; + IRQ14: intsrc15 { vector = <0x3c0>; }; + IRQ15: intsrc16 { vector = <0x3e0>; }; + IRQ16: intsrc17 { vector = <0x3200>; }; + IRQ17: intsrc18 { vector = <0x3220>; }; + IRQ18: intsrc19 { vector = <0x3240>; }; + IRQ19: intsrc20 { vector = <0x3260>; }; + IRQ20: intsrc21 { vector = <0x3280>; }; + IRQ21: intsrc22 { vector = <0x32a0>; }; + IRQ22: intsrc23 { vector = <0x32c0>; }; + IRQ23: intsrc24 { vector = <0x32e0>; }; + IRQ24: intsrc25 { vector = <0x3300>; }; + IRQ25: intsrc26 { vector = <0x3320>; }; + IRQ26: intsrc27 { vector = <0x3340>; }; + IRQ27: intsrc28 { vector = <0x3360>; }; + IRQ28: intsrc29 { vector = <0x3380>; }; + IRQ29: intsrc30 { vector = <0x33a0>; }; + IRQ30: intsrc31 { vector = <0x33c0>; }; + IRQ31: intsrc32 { vector = <0x33e0>; }; + + intc_vectors { + vector_table = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4 &IRQ5 + &IRQ6 &IRQ7 &IRQ8 &IRQ9 &IRQ10 + &IRQ11 &IRQ12 &IRQ13 &IRQ14 &IRQ15 + &IRQ16 &IRQ17 &IRQ18 &IRQ19 &IRQ20 + &IRQ21 &IRQ22 &IRQ23 &IRQ24 &IRQ25 + &IRQ26 &IRQ27 &IRQ28 &IRQ29 &IRQ30 + &IRQ31>; + }; + + intc_mask_registers { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc_mask0 { + reg = <0xe6900040 1>, <0xe6900060 1>; + reginfo = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4 + &IRQ5 &IRQ6 &IRQ7>; + }; + + intc_mask1 { + reg = <0xe6900044 1>, <0xe6900064 1>; + reginfo = <&IRQ8 &IRQ9 &IRQ10 &IRQ11 + &IRQ12 &IRQ13 &IRQ14 &IRQ15>; + }; + + intc_mask2 { + reg = <0xe6900048 1>, <0xe6900068 1>; + reginfo = <&IRQ16 &IRQ17 &IRQ18 &IRQ19 + &IRQ20 &IRQ21 &IRQ22 &IRQ23>; + }; + + intc_mask3 { + reg = <0xe690004C 1>, <0xe690006C 1>; + reginfo = <&IRQ24 &IRQ25 &IRQ26 &IRQ27 + &IRQ28 &IRQ29 &IRQ30 &IRQ31>; + }; + }; + + intc_prio_registers { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc_prio0 { + reg = <0xe6900010 4>; + field-width = <4>; + reginfo = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4 &IRQ5 &IRQ6 &IRQ7>; + }; + + intc_prio1 { + reg = <0xe6900014 4>; + field-width = <4>; + reginfo = <&IRQ8 &IRQ9 &IRQ10 &IRQ11 + &IRQ12 &IRQ13 &IRQ14 &IRQ15>; + }; + + intc_prio2 { + reg = <0xe6900018 4>; + field-width = <4>; + reginfo = <&IRQ16 &IRQ17 &IRQ18 &IRQ19 + &IRQ20 &IRQ21 &IRQ22 &IRQ23>; + }; + + intc_prio3 { + reg = <0xe690001C 4>; + field-width = <4>; + reginfo = <&IRQ24 &IRQ25 &IRQ26 &IRQ27 + &IRQ28 &IRQ29 &IRQ30 &IRQ31>; + }; + }; + + intc_sense_registers { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc_sense0 { + reg = <0xe6900000 4>; + field-width = <4>; + reginfo = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4 &IRQ5 &IRQ6 &IRQ7>; + }; + + intc_sense1 { + reg = <0xe6900004 4>; + field-width = <4>; + reginfo = <&IRQ8 &IRQ9 &IRQ10 &IRQ11 + &IRQ12 &IRQ13 &IRQ14 &IRQ15>; + }; + + intc_sense2 { + reg = <0xe6900008 4>; + field-width = <4>; + reginfo = <&IRQ16 &IRQ17 &IRQ18 &IRQ19 + &IRQ20 &IRQ21 &IRQ22 &IRQ23>; + }; + + intc_sense3 { + reg = <0xe690000C 4>; + field-width = <4>; + reginfo = <&IRQ24 &IRQ25 &IRQ26 &IRQ27 + &IRQ28 &IRQ29 &IRQ30 &IRQ31>; + }; + }; + + intc_ack_registers { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc_ack0 { + reg = <0xe6900020 1>; + reginfo = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4 &IRQ5 &IRQ6 &IRQ7>; + }; + + intc_ack1 { + reg = <0xe6900024 1>; + reginfo = <&IRQ8 &IRQ9 &IRQ10 &IRQ11 + &IRQ12 &IRQ13 &IRQ14 &IRQ15>; + }; + + intc_ack2 { + reg = <0xe6900028 1>; + reginfo = <&IRQ16 &IRQ17 &IRQ18 &IRQ19 + &IRQ20 &IRQ21 &IRQ22 &IRQ23>; + }; + + intc_ack3 { + reg = <0xe690002C 1>; + reginfo = <&IRQ24 &IRQ25 &IRQ26 &IRQ27 + &IRQ28 &IRQ29 &IRQ30 &IRQ31>; + }; + }; + }; + }; }; -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 6/8] ARM: shmobile: r8a7740: Use DT initialisation of INTC 2013-01-09 6:29 [RFC v9 0/8] ARM: shmobile: DT initialisation of INTC Simon Horman ` (4 preceding siblings ...) 2013-01-09 6:30 ` [PATCH 5/8] ARM: shmobile: Add DT table of INTC for r8a7740 Simon Horman @ 2013-01-09 6:30 ` Simon Horman 2013-01-09 6:30 ` [PATCH 7/8] ARM: shmobile: sh7372: Do not initialise TMU when using DT Simon Horman 2013-01-09 6:30 ` [PATCH 8/8] ARM: shmobile: sh7372: Use DT initialisation of INTC Simon Horman 7 siblings, 0 replies; 17+ messages in thread From: Simon Horman @ 2013-01-09 6:30 UTC (permalink / raw) To: linux-arm-kernel From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Cc: Magnus Damm <damm@opensource.se> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- arch/arm/mach-shmobile/setup-r8a7740.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index 28a2ab3..9fe7ca8 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c @@ -879,7 +879,7 @@ static const char *r8a7740_boards_compat_dt[] __initdata = { DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)") .map_io = r8a7740_map_io, .init_early = r8a7740_add_early_devices_dt, - .init_irq = r8a7740_init_irq, + .init_irq = r8a7740_init_irq_of, .handle_irq = shmobile_handle_irq_intc, .init_machine = r8a7740_add_standard_devices_dt, .timer = &shmobile_timer, -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 7/8] ARM: shmobile: sh7372: Do not initialise TMU when using DT 2013-01-09 6:29 [RFC v9 0/8] ARM: shmobile: DT initialisation of INTC Simon Horman ` (5 preceding siblings ...) 2013-01-09 6:30 ` [PATCH 6/8] ARM: shmobile: r8a7740: Use DT initialisation of INTC Simon Horman @ 2013-01-09 6:30 ` Simon Horman 2013-01-09 6:30 ` [PATCH 8/8] ARM: shmobile: sh7372: Use DT initialisation of INTC Simon Horman 7 siblings, 0 replies; 17+ messages in thread From: Simon Horman @ 2013-01-09 6:30 UTC (permalink / raw) To: linux-arm-kernel This is in preparation for initialising INTC using DT. The proposed INTC configuration is not complete and does not allow the TMU to be initialised, to exclude it when using DT. Cc: Magnus Damm <damm@opensource.se> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- arch/arm/mach-shmobile/setup-sh7372.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 42f1945..7dbed95 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -1008,7 +1008,7 @@ static struct platform_device spu1_device = { .num_resources = ARRAY_SIZE(spu1_resources), }; -static struct platform_device *sh7372_early_devices[] __initdata = { +static struct platform_device *sh7372_early_devices_dt[] __initdata = { &scif0_device, &scif1_device, &scif2_device, @@ -1017,6 +1017,9 @@ static struct platform_device *sh7372_early_devices[] __initdata = { &scif5_device, &scif6_device, &cmt2_device, +}; + +static struct platform_device *sh7372_early_devices[] __initdata = { &tmu00_device, &tmu01_device, }; @@ -1070,6 +1073,8 @@ void __init sh7372_add_standard_devices(void) sh7372_init_pm_domains(); + platform_add_devices(sh7372_early_devices_dt, + ARRAY_SIZE(sh7372_early_devices_dt)); platform_add_devices(sh7372_early_devices, ARRAY_SIZE(sh7372_early_devices)); @@ -1088,6 +1093,8 @@ static void __init sh7372_earlytimer_init(void) void __init sh7372_add_early_devices(void) { + early_platform_add_devices(sh7372_early_devices_dt, + ARRAY_SIZE(sh7372_early_devices_dt)); early_platform_add_devices(sh7372_early_devices, ARRAY_SIZE(sh7372_early_devices)); @@ -1104,8 +1111,8 @@ void __init sh7372_add_early_devices_dt(void) { shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */ - early_platform_add_devices(sh7372_early_devices, - ARRAY_SIZE(sh7372_early_devices)); + early_platform_add_devices(sh7372_early_devices_dt, + ARRAY_SIZE(sh7372_early_devices_dt)); /* setup early console here as well */ shmobile_setup_console(); @@ -1120,8 +1127,8 @@ void __init sh7372_add_standard_devices_dt(void) /* clocks are setup late during boot in the case of DT */ sh7372_clock_init(); - platform_add_devices(sh7372_early_devices, - ARRAY_SIZE(sh7372_early_devices)); + platform_add_devices(sh7372_early_devices_dt, + ARRAY_SIZE(sh7372_early_devices_dt)); of_platform_populate(NULL, of_default_bus_match_table, sh7372_auxdata_lookup, NULL); -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 8/8] ARM: shmobile: sh7372: Use DT initialisation of INTC 2013-01-09 6:29 [RFC v9 0/8] ARM: shmobile: DT initialisation of INTC Simon Horman ` (6 preceding siblings ...) 2013-01-09 6:30 ` [PATCH 7/8] ARM: shmobile: sh7372: Do not initialise TMU when using DT Simon Horman @ 2013-01-09 6:30 ` Simon Horman 7 siblings, 0 replies; 17+ messages in thread From: Simon Horman @ 2013-01-09 6:30 UTC (permalink / raw) To: linux-arm-kernel From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Cc: Magnus Damm <damm@opensource.se> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- arch/arm/mach-shmobile/setup-sh7372.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 7dbed95..9f9a3b5 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -1143,7 +1143,7 @@ DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)") .map_io = sh7372_map_io, .init_early = sh7372_add_early_devices_dt, .nr_irqs = NR_IRQS_LEGACY, - .init_irq = sh7372_init_irq, + .init_irq = sh7372_init_irq_of, .handle_irq = shmobile_handle_irq_intc, .init_machine = sh7372_add_standard_devices_dt, .timer = &shmobile_timer, -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 17+ messages in thread
end of thread, other threads:[~2013-01-17 6:20 UTC | newest] Thread overview: 17+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-01-09 6:29 [RFC v9 0/8] ARM: shmobile: DT initialisation of INTC Simon Horman 2013-01-09 6:30 ` [PATCH 1/8] SH: intc: Add support OF for INTC Simon Horman 2013-01-09 11:53 ` Mark Rutland 2013-01-09 19:11 ` Arnd Bergmann 2013-01-10 1:56 ` Simon Horman 2013-01-17 6:20 ` Simon Horman 2013-01-10 1:58 ` Simon Horman 2013-01-10 8:42 ` Magnus Damm 2013-01-09 6:30 ` [PATCH 2/8] ARM: shmobile: Add support OF of INTC for r8a7740 Simon Horman 2013-01-09 6:30 ` [PATCH 3/8] ARM: shmobile: Add support OF of INTC for sh7372 Simon Horman 2013-01-09 11:17 ` Mark Rutland 2013-01-10 8:34 ` Magnus Damm 2013-01-09 6:30 ` [PATCH 4/8] ARM: shmobile: Add DT table " Simon Horman 2013-01-09 6:30 ` [PATCH 5/8] ARM: shmobile: Add DT table of INTC for r8a7740 Simon Horman 2013-01-09 6:30 ` [PATCH 6/8] ARM: shmobile: r8a7740: Use DT initialisation of INTC Simon Horman 2013-01-09 6:30 ` [PATCH 7/8] ARM: shmobile: sh7372: Do not initialise TMU when using DT Simon Horman 2013-01-09 6:30 ` [PATCH 8/8] ARM: shmobile: sh7372: Use DT initialisation of INTC Simon Horman
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