From: Oliver Upton <oupton@google.com>
To: kvmarm@lists.cs.columbia.edu
Cc: kvm@vger.kernel.org, Marc Zyngier <maz@kernel.org>,
James Morse <james.morse@arm.com>,
Alexandru Elisei <Alexandru.Elisei@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
linux-arm-kernel@lists.infradead.org,
Peter Shier <pshier@google.com>,
Ricardo Koller <ricarkol@google.com>,
Reiji Watanabe <reijiw@google.com>
Subject: Re: [PATCH 3/3] KVM: arm64: Start trapping ID registers for 32 bit guests
Date: Tue, 29 Mar 2022 06:36:40 -0700 [thread overview]
Message-ID: <CAOQ_QsiKa4UUvsfypGqiMoFb0c5f5gtyk7ADv0M15E0Gi04QPQ@mail.gmail.com> (raw)
In-Reply-To: <20220329011301.1166265-4-oupton@google.com>
On Mon, Mar 28, 2022 at 6:13 PM Oliver Upton <oupton@google.com> wrote:
>
> To date KVM has not trapped ID register accesses from AArch32, meaning
> that guests get an unconstrained view of what hardware supports. This
> can be a serious problem because we try to base the guest's feature
> registers on values that are safe system-wide. Furthermore, KVM does not
> implement the latest ISA in the PMU and Debug architecture, so we
> constrain these fields to supported values.
>
> Since KVM now correctly handles CP15 and CP10 register traps, we no
> longer need to clear HCR_EL2.TID3 for 32 bit guests and will instead
> emulate reads with their safe values.
>
> Signed-off-by: Oliver Upton <oupton@google.com>
> ---
> arch/arm64/include/asm/kvm_emulate.h | 8 --------
> 1 file changed, 8 deletions(-)
>
> diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
> index d62405ce3e6d..fe32b4c8b35b 100644
> --- a/arch/arm64/include/asm/kvm_emulate.h
> +++ b/arch/arm64/include/asm/kvm_emulate.h
> @@ -75,14 +75,6 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
> if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features))
> vcpu->arch.hcr_el2 &= ~HCR_RW;
>
> - /*
> - * TID3: trap feature register accesses that we virtualise.
> - * For now this is conditional, since no AArch32 feature regs
> - * are currently virtualised.
> - */
> - if (!vcpu_el1_is_32bit(vcpu))
> - vcpu->arch.hcr_el2 |= HCR_TID3;
> -
This is obviously wrong. I deleted one too many lines! Will retest and
resend, this time hopefully with register reads _actually_ being
emulated :)
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next prev parent reply other threads:[~2022-03-29 13:38 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-29 1:12 [PATCH 0/3] KVM: arm64: Limit feature register reads from AArch32 Oliver Upton
2022-03-29 1:12 ` [PATCH 1/3] KVM: arm64: Wire up CP15 feature registers to their AArch64 equivalents Oliver Upton
2022-03-31 5:45 ` Reiji Watanabe
2022-03-31 15:34 ` Oliver Upton
2022-03-29 1:13 ` [PATCH 2/3] KVM: arm64: Plumb cp10 ID traps through the AArch64 sysreg handler Oliver Upton
2022-03-29 1:13 ` [PATCH 3/3] KVM: arm64: Start trapping ID registers for 32 bit guests Oliver Upton
2022-03-29 13:36 ` Oliver Upton [this message]
2022-03-29 1:23 ` [PATCH 0/3] KVM: arm64: Limit feature register reads from AArch32 Oliver Upton
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