* [PATCH v2 0/3] arm: npcm: add basic support for Nuvoton BMCs
@ 2017-08-31 22:53 Brendan Higgins
2017-08-31 22:53 ` [PATCH v2 1/3] " Brendan Higgins
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Brendan Higgins @ 2017-08-31 22:53 UTC (permalink / raw)
To: linux-arm-kernel
Addressed comments from:
- Rob: http://www.spinics.net/lists/devicetree/msg192130.html
- kbuild test robot: http://www.spinics.net/lists/devicetree/msg191902.html
- kbuild test robot: http://www.spinics.net/lists/devicetree/msg191902.html
Changes since previous update:
- Added dependency for !CPU_V6 and !CPU_V6K since headsmp.S depends on v7
instructions
- Dropped errata that depend on !ARCH_MULTIPLATFORM
- Removed custom smp_init_cpus from smp_operations
- Numerous changes to device tree support
Changes have been tested on the NPCM750 evaluation board.
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v2 1/3] arm: npcm: add basic support for Nuvoton BMCs 2017-08-31 22:53 [PATCH v2 0/3] arm: npcm: add basic support for Nuvoton BMCs Brendan Higgins @ 2017-08-31 22:53 ` Brendan Higgins 2017-09-04 14:24 ` Tomer Maimon 2017-09-05 2:47 ` Florian Fainelli 2017-08-31 22:53 ` [PATCH v2 2/3] arm: dts: add Nuvoton NPCM750 device tree Brendan Higgins 2017-08-31 22:54 ` [PATCH v2 3/3] MAINTAINERS: Add entry for the Nuvoton NPCM architecture Brendan Higgins 2 siblings, 2 replies; 9+ messages in thread From: Brendan Higgins @ 2017-08-31 22:53 UTC (permalink / raw) To: linux-arm-kernel Adds basic support for the Nuvoton NPCM750 BMC. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> --- arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + arch/arm/mach-npcm/Kconfig | 58 +++++++++++++++ arch/arm/mach-npcm/Makefile | 3 + arch/arm/mach-npcm/headsmp.S | 120 +++++++++++++++++++++++++++++++ arch/arm/mach-npcm/npcm7xx.c | 34 +++++++++ arch/arm/mach-npcm/platsmp.c | 168 +++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 386 insertions(+) create mode 100644 arch/arm/mach-npcm/Kconfig create mode 100644 arch/arm/mach-npcm/Makefile create mode 100644 arch/arm/mach-npcm/headsmp.S create mode 100644 arch/arm/mach-npcm/npcm7xx.c create mode 100644 arch/arm/mach-npcm/platsmp.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 61a0cb15067e..05543f1cfbde 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -782,6 +782,8 @@ source "arch/arm/mach-netx/Kconfig" source "arch/arm/mach-nomadik/Kconfig" +source "arch/arm/mach-npcm/Kconfig" + source "arch/arm/mach-nspire/Kconfig" source "arch/arm/plat-omap/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 47d3a1ab08d2..60ca50c7d762 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK) += mediatek machine-$(CONFIG_ARCH_MXS) += mxs machine-$(CONFIG_ARCH_NETX) += netx machine-$(CONFIG_ARCH_NOMADIK) += nomadik +machine-$(CONFIG_ARCH_NPCM) += npcm machine-$(CONFIG_ARCH_NSPIRE) += nspire machine-$(CONFIG_ARCH_OXNAS) += oxnas machine-$(CONFIG_ARCH_OMAP1) += omap1 diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig new file mode 100644 index 000000000000..a45670e516b4 --- /dev/null +++ b/arch/arm/mach-npcm/Kconfig @@ -0,0 +1,58 @@ +menuconfig ARCH_NPCM + bool "Nuvoton NPCM Architecture" + select ARCH_REQUIRE_GPIOLIB + select USE_OF + select PINCTRL + select PINCTRL_NPCM7XX + +if ARCH_NPCM + +comment "NPCMX50 CPU type" + +config CPU_NPCM750 + depends on ARCH_NPCM && ARCH_MULTI_V7 && !CPU_V6 && !CPU_V6K + bool "Support for NPCM750 BMC CPU (Poleg)" + select CACHE_L2X0 + select CPU_V7 + select ARM_GIC + select ARM_ERRATA_754322 + select ARM_ERRATA_764369 + select USB_EHCI_ROOT_HUB_TT + select USB_ARCH_HAS_HCD + select USB_ARCH_HAS_EHCI + select USB_EHCI_HCD + select USB_ARCH_HAS_OHCI + select USB_OHCI_HCD + select USB + select FIQ + select CPU_USE_DOMAINS + select COMMON_CLK if OF + select NPCM750_TIMER + select MFD_SYSCON + help + Support for single core NPCM750 BMC CPU (Poleg). + + Single core variant of the Nuvoton NPCM750 BMC based on the Cortex A9. + +config CPU_NPCM750_SMP + depends on CPU_NPCM750 + bool "Support for NPCM750 BMC CPU SMP (Poleg)" + select HAVE_SMP + select HAVE_ARM_SCU + select ARM_ERRATA_794072 + select PL310_ERRATA_588369 + select PL310_ERRATA_727915 + select ARM_ERRATA_720789 + select DEBUG_SPINLOCK + select GENERIC_CLOCKEVENTS + select SMP + select HAVE_ARM_TWD if SMP + select HAVE_ARM_SCU if SMP + select CLKDEV_LOOKUP + select COMMON_CLK if OF + help + Support for dual core NPCM750 BMC CPU (Poleg). + + Dual core variant of the Nuvoton NPCM750 BMC based on the Cortex A9. + +endif diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile new file mode 100644 index 000000000000..634e7c4d6b98 --- /dev/null +++ b/arch/arm/mach-npcm/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_CPU_NPCM750_SMP) += platsmp.o headsmp.o + +obj-$(CONFIG_CPU_NPCM750) += npcm7xx.o diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S new file mode 100644 index 000000000000..d22d2fc1a35c --- /dev/null +++ b/arch/arm/mach-npcm/headsmp.S @@ -0,0 +1,120 @@ +/* + * linux/arch/arm/mach-realview/headsmp.S + * + * Copyright (c) 2003 ARM Limited + * Copyright 2017 Google, Inc. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/linkage.h> +#include <linux/init.h> + +.equ SVC_MODE, 0x13 +.equ I_BIT, 0x80 +.equ F_BIT, 0x40 + +ENTRY(npcm7xx_wakeup_z1) + stmfd sp!, {r0-r12, lr} + ldr r0, =0x01 + ldr r1, =0x01 + ldr r2, =0x01 + + and r3, r0, #0x0F /* Mask off unused bits of ID, and move to r3 */ + and r1, r1, #0x0F /* Mask off unused bits of target_filter */ + and r2, r2, #0x0F /* Mask off unused bits of filter_list */ + + orr r3, r3, r1, LSL #16 /* Combine ID and target_filter */ + orr r3, r3, r2, LSL #24 /* and now the filter list */ + + /* Get the address of the GIC */ + mrc p15, 4, r0, c15, c0, 0 /* Read periph base address */ + add r0, r0, #0x1F00 /* Add offset of the sgi_trigger reg */ + + /* Write to the Software Generated Interrupt Register (ICDSGIR) */ + str r3, [r0] + + ldmfd sp!, {r0-r12, pc} +ENDPROC(npcm7xx_wakeup_z1) + +ENTRY(v7_invalidate_l1_npcmX50) + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 /* invalidate I cache */ + mcr p15, 2, r0, c0, c0, 0 + mrc p15, 1, r0, c0, c0, 0 + + ldr r1, =0x7fff + and r2, r1, r0, lsr #13 + + ldr r1, =0x3ff + + and r3, r1, r0, lsr #3 /* NumWays - 1 */ + add r2, r2, #1 /* NumSets */ + + and r0, r0, #0x7 + add r0, r0, #4 /* SetShift */ + + clz r1, r3 /* WayShift */ + add r4, r3, #1 /* NumWays */ +1: sub r2, r2, #1 /* NumSets-- */ + mov r3, r4 /* Temp = NumWays */ +2: subs r3, r3, #1 /* Temp-- */ + mov r5, r3, lsl r1 + mov r6, r2, lsl r0 + /* Reg = (Temp << WayShift) | (NumSets << SetShift) */ + orr r5, r5, r6 + mcr p15, 0, r5, c7, c6, 2 + bgt 2b + cmp r2, #0 + bgt 1b + dsb + isb + mov pc, lr +ENDPROC(v7_invalidate_l1_npcmX50) + +/* + * MSM specific entry point for secondary CPUs. This provides + * a "holding pen" into which all secondary cores are held until we're + * ready for them to initialise. + */ +ENTRY(npcm7xx_secondary_startup) + msr CPSR_c, #(SVC_MODE) + + bl v7_invalidate_l1_npcmX50 + /* disable vector table remapping */ + mrc p15, 0,r0, c1, c0, 0 + and r0, #0xffffdfff + mcr p15, 0,r0, c1, c0, 0 + +#ifdef CONFIG_CACHE_L2X0 + /* Enable L1 & L2 prefetch + Zero line */ + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #(7 << 1) + mcr p15, 0, r0, c1, c0, 1 +#endif /* CONFIG_CACHE_L2X0 */ + + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #15 + adr r4, 1f + ldmia r4, {r5, r6} + sub r4, r4, r5 + add r6, r6, r4 + str r3,[r2] + +pen: ldr r7, [r6] + cmp r7, r0 + bne pen + + /* + * we've been released from the holding pen: secondary_stack + * should now contain the SVC stack for this core + */ + b secondary_startup +ENDPROC(npcm7xx_secondary_startup) + + .align +1: .long . + .long pen_release diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c new file mode 100644 index 000000000000..106dc62dd62b --- /dev/null +++ b/arch/arm/mach-npcm/npcm7xx.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2014 Nuvoton Technology corporation. + * Copyright 2017 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation;version 2 of the License. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <asm/mach/arch.h> +#include <asm/mach-types.h> +#include <asm/mach/map.h> +#include <asm/hardware/cache-l2x0.h> + +#define NPCM7XX_AUX_VAL (L310_AUX_CTRL_INSTR_PREFETCH | \ + L310_AUX_CTRL_DATA_PREFETCH | \ + L310_AUX_CTRL_NS_LOCKDOWN | \ + L310_AUX_CTRL_CACHE_REPLACE_RR | \ + L2C_AUX_CTRL_SHARED_OVERRIDE | \ + L310_AUX_CTRL_FULL_LINE_ZERO) + +static const char *const npcm7xx_dt_match[] = { + "nuvoton,npcm750", + NULL +}; + +DT_MACHINE_START(NPCM7XX_DT, "NPCMX50 Chip family") + .atag_offset = 0x100, + .dt_compat = npcm7xx_dt_match, + .l2c_aux_val = NPCM7XX_AUX_VAL, + .l2c_aux_mask = ~NPCM7XX_AUX_VAL, +MACHINE_END diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c new file mode 100644 index 000000000000..4b53adb467fc --- /dev/null +++ b/arch/arm/mach-npcm/platsmp.c @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2002 ARM Ltd. + * Copyright (C) 2008 STMicroelctronics. + * Copyright (C) 2009 ST-Ericsson. + * Copyright 2017 Google, Inc. + * + * This file is based on arm realview platform + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define pr_fmt(fmt) "PLATSMP: " fmt + +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/smp.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/of_address.h> +#include <asm/cacheflush.h> +#include <asm/smp.h> +#include <asm/smp_plat.h> +#include <asm/smp_scu.h> + +#define NPCM7XX_SCRPAD_REG 0x13c + +static void __iomem *gcr_base; +static void __iomem *scu_base; + +/* This is called from headsmp.S to wakeup the secondary core */ +extern void npcm7xx_secondary_startup(void); +extern void npcm7xx_wakeup_z1(void); + +/* + * Write pen_release in a way that is guaranteed to be visible to all + * observers, irrespective of whether they're taking part in coherency + * or not. This is necessary for the hotplug code to work reliably. + */ +static void npcm7xx_write_pen_release(int val) +{ + pen_release = val; + /* write to pen_release must be visible to all observers. */ + smp_wmb(); + __cpuc_flush_dcache_area((void *) &pen_release, sizeof(pen_release)); + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); +} + +static DEFINE_SPINLOCK(boot_lock); + +static void npcm7xx_smp_secondary_init(unsigned int cpu) +{ + /* + * let the primary processor know we're out of the + * pen, then head off into the C entry point + */ + npcm7xx_write_pen_release(-1); + + /* + * Synchronise with the boot thread. + */ + spin_lock(&boot_lock); + spin_unlock(&boot_lock); +} + +static int npcm7xx_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long timeout; + + if (!gcr_base) + return -EIO; + + /* + * set synchronisation state between this boot processor + * and the secondary one + */ + spin_lock(&boot_lock); + + /* + * The secondary processor is waiting to be released from + * the holding pen - release it, then wait for it to flag + * that it has been released by resetting pen_release. + */ + npcm7xx_write_pen_release(cpu_logical_map(cpu)); + iowrite32(virt_to_phys(npcm7xx_secondary_startup), + gcr_base + NPCM7XX_SCRPAD_REG); + /* make npcm7xx_secondary_startup visible to all observers. */ + smp_rmb(); + + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + timeout = jiffies + (HZ * 1); + while (time_before(jiffies, timeout)) { + /* make sure we see any writes to pen_release. */ + smp_rmb(); + if (pen_release == -1) + break; + + udelay(10); + } + + /* + * now the secondary core is starting up let it run its + * calibrations, then wait for it to finish + */ + spin_unlock(&boot_lock); + + return pen_release != -1 ? -EIO : 0; +} + + +static void __init npcm7xx_wakeup_secondary(void) +{ + /* + * write the address of secondary startup into the backup ram register + * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the + * backup ram register at offset 0x1FF0, which is what boot rom code + * is waiting for. This would wake up the secondary core from WFE + */ + iowrite32(virt_to_phys(npcm7xx_secondary_startup), gcr_base + + NPCM7XX_SCRPAD_REG); + /* make sure npcm7xx_secondary_startup is seen by all observers. */ + smp_wmb(); + dsb_sev(); + + /* make sure write buffer is drained */ + mb(); +} + +static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *gcr_np, *scu_np; + + gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr"); + if (!gcr_np) { + pr_err("no gcr device node\n"); + return; + } + gcr_base = of_iomap(gcr_np, 0); + if (!gcr_base) { + pr_err("could not iomap gcr at: 0x%llx\n", gcr_base); + return; + } + + scu_np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); + if (!scu_np) { + pr_err("no scu device node\n"); + return; + } + scu_base = of_iomap(scu_np, 0); + if (!scu_base) { + pr_err("could not iomap gcr at: 0x%llx\n", scu_base); + return; + } + + scu_enable(scu_base); + npcm7xx_wakeup_secondary(); +} + +static struct smp_operations npcm7xx_smp_ops __initdata = { + .smp_prepare_cpus = npcm7xx_smp_prepare_cpus, + .smp_boot_secondary = npcm7xx_smp_boot_secondary, + .smp_secondary_init = npcm7xx_smp_secondary_init, +}; + +CPU_METHOD_OF_DECLARE(npcm7xx_smp, "nuvoton,npcm7xx-smp", &npcm7xx_smp_ops); -- 2.14.1.581.gf28d330327-goog ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 1/3] arm: npcm: add basic support for Nuvoton BMCs 2017-08-31 22:53 ` [PATCH v2 1/3] " Brendan Higgins @ 2017-09-04 14:24 ` Tomer Maimon 2017-09-05 2:47 ` Florian Fainelli 1 sibling, 0 replies; 9+ messages in thread From: Tomer Maimon @ 2017-09-04 14:24 UTC (permalink / raw) To: linux-arm-kernel On 1 September 2017 at 01:53, Brendan Higgins <brendanhiggins@google.com> wrote: > Adds basic support for the Nuvoton NPCM750 BMC. > > Signed-off-by: Brendan Higgins <brendanhiggins@google.com> > --- > arch/arm/Kconfig | 2 + > arch/arm/Makefile | 1 + > arch/arm/mach-npcm/Kconfig | 58 +++++++++++++++ > arch/arm/mach-npcm/Makefile | 3 + > arch/arm/mach-npcm/headsmp.S | 120 +++++++++++++++++++++++++++++++ > arch/arm/mach-npcm/npcm7xx.c | 34 +++++++++ > arch/arm/mach-npcm/platsmp.c | 168 +++++++++++++++++++++++++++++++++++++++++++ > 7 files changed, 386 insertions(+) > create mode 100644 arch/arm/mach-npcm/Kconfig > create mode 100644 arch/arm/mach-npcm/Makefile > create mode 100644 arch/arm/mach-npcm/headsmp.S > create mode 100644 arch/arm/mach-npcm/npcm7xx.c > create mode 100644 arch/arm/mach-npcm/platsmp.c > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 61a0cb15067e..05543f1cfbde 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -782,6 +782,8 @@ source "arch/arm/mach-netx/Kconfig" > > source "arch/arm/mach-nomadik/Kconfig" > > +source "arch/arm/mach-npcm/Kconfig" > + > source "arch/arm/mach-nspire/Kconfig" > > source "arch/arm/plat-omap/Kconfig" > diff --git a/arch/arm/Makefile b/arch/arm/Makefile > index 47d3a1ab08d2..60ca50c7d762 100644 > --- a/arch/arm/Makefile > +++ b/arch/arm/Makefile > @@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK) += mediatek > machine-$(CONFIG_ARCH_MXS) += mxs > machine-$(CONFIG_ARCH_NETX) += netx > machine-$(CONFIG_ARCH_NOMADIK) += nomadik > +machine-$(CONFIG_ARCH_NPCM) += npcm > machine-$(CONFIG_ARCH_NSPIRE) += nspire > machine-$(CONFIG_ARCH_OXNAS) += oxnas > machine-$(CONFIG_ARCH_OMAP1) += omap1 > diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig > new file mode 100644 > index 000000000000..a45670e516b4 > --- /dev/null > +++ b/arch/arm/mach-npcm/Kconfig > @@ -0,0 +1,58 @@ > +menuconfig ARCH_NPCM > + bool "Nuvoton NPCM Architecture" > + select ARCH_REQUIRE_GPIOLIB > + select USE_OF > + select PINCTRL > + select PINCTRL_NPCM7XX > + > +if ARCH_NPCM > + > +comment "NPCMX50 CPU type" > + > +config CPU_NPCM750 > + depends on ARCH_NPCM && ARCH_MULTI_V7 && !CPU_V6 && !CPU_V6K > + bool "Support for NPCM750 BMC CPU (Poleg)" > + select CACHE_L2X0 > + select CPU_V7 > + select ARM_GIC > + select ARM_ERRATA_754322 > + select ARM_ERRATA_764369 > + select USB_EHCI_ROOT_HUB_TT > + select USB_ARCH_HAS_HCD > + select USB_ARCH_HAS_EHCI > + select USB_EHCI_HCD > + select USB_ARCH_HAS_OHCI > + select USB_OHCI_HCD > + select USB > + select FIQ > + select CPU_USE_DOMAINS > + select COMMON_CLK if OF > + select NPCM750_TIMER > + select MFD_SYSCON > + help > + Support for single core NPCM750 BMC CPU (Poleg). > + > + Single core variant of the Nuvoton NPCM750 BMC based on the Cortex A9. > + > +config CPU_NPCM750_SMP > + depends on CPU_NPCM750 > + bool "Support for NPCM750 BMC CPU SMP (Poleg)" > + select HAVE_SMP > + select HAVE_ARM_SCU > + select ARM_ERRATA_794072 > + select PL310_ERRATA_588369 > + select PL310_ERRATA_727915 > + select ARM_ERRATA_720789 > + select DEBUG_SPINLOCK > + select GENERIC_CLOCKEVENTS > + select SMP > + select HAVE_ARM_TWD if SMP > + select HAVE_ARM_SCU if SMP > + select CLKDEV_LOOKUP > + select COMMON_CLK if OF > + help > + Support for dual core NPCM750 BMC CPU (Poleg). > + > + Dual core variant of the Nuvoton NPCM750 BMC based on the Cortex A9. > + > +endif > diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile > new file mode 100644 > index 000000000000..634e7c4d6b98 > --- /dev/null > +++ b/arch/arm/mach-npcm/Makefile > @@ -0,0 +1,3 @@ > +obj-$(CONFIG_CPU_NPCM750_SMP) += platsmp.o headsmp.o > + > +obj-$(CONFIG_CPU_NPCM750) += npcm7xx.o > diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S > new file mode 100644 > index 000000000000..d22d2fc1a35c > --- /dev/null > +++ b/arch/arm/mach-npcm/headsmp.S > @@ -0,0 +1,120 @@ > +/* > + * linux/arch/arm/mach-realview/headsmp.S > + * > + * Copyright (c) 2003 ARM Limited > + * Copyright 2017 Google, Inc. > + * All Rights Reserved > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include <linux/linkage.h> > +#include <linux/init.h> > + > +.equ SVC_MODE, 0x13 > +.equ I_BIT, 0x80 > +.equ F_BIT, 0x40 > + > +ENTRY(npcm7xx_wakeup_z1) > + stmfd sp!, {r0-r12, lr} > + ldr r0, =0x01 > + ldr r1, =0x01 > + ldr r2, =0x01 > + > + and r3, r0, #0x0F /* Mask off unused bits of ID, and move to r3 */ > + and r1, r1, #0x0F /* Mask off unused bits of target_filter */ > + and r2, r2, #0x0F /* Mask off unused bits of filter_list */ > + > + orr r3, r3, r1, LSL #16 /* Combine ID and target_filter */ > + orr r3, r3, r2, LSL #24 /* and now the filter list */ > + > + /* Get the address of the GIC */ > + mrc p15, 4, r0, c15, c0, 0 /* Read periph base address */ > + add r0, r0, #0x1F00 /* Add offset of the sgi_trigger reg */ > + > + /* Write to the Software Generated Interrupt Register (ICDSGIR) */ > + str r3, [r0] > + > + ldmfd sp!, {r0-r12, pc} > +ENDPROC(npcm7xx_wakeup_z1) > + > +ENTRY(v7_invalidate_l1_npcmX50) > + mov r0, #0 > + mcr p15, 0, r0, c7, c5, 0 /* invalidate I cache */ > + mcr p15, 2, r0, c0, c0, 0 > + mrc p15, 1, r0, c0, c0, 0 > + > + ldr r1, =0x7fff > + and r2, r1, r0, lsr #13 > + > + ldr r1, =0x3ff > + > + and r3, r1, r0, lsr #3 /* NumWays - 1 */ > + add r2, r2, #1 /* NumSets */ > + > + and r0, r0, #0x7 > + add r0, r0, #4 /* SetShift */ > + > + clz r1, r3 /* WayShift */ > + add r4, r3, #1 /* NumWays */ > +1: sub r2, r2, #1 /* NumSets-- */ > + mov r3, r4 /* Temp = NumWays */ > +2: subs r3, r3, #1 /* Temp-- */ > + mov r5, r3, lsl r1 > + mov r6, r2, lsl r0 > + /* Reg = (Temp << WayShift) | (NumSets << SetShift) */ > + orr r5, r5, r6 > + mcr p15, 0, r5, c7, c6, 2 > + bgt 2b > + cmp r2, #0 > + bgt 1b > + dsb > + isb > + mov pc, lr > +ENDPROC(v7_invalidate_l1_npcmX50) > + > +/* > + * MSM specific entry point for secondary CPUs. This provides > + * a "holding pen" into which all secondary cores are held until we're > + * ready for them to initialise. > + */ > +ENTRY(npcm7xx_secondary_startup) > + msr CPSR_c, #(SVC_MODE) > + > + bl v7_invalidate_l1_npcmX50 > + /* disable vector table remapping */ > + mrc p15, 0,r0, c1, c0, 0 > + and r0, #0xffffdfff > + mcr p15, 0,r0, c1, c0, 0 > + > +#ifdef CONFIG_CACHE_L2X0 > + /* Enable L1 & L2 prefetch + Zero line */ > + mrc p15, 0, r0, c1, c0, 1 > + orr r0, r0, #(7 << 1) > + mcr p15, 0, r0, c1, c0, 1 > +#endif /* CONFIG_CACHE_L2X0 */ > + > + mrc p15, 0, r0, c0, c0, 5 > + and r0, r0, #15 > + adr r4, 1f > + ldmia r4, {r5, r6} > + sub r4, r4, r5 > + add r6, r6, r4 > + str r3,[r2] > + > +pen: ldr r7, [r6] > + cmp r7, r0 > + bne pen > + > + /* > + * we've been released from the holding pen: secondary_stack > + * should now contain the SVC stack for this core > + */ > + b secondary_startup > +ENDPROC(npcm7xx_secondary_startup) > + > + .align > +1: .long . > + .long pen_release > diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c > new file mode 100644 > index 000000000000..106dc62dd62b > --- /dev/null > +++ b/arch/arm/mach-npcm/npcm7xx.c > @@ -0,0 +1,34 @@ > +/* > + * Copyright (c) 2014 Nuvoton Technology corporation. > + * Copyright 2017 Google, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation;version 2 of the License. > + */ > + > +#include <linux/kernel.h> > +#include <linux/types.h> > +#include <asm/mach/arch.h> > +#include <asm/mach-types.h> > +#include <asm/mach/map.h> > +#include <asm/hardware/cache-l2x0.h> > + > +#define NPCM7XX_AUX_VAL (L310_AUX_CTRL_INSTR_PREFETCH | \ > + L310_AUX_CTRL_DATA_PREFETCH | \ > + L310_AUX_CTRL_NS_LOCKDOWN | \ > + L310_AUX_CTRL_CACHE_REPLACE_RR | \ > + L2C_AUX_CTRL_SHARED_OVERRIDE | \ > + L310_AUX_CTRL_FULL_LINE_ZERO) > + > +static const char *const npcm7xx_dt_match[] = { > + "nuvoton,npcm750", > + NULL > +}; > + > +DT_MACHINE_START(NPCM7XX_DT, "NPCMX50 Chip family") > + .atag_offset = 0x100, > + .dt_compat = npcm7xx_dt_match, > + .l2c_aux_val = NPCM7XX_AUX_VAL, > + .l2c_aux_mask = ~NPCM7XX_AUX_VAL, > +MACHINE_END > diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c > new file mode 100644 > index 000000000000..4b53adb467fc > --- /dev/null > +++ b/arch/arm/mach-npcm/platsmp.c > @@ -0,0 +1,168 @@ > +/* > + * Copyright (C) 2002 ARM Ltd. > + * Copyright (C) 2008 STMicroelctronics. > + * Copyright (C) 2009 ST-Ericsson. > + * Copyright 2017 Google, Inc. > + * > + * This file is based on arm realview platform > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#define pr_fmt(fmt) "PLATSMP: " fmt > + > +#include <linux/delay.h> > +#include <linux/device.h> > +#include <linux/smp.h> > +#include <linux/io.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/of_platform.h> > +#include <linux/of_address.h> > +#include <asm/cacheflush.h> > +#include <asm/smp.h> > +#include <asm/smp_plat.h> > +#include <asm/smp_scu.h> > + > +#define NPCM7XX_SCRPAD_REG 0x13c > + > +static void __iomem *gcr_base; > +static void __iomem *scu_base; > + > +/* This is called from headsmp.S to wakeup the secondary core */ > +extern void npcm7xx_secondary_startup(void); > +extern void npcm7xx_wakeup_z1(void); > + > +/* > + * Write pen_release in a way that is guaranteed to be visible to all > + * observers, irrespective of whether they're taking part in coherency > + * or not. This is necessary for the hotplug code to work reliably. > + */ > +static void npcm7xx_write_pen_release(int val) > +{ > + pen_release = val; > + /* write to pen_release must be visible to all observers. */ > + smp_wmb(); > + __cpuc_flush_dcache_area((void *) &pen_release, sizeof(pen_release)); > + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); > +} > + > +static DEFINE_SPINLOCK(boot_lock); > + > +static void npcm7xx_smp_secondary_init(unsigned int cpu) > +{ > + /* > + * let the primary processor know we're out of the > + * pen, then head off into the C entry point > + */ > + npcm7xx_write_pen_release(-1); > + > + /* > + * Synchronise with the boot thread. > + */ > + spin_lock(&boot_lock); > + spin_unlock(&boot_lock); > +} > + > +static int npcm7xx_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) > +{ > + unsigned long timeout; > + > + if (!gcr_base) > + return -EIO; > + > + /* > + * set synchronisation state between this boot processor > + * and the secondary one > + */ > + spin_lock(&boot_lock); > + > + /* > + * The secondary processor is waiting to be released from > + * the holding pen - release it, then wait for it to flag > + * that it has been released by resetting pen_release. > + */ > + npcm7xx_write_pen_release(cpu_logical_map(cpu)); > + iowrite32(virt_to_phys(npcm7xx_secondary_startup), > + gcr_base + NPCM7XX_SCRPAD_REG); > + /* make npcm7xx_secondary_startup visible to all observers. */ > + smp_rmb(); > + > + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); > + timeout = jiffies + (HZ * 1); > + while (time_before(jiffies, timeout)) { > + /* make sure we see any writes to pen_release. */ > + smp_rmb(); > + if (pen_release == -1) > + break; > + > + udelay(10); > + } > + > + /* > + * now the secondary core is starting up let it run its > + * calibrations, then wait for it to finish > + */ > + spin_unlock(&boot_lock); > + > + return pen_release != -1 ? -EIO : 0; > +} > + > + > +static void __init npcm7xx_wakeup_secondary(void) > +{ > + /* > + * write the address of secondary startup into the backup ram register > + * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the > + * backup ram register at offset 0x1FF0, which is what boot rom code > + * is waiting for. This would wake up the secondary core from WFE > + */ > + iowrite32(virt_to_phys(npcm7xx_secondary_startup), gcr_base + > + NPCM7XX_SCRPAD_REG); > + /* make sure npcm7xx_secondary_startup is seen by all observers. */ > + smp_wmb(); > + dsb_sev(); > + > + /* make sure write buffer is drained */ > + mb(); > +} > + > +static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus) > +{ > + struct device_node *gcr_np, *scu_np; > + > + gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr"); > + if (!gcr_np) { > + pr_err("no gcr device node\n"); > + return; > + } > + gcr_base = of_iomap(gcr_np, 0); > + if (!gcr_base) { > + pr_err("could not iomap gcr at: 0x%llx\n", gcr_base); > + return; > + } > + > + scu_np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); > + if (!scu_np) { > + pr_err("no scu device node\n"); > + return; > + } > + scu_base = of_iomap(scu_np, 0); > + if (!scu_base) { > + pr_err("could not iomap gcr at: 0x%llx\n", scu_base); > + return; > + } > + > + scu_enable(scu_base); > + npcm7xx_wakeup_secondary(); > +} > + > +static struct smp_operations npcm7xx_smp_ops __initdata = { > + .smp_prepare_cpus = npcm7xx_smp_prepare_cpus, > + .smp_boot_secondary = npcm7xx_smp_boot_secondary, > + .smp_secondary_init = npcm7xx_smp_secondary_init, > +}; > + > +CPU_METHOD_OF_DECLARE(npcm7xx_smp, "nuvoton,npcm7xx-smp", &npcm7xx_smp_ops); > -- > 2.14.1.581.gf28d330327-goog > Reviewed-by: Tomer Maimon <tmaimon77@gmail.com> Tested-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> Tested-by: Avi Fishman <avifishman70@gmail.com> ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 1/3] arm: npcm: add basic support for Nuvoton BMCs 2017-08-31 22:53 ` [PATCH v2 1/3] " Brendan Higgins 2017-09-04 14:24 ` Tomer Maimon @ 2017-09-05 2:47 ` Florian Fainelli 2017-09-06 0:42 ` Brendan Higgins 1 sibling, 1 reply; 9+ messages in thread From: Florian Fainelli @ 2017-09-05 2:47 UTC (permalink / raw) To: linux-arm-kernel Le 08/31/17 ? 15:53, Brendan Higgins a ?crit : > Adds basic support for the Nuvoton NPCM750 BMC. > > Signed-off-by: Brendan Higgins <brendanhiggins@google.com> > --- > arch/arm/Kconfig | 2 + > arch/arm/Makefile | 1 + > arch/arm/mach-npcm/Kconfig | 58 +++++++++++++++ > arch/arm/mach-npcm/Makefile | 3 + > arch/arm/mach-npcm/headsmp.S | 120 +++++++++++++++++++++++++++++++ > arch/arm/mach-npcm/npcm7xx.c | 34 +++++++++ > arch/arm/mach-npcm/platsmp.c | 168 +++++++++++++++++++++++++++++++++++++++++++ > 7 files changed, 386 insertions(+) > create mode 100644 arch/arm/mach-npcm/Kconfig > create mode 100644 arch/arm/mach-npcm/Makefile > create mode 100644 arch/arm/mach-npcm/headsmp.S > create mode 100644 arch/arm/mach-npcm/npcm7xx.c > create mode 100644 arch/arm/mach-npcm/platsmp.c > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 61a0cb15067e..05543f1cfbde 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -782,6 +782,8 @@ source "arch/arm/mach-netx/Kconfig" > > source "arch/arm/mach-nomadik/Kconfig" > > +source "arch/arm/mach-npcm/Kconfig" > + > source "arch/arm/mach-nspire/Kconfig" > > source "arch/arm/plat-omap/Kconfig" > diff --git a/arch/arm/Makefile b/arch/arm/Makefile > index 47d3a1ab08d2..60ca50c7d762 100644 > --- a/arch/arm/Makefile > +++ b/arch/arm/Makefile > @@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK) += mediatek > machine-$(CONFIG_ARCH_MXS) += mxs > machine-$(CONFIG_ARCH_NETX) += netx > machine-$(CONFIG_ARCH_NOMADIK) += nomadik > +machine-$(CONFIG_ARCH_NPCM) += npcm > machine-$(CONFIG_ARCH_NSPIRE) += nspire > machine-$(CONFIG_ARCH_OXNAS) += oxnas > machine-$(CONFIG_ARCH_OMAP1) += omap1 > diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig > new file mode 100644 > index 000000000000..a45670e516b4 > --- /dev/null > +++ b/arch/arm/mach-npcm/Kconfig > @@ -0,0 +1,58 @@ > +menuconfig ARCH_NPCM > + bool "Nuvoton NPCM Architecture" > + select ARCH_REQUIRE_GPIOLIB > + select USE_OF > + select PINCTRL > + select PINCTRL_NPCM7XX > + > +if ARCH_NPCM > + > +comment "NPCMX50 CPU type" > + > +config CPU_NPCM750 > + depends on ARCH_NPCM && ARCH_MULTI_V7 && !CPU_V6 && !CPU_V6K Why the !CPU_V6 and !CPU_V6K, you indicate in your cover letter that this is because headsmp.S requires ARMv7 instructions, so just tell the assembler that with: AFLAGS_headsmp.o += -march=armv7-a > + bool "Support for NPCM750 BMC CPU (Poleg)" > + select CACHE_L2X0 > + select CPU_V7 > + select ARM_GIC > + select ARM_ERRATA_754322 > + select ARM_ERRATA_764369 > + select USB_EHCI_ROOT_HUB_TT > + select USB_ARCH_HAS_HCD > + select USB_ARCH_HAS_EHCI > + select USB_EHCI_HCD > + select USB_ARCH_HAS_OHCI > + select USB_OHCI_HCD > + select USB > + select FIQ > + select CPU_USE_DOMAINS > + select COMMON_CLK if OF > + select NPCM750_TIMER > + select MFD_SYSCON > + help > + Support for single core NPCM750 BMC CPU (Poleg). > + > + Single core variant of the Nuvoton NPCM750 BMC based on the Cortex A9. > + > +config CPU_NPCM750_SMP > + depends on CPU_NPCM750 > + bool "Support for NPCM750 BMC CPU SMP (Poleg)" > + select HAVE_SMP > + select HAVE_ARM_SCU > + select ARM_ERRATA_794072 > + select PL310_ERRATA_588369 > + select PL310_ERRATA_727915 > + select ARM_ERRATA_720789 > + select DEBUG_SPINLOCK > + select GENERIC_CLOCKEVENTS > + select SMP > + select HAVE_ARM_TWD if SMP > + select HAVE_ARM_SCU if SMP > + select CLKDEV_LOOKUP > + select COMMON_CLK if OF > + help > + Support for dual core NPCM750 BMC CPU (Poleg). > + > + Dual core variant of the Nuvoton NPCM750 BMC based on the Cortex A9. This is something that you could determine entirely from Device Tree and just have this code unconditionally be built into the kernel and have your SMP operations do nothing if only one CPU is enabled/declared in DT. The runtime overhead of running SMP_ON_UP is largely negligible that it is worth having fewer configuration options to support. > diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S > new file mode 100644 > index 000000000000..d22d2fc1a35c > --- /dev/null > +++ b/arch/arm/mach-npcm/headsmp.S > @@ -0,0 +1,120 @@ > +/* > + * linux/arch/arm/mach-realview/headsmp.S The filename no longer matches but this also indicates that this was largely based on the realview board's SMP bring-up code which Russell King repeatedly tells people to move away from since it is made for a board with a ton of limitations. > + * > + * Copyright (c) 2003 ARM Limited > + * Copyright 2017 Google, Inc. > + * All Rights Reserved > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include <linux/linkage.h> > +#include <linux/init.h> > + > +.equ SVC_MODE, 0x13 > +.equ I_BIT, 0x80 > +.equ F_BIT, 0x40 You can use the C preprocessor to make this more readable and/or re-use existing defines from other header files. > + > +ENTRY(npcm7xx_wakeup_z1) > + stmfd sp!, {r0-r12, lr} > + ldr r0, =0x01 > + ldr r1, =0x01 > + ldr r2, =0x01 > + > + and r3, r0, #0x0F /* Mask off unused bits of ID, and move to r3 */ > + and r1, r1, #0x0F /* Mask off unused bits of target_filter */ > + and r2, r2, #0x0F /* Mask off unused bits of filter_list */ > + > + orr r3, r3, r1, LSL #16 /* Combine ID and target_filter */ > + orr r3, r3, r2, LSL #24 /* and now the filter list */ > + > + /* Get the address of the GIC */ > + mrc p15, 4, r0, c15, c0, 0 /* Read periph base address */ > + add r0, r0, #0x1F00 /* Add offset of the sgi_trigger reg */ > + > + /* Write to the Software Generated Interrupt Register (ICDSGIR) */ > + str r3, [r0] Don't you need some kind of barrier here? > + > + ldmfd sp!, {r0-r12, pc} > +ENDPROC(npcm7xx_wakeup_z1) > + > +ENTRY(v7_invalidate_l1_npcmX50) > + mov r0, #0 > + mcr p15, 0, r0, c7, c5, 0 /* invalidate I cache */ > + mcr p15, 2, r0, c0, c0, 0 > + mrc p15, 1, r0, c0, c0, 0 > + > + ldr r1, =0x7fff > + and r2, r1, r0, lsr #13 > + > + ldr r1, =0x3ff > + > + and r3, r1, r0, lsr #3 /* NumWays - 1 */ > + add r2, r2, #1 /* NumSets */ > + > + and r0, r0, #0x7 > + add r0, r0, #4 /* SetShift */ > + > + clz r1, r3 /* WayShift */ > + add r4, r3, #1 /* NumWays */ > +1: sub r2, r2, #1 /* NumSets-- */ > + mov r3, r4 /* Temp = NumWays */ > +2: subs r3, r3, #1 /* Temp-- */ > + mov r5, r3, lsl r1 > + mov r6, r2, lsl r0 > + /* Reg = (Temp << WayShift) | (NumSets << SetShift) */ > + orr r5, r5, r6 > + mcr p15, 0, r5, c7, c6, 2 > + bgt 2b > + cmp r2, #0 > + bgt 1b > + dsb > + isb > + mov pc, lr > +ENDPROC(v7_invalidate_l1_npcmX50) This looks a lot, if not nearly the same thing as v7_invalidate_l1 which is already called by secondary_startup, can you see if you can re-use it directly? > + > +/* > + * MSM specific entry point for secondary CPUs. This provides > + * a "holding pen" into which all secondary cores are held until we're > + * ready for them to initialise. > + */ Assuming this was copied from a Qualcomm MSM routine, you may want to fix the comment, typo on "initialis. > +ENTRY(npcm7xx_secondary_startup) > + msr CPSR_c, #(SVC_MODE) Is there a BootROM or something that would not make the secondary cores start in supervisor mode? > + > + bl v7_invalidate_l1_npcmX50 > + /* disable vector table remapping */ > + mrc p15, 0,r0, c1, c0, 0 > + and r0, #0xffffdfff > + mcr p15, 0,r0, c1, c0, 0 > + > +#ifdef CONFIG_CACHE_L2X0 > + /* Enable L1 & L2 prefetch + Zero line */ > + mrc p15, 0, r0, c1, c0, 1 > + orr r0, r0, #(7 << 1) > + mcr p15, 0, r0, c1, c0, 1 > +#endif /* CONFIG_CACHE_L2X0 */ > + > + mrc p15, 0, r0, c0, c0, 5 > + and r0, r0, #15 > + adr r4, 1f > + ldmia r4, {r5, r6} > + sub r4, r4, r5 > + add r6, r6, r4 > + str r3,[r2] > + > +pen: ldr r7, [r6] > + cmp r7, r0 > + bne pen > + > + /* > + * we've been released from the holding pen: secondary_stack > + * should now contain the SVC stack for this core > + */ > + b secondary_startup > +ENDPROC(npcm7xx_secondary_startup) > + > + .align > +1: .long . > + .long pen_release > diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c > new file mode 100644 > index 000000000000..106dc62dd62b > --- /dev/null > +++ b/arch/arm/mach-npcm/npcm7xx.c > @@ -0,0 +1,34 @@ > +/* > + * Copyright (c) 2014 Nuvoton Technology corporation. > + * Copyright 2017 Google, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation;version 2 of the License. > + */ > + > +#include <linux/kernel.h> > +#include <linux/types.h> > +#include <asm/mach/arch.h> > +#include <asm/mach-types.h> > +#include <asm/mach/map.h> > +#include <asm/hardware/cache-l2x0.h> > + > +#define NPCM7XX_AUX_VAL (L310_AUX_CTRL_INSTR_PREFETCH | \ > + L310_AUX_CTRL_DATA_PREFETCH | \ > + L310_AUX_CTRL_NS_LOCKDOWN | \ > + L310_AUX_CTRL_CACHE_REPLACE_RR | \ > + L2C_AUX_CTRL_SHARED_OVERRIDE | \ > + L310_AUX_CTRL_FULL_LINE_ZERO) > + > +static const char *const npcm7xx_dt_match[] = { > + "nuvoton,npcm750", > + NULL > +}; > + > +DT_MACHINE_START(NPCM7XX_DT, "NPCMX50 Chip family") > + .atag_offset = 0x100, > + .dt_compat = npcm7xx_dt_match, > + .l2c_aux_val = NPCM7XX_AUX_VAL, > + .l2c_aux_mask = ~NPCM7XX_AUX_VAL, > +MACHINE_END > diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c > new file mode 100644 > index 000000000000..4b53adb467fc > --- /dev/null > +++ b/arch/arm/mach-npcm/platsmp.c > @@ -0,0 +1,168 @@ > +/* > + * Copyright (C) 2002 ARM Ltd. > + * Copyright (C) 2008 STMicroelctronics. > + * Copyright (C) 2009 ST-Ericsson. > + * Copyright 2017 Google, Inc. > + * > + * This file is based on arm realview platform > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#define pr_fmt(fmt) "PLATSMP: " fmt > + > +#include <linux/delay.h> > +#include <linux/device.h> > +#include <linux/smp.h> > +#include <linux/io.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/of_platform.h> > +#include <linux/of_address.h> > +#include <asm/cacheflush.h> > +#include <asm/smp.h> > +#include <asm/smp_plat.h> > +#include <asm/smp_scu.h> > + > +#define NPCM7XX_SCRPAD_REG 0x13c > + > +static void __iomem *gcr_base; > +static void __iomem *scu_base; > + > +/* This is called from headsmp.S to wakeup the secondary core */ > +extern void npcm7xx_secondary_startup(void); > +extern void npcm7xx_wakeup_z1(void); This routine is not called, was it for an early revision of the silicon, or is it for CPU hotplugging maybe? > + > +/* > + * Write pen_release in a way that is guaranteed to be visible to all > + * observers, irrespective of whether they're taking part in coherency > + * or not. This is necessary for the hotplug code to work reliably. > + */ > +static void npcm7xx_write_pen_release(int val) > +{ > + pen_release = val; > + /* write to pen_release must be visible to all observers. */ > + smp_wmb(); > + __cpuc_flush_dcache_area((void *) &pen_release, sizeof(pen_release)); > + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); > +} > + > +static DEFINE_SPINLOCK(boot_lock); > + > +static void npcm7xx_smp_secondary_init(unsigned int cpu) > +{ > + /* > + * let the primary processor know we're out of the > + * pen, then head off into the C entry point > + */ > + npcm7xx_write_pen_release(-1); > + > + /* > + * Synchronise with the boot thread. > + */ > + spin_lock(&boot_lock); > + spin_unlock(&boot_lock); > +} > + > +static int npcm7xx_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) > +{ > + unsigned long timeout; > + > + if (!gcr_base) > + return -EIO; > + > + /* > + * set synchronisation state between this boot processor > + * and the secondary one > + */ > + spin_lock(&boot_lock); > + > + /* > + * The secondary processor is waiting to be released from > + * the holding pen - release it, then wait for it to flag > + * that it has been released by resetting pen_release. > + */ > + npcm7xx_write_pen_release(cpu_logical_map(cpu)); > + iowrite32(virt_to_phys(npcm7xx_secondary_startup), > + gcr_base + NPCM7XX_SCRPAD_REG); Please use __pa_symbol here instead of virt_to_phys() since you are calling this against a kernel image symbol. > + /* make npcm7xx_secondary_startup visible to all observers. */ > + smp_rmb(); > + > + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); > + timeout = jiffies + (HZ * 1); > + while (time_before(jiffies, timeout)) { > + /* make sure we see any writes to pen_release. */ > + smp_rmb(); > + if (pen_release == -1) > + break; > + > + udelay(10); > + } > + > + /* > + * now the secondary core is starting up let it run its > + * calibrations, then wait for it to finish > + */ > + spin_unlock(&boot_lock); > + > + return pen_release != -1 ? -EIO : 0; > +} > + > + > +static void __init npcm7xx_wakeup_secondary(void) > +{ > + /* > + * write the address of secondary startup into the backup ram register > + * at offset 0x1FF4, then write the magic number 0xA1FEED01f to the > + * backup ram register at offset 0x1FF0, which is what boot rom code > + * is waiting for. This would wake up the secondary core from WFE > + */ The comment does not seem to match what you are doing. > + iowrite32(virt_to_phys(npcm7xx_secondary_startup), gcr_base + > + NPCM7XX_SCRPAD_REG); Same here please use __pa_symbol(). > + /* make sure npcm7xx_secondary_startup is seen by all observers. */ > + smp_wmb(); > + dsb_sev(); > + > + /* make sure write buffer is drained */ > + mb(); > +} > + > +static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus) > +{ > + struct device_node *gcr_np, *scu_np; > + > + gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr"); > + if (!gcr_np) { > + pr_err("no gcr device node\n"); > + return; > + } > + gcr_base = of_iomap(gcr_np, 0); > + if (!gcr_base) { > + pr_err("could not iomap gcr at: 0x%llx\n", gcr_base); > + return; > + } > + > + scu_np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); > + if (!scu_np) { > + pr_err("no scu device node\n"); > + return; > + } > + scu_base = of_iomap(scu_np, 0); > + if (!scu_base) { > + pr_err("could not iomap gcr at: 0x%llx\n", scu_base); > + return; > + } > + > + scu_enable(scu_base); > + npcm7xx_wakeup_secondary(); > +} > + > +static struct smp_operations npcm7xx_smp_ops __initdata = { > + .smp_prepare_cpus = npcm7xx_smp_prepare_cpus, > + .smp_boot_secondary = npcm7xx_smp_boot_secondary, > + .smp_secondary_init = npcm7xx_smp_secondary_init, > +}; Overall you have copied the realview pen hold/release mechanism and this is really frowned upon especially if you have a better way to control the bring-up of secondary cores, e.g: via writing a special word to a specific register, or setting a special address bit (e.g: bit 31 of the physical address | secondary_startup) or anything that acts as a "GO" signal of some sort. -- Florian ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 1/3] arm: npcm: add basic support for Nuvoton BMCs 2017-09-05 2:47 ` Florian Fainelli @ 2017-09-06 0:42 ` Brendan Higgins 0 siblings, 0 replies; 9+ messages in thread From: Brendan Higgins @ 2017-09-06 0:42 UTC (permalink / raw) To: linux-arm-kernel With the exception of one comment, which I have responded to below, I have addressed your comments in my new version of this patch: https://patchwork.kernel.org/patch/9914153/ On Mon, Sep 4, 2017 at 7:47 PM, Florian Fainelli <f.fainelli@gmail.com> wrote: ... >> + >> +ENTRY(v7_invalidate_l1_npcmX50) >> + mov r0, #0 >> + mcr p15, 0, r0, c7, c5, 0 /* invalidate I cache */ >> + mcr p15, 2, r0, c0, c0, 0 >> + mrc p15, 1, r0, c0, c0, 0 >> + >> + ldr r1, =0x7fff >> + and r2, r1, r0, lsr #13 >> + >> + ldr r1, =0x3ff >> + >> + and r3, r1, r0, lsr #3 /* NumWays - 1 */ >> + add r2, r2, #1 /* NumSets */ >> + >> + and r0, r0, #0x7 >> + add r0, r0, #4 /* SetShift */ >> + >> + clz r1, r3 /* WayShift */ >> + add r4, r3, #1 /* NumWays */ >> +1: sub r2, r2, #1 /* NumSets-- */ >> + mov r3, r4 /* Temp = NumWays */ >> +2: subs r3, r3, #1 /* Temp-- */ >> + mov r5, r3, lsl r1 >> + mov r6, r2, lsl r0 >> + /* Reg = (Temp << WayShift) | (NumSets << SetShift) */ >> + orr r5, r5, r6 >> + mcr p15, 0, r5, c7, c6, 2 >> + bgt 2b >> + cmp r2, #0 >> + bgt 1b >> + dsb >> + isb >> + mov pc, lr >> +ENDPROC(v7_invalidate_l1_npcmX50) > > This looks a lot, if not nearly the same thing as v7_invalidate_l1 which > is already called by secondary_startup, can you see if you can re-use it > directly? > >> + >> +/* >> + * MSM specific entry point for secondary CPUs. This provides >> + * a "holding pen" into which all secondary cores are held until we're >> + * ready for them to initialise. >> + */ > > Assuming this was copied from a Qualcomm MSM routine, you may want to > fix the comment, typo on "initialis. > >> +ENTRY(npcm7xx_secondary_startup) >> + msr CPSR_c, #(SVC_MODE) > > Is there a BootROM or something that would not make the secondary cores > start in supervisor mode? Unfortunately, yes; however, I was able to cut all of the other code out of npcm7xx_secondary_startup, so now it just puts the core in SVC mode and relies on secondary_startup to do all of the L1 cache invalidation. > >> + >> + bl v7_invalidate_l1_npcmX50 >> + /* disable vector table remapping */ >> + mrc p15, 0,r0, c1, c0, 0 >> + and r0, #0xffffdfff >> + mcr p15, 0,r0, c1, c0, 0 >> + >> +#ifdef CONFIG_CACHE_L2X0 >> + /* Enable L1 & L2 prefetch + Zero line */ >> + mrc p15, 0, r0, c1, c0, 1 >> + orr r0, r0, #(7 << 1) >> + mcr p15, 0, r0, c1, c0, 1 >> +#endif /* CONFIG_CACHE_L2X0 */ >> + >> + mrc p15, 0, r0, c0, c0, 5 >> + and r0, r0, #15 >> + adr r4, 1f >> + ldmia r4, {r5, r6} >> + sub r4, r4, r5 >> + add r6, r6, r4 >> + str r3,[r2] >> + >> +pen: ldr r7, [r6] >> + cmp r7, r0 >> + bne pen >> + ... ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 2/3] arm: dts: add Nuvoton NPCM750 device tree 2017-08-31 22:53 [PATCH v2 0/3] arm: npcm: add basic support for Nuvoton BMCs Brendan Higgins 2017-08-31 22:53 ` [PATCH v2 1/3] " Brendan Higgins @ 2017-08-31 22:53 ` Brendan Higgins 2017-09-04 14:24 ` Tomer Maimon 2017-08-31 22:54 ` [PATCH v2 3/3] MAINTAINERS: Add entry for the Nuvoton NPCM architecture Brendan Higgins 2 siblings, 1 reply; 9+ messages in thread From: Brendan Higgins @ 2017-08-31 22:53 UTC (permalink / raw) To: linux-arm-kernel Add a common device tree for all Nuvoton NPCM750 BMCs and a board specific device tree for the NPCM750 (Poleg) evaluation board. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> --- .../arm/cpu-enable-method/nuvoton,npcm7xx-smp | 42 +++++ .../devicetree/bindings/arm/npcm/npcm.txt | 6 + arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 59 +++++++ arch/arm/boot/dts/nuvoton-npcm750.dtsi | 177 +++++++++++++++++++++ include/dt-bindings/clock/nuvoton,npcm7xx-clks.h | 39 +++++ 5 files changed, 323 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clks.h diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp new file mode 100644 index 000000000000..e81f85b400cf --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp @@ -0,0 +1,42 @@ +========================================================= +Secondary CPU enable-method "nuvoton,npcm7xx-smp" binding +========================================================= + +To apply to all CPUs, a single "nuvoton,npcm7xx-smp" enable method should be +defined in the "cpus" node. + +Enable method name: "nuvoton,npcm7xx-smp" +Compatible machines: "nuvoton,npcm750" +Compatible CPUs: "arm,cortex-a9" +Related properties: (none) + +Note: +This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and +"nuvoton,npcm750-gcr". + +Example: + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm7xx-smp"; + + cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt new file mode 100644 index 000000000000..2d87d9ecea85 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt @@ -0,0 +1,6 @@ +NPCM Platforms Device Tree Bindings +----------------------------------- +NPCM750 SoC +Required root node properties: + - compatible = "nuvoton,npcm750"; + diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts new file mode 100644 index 000000000000..54df32cff21b --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts @@ -0,0 +1,59 @@ +/* + * DTS file for all NPCM750 SoCs + * + * Copyright 2012 Tomer Maimon <tomer.maimon@nuvoton.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "nuvoton-npcm750.dtsi" + +/ { + model = "Nuvoton npcm750 Development Board (Device Tree)"; + compatible = "nuvoton,npcm750"; + + chosen { + stdout-path = &serial3; + bootargs = "earlyprintk=serial,serial3,115200"; + }; + + memory { + reg = <0 0x40000000>; + }; + + cpus { + enable-method = "nuvoton,npcm7xx-smp"; + }; + + clk: clock-controller at f0801000 { + status = "okay"; + }; + + apb { + watchdog1: watchdog at f0009000 { + status = "okay"; + }; + + serial0: serial0 at f0001000 { + status = "okay"; + }; + + serial1: serial1 at f0002000 { + status = "okay"; + }; + + serial2: serial2 at f0003000 { + status = "okay"; + }; + + serial3: serial3 at f0004000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi new file mode 100644 index 000000000000..bca96b3ae9d3 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi @@ -0,0 +1,177 @@ +/* + * DTSi file for the NPCM750 SoC + * + * Copyright 2012 Tomer Maimon <tomer.maimon@nuvoton.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/nuvoton,npcm7xx-clks.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + gcr: gcr at f0800000 { + compatible = "nuvoton,npcm750-gcr", "syscon", + "simple-mfd"; + reg = <0xf0800000 0x1000>; + }; + + scu: scu at f03fe000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xf03fe000 0x1000>; + }; + + l2: l2-cache at f03fc000 { + compatible = "arm,pl310-cache"; + reg = <0xf03fc000 0x1000>; + interrupts = <0 21 4>; + cache-unified; + cache-level = <2>; + clocks = <&clk NPCM7XX_CLK_AXI>; + }; + + gic: interrupt-controller at f03ff000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf03ff000 0x1000>, + <0xf03fe100 0x100>; + }; + + clk: clock-controller at f0801000 { + compatible = "nuvoton,npcm750-clk"; + #clock-cells = <1>; + reg = <0xf0801000 0x1000>; + }; + + /* external clock signal rg1refck, supplied by the phy */ + clk-rg1refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + /* external clock signal rg2refck, supplied by the phy */ + clk-rg2refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk-xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + timer at f03fe600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf03fe600 0x20>; + interrupts = <1 13 0x304>; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + timer0: timer at f0000000 { + compatible = "nuvoton,npcm750-timer"; + interrupts = <0 32 4>; + reg = <0xf0000000 0x1000>; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + watchdog0: watchdog at f0008000 { + compatible = "nuvoton,npcm750-wdt"; + interrupts = <0 47 4>; + reg = <0xf0008000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + watchdog1: watchdog at f0009000 { + compatible = "nuvoton,npcm750-wdt"; + interrupts = <0 48 4>; + reg = <0xf0009000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + watchdog2: watchdog at f000a000 { + compatible = "nuvoton,npcm750-wdt"; + interrupts = <0 49 4>; + reg = <0xf000a000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + serial0: serial0 at f0001000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0001000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART_CORE>; + interrupts = <0 2 4>; + status = "disabled"; + }; + + serial1: serial1 at f0002000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0002000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART_CORE>; + interrupts = <0 3 4>; + status = "disabled"; + }; + + serial2: serial2 at f0003000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0003000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART_CORE>; + interrupts = <0 4 4>; + status = "disabled"; + }; + + serial3: serial3 at f0004000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0004000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART_CORE>; + interrupts = <0 5 4>; + status = "disabled"; + }; + }; +}; diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h new file mode 100644 index 000000000000..c69d3bbf7e42 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2016 Nuvoton Technologies, tali.perry at nuvoton.com + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + */ + +#ifndef _DT_BINDINGS_CLK_NPCM7XX_H +#define _DT_BINDINGS_CLK_NPCM7XX_H + +#define NPCM7XX_CLK_PLL0 0 +#define NPCM7XX_CLK_PLL1 1 +#define NPCM7XX_CLK_PLL2 2 +#define NPCM7XX_CLK_GFX 3 +#define NPCM7XX_CLK_APB1 4 +#define NPCM7XX_CLK_APB2 5 +#define NPCM7XX_CLK_APB3 6 +#define NPCM7XX_CLK_APB4 7 +#define NPCM7XX_CLK_APB5 8 +#define NPCM7XX_CLK_MC 9 +#define NPCM7XX_CLK_CPU 10 +#define NPCM7XX_CLK_SPI0 11 +#define NPCM7XX_CLK_SPI3 12 +#define NPCM7XX_CLK_SPIX 13 +#define NPCM7XX_CLK_UART_CORE 14 +#define NPCM7XX_CLK_TIMER 15 +#define NPCM7XX_CLK_HOST_UART 16 +#define NPCM7XX_CLK_MMC 17 +#define NPCM7XX_CLK_SDHC 18 +#define NPCM7XX_CLK_ADC 19 +#define NPCM7XX_CLK_GFX_MEM 20 +#define NPCM7XX_CLK_USB_BRIDGE 21 +#define NPCM7XX_CLK_AXI 22 +#define NPCM7XX_CLK_AHB 23 +#define NPCM7XX_CLK_EMC 24 +#define NPCM7XX_CLK_GMAC 25 + +#endif -- 2.14.1.581.gf28d330327-goog ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 2/3] arm: dts: add Nuvoton NPCM750 device tree 2017-08-31 22:53 ` [PATCH v2 2/3] arm: dts: add Nuvoton NPCM750 device tree Brendan Higgins @ 2017-09-04 14:24 ` Tomer Maimon 0 siblings, 0 replies; 9+ messages in thread From: Tomer Maimon @ 2017-09-04 14:24 UTC (permalink / raw) To: linux-arm-kernel On 1 September 2017 at 01:53, Brendan Higgins <brendanhiggins@google.com> wrote: > Add a common device tree for all Nuvoton NPCM750 BMCs and a board > specific device tree for the NPCM750 (Poleg) evaluation board. > > Signed-off-by: Brendan Higgins <brendanhiggins@google.com> > --- > .../arm/cpu-enable-method/nuvoton,npcm7xx-smp | 42 +++++ > .../devicetree/bindings/arm/npcm/npcm.txt | 6 + > arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 59 +++++++ > arch/arm/boot/dts/nuvoton-npcm750.dtsi | 177 +++++++++++++++++++++ > include/dt-bindings/clock/nuvoton,npcm7xx-clks.h | 39 +++++ > 5 files changed, 323 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp > create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt > create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts > create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi > create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clks.h > > diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp > new file mode 100644 > index 000000000000..e81f85b400cf > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp > @@ -0,0 +1,42 @@ > +========================================================= > +Secondary CPU enable-method "nuvoton,npcm7xx-smp" binding > +========================================================= > + > +To apply to all CPUs, a single "nuvoton,npcm7xx-smp" enable method should be > +defined in the "cpus" node. > + > +Enable method name: "nuvoton,npcm7xx-smp" > +Compatible machines: "nuvoton,npcm750" > +Compatible CPUs: "arm,cortex-a9" > +Related properties: (none) > + > +Note: > +This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and > +"nuvoton,npcm750-gcr". > + > +Example: > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + enable-method = "nuvoton,npcm7xx-smp"; > + > + cpu at 0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + clocks = <&clk NPCM7XX_CLK_CPU>; > + clock-names = "clk_cpu"; > + reg = <0>; > + next-level-cache = <&L2>; > + }; > + > + cpu at 1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + clocks = <&clk NPCM7XX_CLK_CPU>; > + clock-names = "clk_cpu"; > + reg = <1>; > + next-level-cache = <&L2>; > + }; > + }; > + > diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt > new file mode 100644 > index 000000000000..2d87d9ecea85 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt > @@ -0,0 +1,6 @@ > +NPCM Platforms Device Tree Bindings > +----------------------------------- > +NPCM750 SoC > +Required root node properties: > + - compatible = "nuvoton,npcm750"; > + > diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts > new file mode 100644 > index 000000000000..54df32cff21b > --- /dev/null > +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts > @@ -0,0 +1,59 @@ > +/* > + * DTS file for all NPCM750 SoCs > + * > + * Copyright 2012 Tomer Maimon <tomer.maimon@nuvoton.com> > + * > + * The code contained herein is licensed under the GNU General Public > + * License. You may obtain a copy of the GNU General Public License > + * Version 2 or later at the following locations: > + * > + * http://www.opensource.org/licenses/gpl-license.html > + * http://www.gnu.org/copyleft/gpl.html > + */ > + > +/dts-v1/; > +#include "nuvoton-npcm750.dtsi" > + > +/ { > + model = "Nuvoton npcm750 Development Board (Device Tree)"; > + compatible = "nuvoton,npcm750"; > + > + chosen { > + stdout-path = &serial3; > + bootargs = "earlyprintk=serial,serial3,115200"; > + }; > + > + memory { > + reg = <0 0x40000000>; > + }; > + > + cpus { > + enable-method = "nuvoton,npcm7xx-smp"; > + }; > + > + clk: clock-controller at f0801000 { > + status = "okay"; > + }; > + > + apb { > + watchdog1: watchdog at f0009000 { > + status = "okay"; > + }; > + > + serial0: serial0 at f0001000 { > + status = "okay"; > + }; > + > + serial1: serial1 at f0002000 { > + status = "okay"; > + }; > + > + serial2: serial2 at f0003000 { > + status = "okay"; > + }; > + > + serial3: serial3 at f0004000 { > + status = "okay"; > + }; > + }; > +}; > diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi > new file mode 100644 > index 000000000000..bca96b3ae9d3 > --- /dev/null > +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi > @@ -0,0 +1,177 @@ > +/* > + * DTSi file for the NPCM750 SoC > + * > + * Copyright 2012 Tomer Maimon <tomer.maimon@nuvoton.com> > + * > + * The code contained herein is licensed under the GNU General Public > + * License. You may obtain a copy of the GNU General Public License > + * Version 2 or later at the following locations: > + * > + * http://www.opensource.org/licenses/gpl-license.html > + * http://www.gnu.org/copyleft/gpl.html > + */ > + > +#include "skeleton.dtsi" > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/clock/nuvoton,npcm7xx-clks.h> > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + interrupt-parent = <&gic>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu at 0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + clocks = <&clk NPCM7XX_CLK_CPU>; > + clock-names = "clk_cpu"; > + reg = <0>; > + next-level-cache = <&l2>; > + }; > + > + cpu at 1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + clocks = <&clk NPCM7XX_CLK_CPU>; > + clock-names = "clk_cpu"; > + reg = <1>; > + next-level-cache = <&l2>; > + }; > + }; > + > + gcr: gcr at f0800000 { > + compatible = "nuvoton,npcm750-gcr", "syscon", > + "simple-mfd"; > + reg = <0xf0800000 0x1000>; > + }; > + > + scu: scu at f03fe000 { > + compatible = "arm,cortex-a9-scu"; > + reg = <0xf03fe000 0x1000>; > + }; > + > + l2: l2-cache at f03fc000 { > + compatible = "arm,pl310-cache"; > + reg = <0xf03fc000 0x1000>; > + interrupts = <0 21 4>; > + cache-unified; > + cache-level = <2>; > + clocks = <&clk NPCM7XX_CLK_AXI>; > + }; > + > + gic: interrupt-controller at f03ff000 { > + compatible = "arm,cortex-a9-gic"; > + interrupt-controller; > + #interrupt-cells = <3>; > + reg = <0xf03ff000 0x1000>, > + <0xf03fe100 0x100>; > + }; > + > + clk: clock-controller at f0801000 { > + compatible = "nuvoton,npcm750-clk"; > + #clock-cells = <1>; > + reg = <0xf0801000 0x1000>; > + }; > + > + /* external clock signal rg1refck, supplied by the phy */ > + clk-rg1refck { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <125000000>; > + }; > + > + /* external clock signal rg2refck, supplied by the phy */ > + clk-rg2refck { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <125000000>; > + }; > + > + clk-xin { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <50000000>; > + }; > + > + timer at f03fe600 { > + compatible = "arm,cortex-a9-twd-timer"; > + reg = <0xf03fe600 0x20>; > + interrupts = <1 13 0x304>; > + clocks = <&clk NPCM7XX_CLK_TIMER>; > + }; > + > + apb { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "simple-bus"; > + interrupt-parent = <&gic>; > + ranges; > + > + timer0: timer at f0000000 { > + compatible = "nuvoton,npcm750-timer"; > + interrupts = <0 32 4>; > + reg = <0xf0000000 0x1000>; > + clocks = <&clk NPCM7XX_CLK_TIMER>; > + }; > + > + watchdog0: watchdog at f0008000 { > + compatible = "nuvoton,npcm750-wdt"; > + interrupts = <0 47 4>; > + reg = <0xf0008000 0x1000>; > + status = "disabled"; > + clocks = <&clk NPCM7XX_CLK_TIMER>; > + }; > + > + watchdog1: watchdog at f0009000 { > + compatible = "nuvoton,npcm750-wdt"; > + interrupts = <0 48 4>; > + reg = <0xf0009000 0x1000>; > + status = "disabled"; > + clocks = <&clk NPCM7XX_CLK_TIMER>; > + }; > + > + watchdog2: watchdog at f000a000 { > + compatible = "nuvoton,npcm750-wdt"; > + interrupts = <0 49 4>; > + reg = <0xf000a000 0x1000>; > + status = "disabled"; > + clocks = <&clk NPCM7XX_CLK_TIMER>; > + }; > + > + serial0: serial0 at f0001000 { > + compatible = "nuvoton,npcm750-uart"; > + reg = <0xf0001000 0x1000>; > + clocks = <&clk NPCM7XX_CLK_UART_CORE>; > + interrupts = <0 2 4>; > + status = "disabled"; > + }; > + > + serial1: serial1 at f0002000 { > + compatible = "nuvoton,npcm750-uart"; > + reg = <0xf0002000 0x1000>; > + clocks = <&clk NPCM7XX_CLK_UART_CORE>; > + interrupts = <0 3 4>; > + status = "disabled"; > + }; > + > + serial2: serial2 at f0003000 { > + compatible = "nuvoton,npcm750-uart"; > + reg = <0xf0003000 0x1000>; > + clocks = <&clk NPCM7XX_CLK_UART_CORE>; > + interrupts = <0 4 4>; > + status = "disabled"; > + }; > + > + serial3: serial3 at f0004000 { > + compatible = "nuvoton,npcm750-uart"; > + reg = <0xf0004000 0x1000>; > + clocks = <&clk NPCM7XX_CLK_UART_CORE>; > + interrupts = <0 5 4>; > + status = "disabled"; > + }; > + }; > +}; > diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h > new file mode 100644 > index 000000000000..c69d3bbf7e42 > --- /dev/null > +++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h > @@ -0,0 +1,39 @@ > +/* > + * Copyright (C) 2016 Nuvoton Technologies, tali.perry at nuvoton.com > + * > + * This software is licensed under the terms of the GNU General Public > + * License version 2, as published by the Free Software Foundation, and > + * may be copied, distributed, and modified under those terms. > + */ > + > +#ifndef _DT_BINDINGS_CLK_NPCM7XX_H > +#define _DT_BINDINGS_CLK_NPCM7XX_H > + > +#define NPCM7XX_CLK_PLL0 0 > +#define NPCM7XX_CLK_PLL1 1 > +#define NPCM7XX_CLK_PLL2 2 > +#define NPCM7XX_CLK_GFX 3 > +#define NPCM7XX_CLK_APB1 4 > +#define NPCM7XX_CLK_APB2 5 > +#define NPCM7XX_CLK_APB3 6 > +#define NPCM7XX_CLK_APB4 7 > +#define NPCM7XX_CLK_APB5 8 > +#define NPCM7XX_CLK_MC 9 > +#define NPCM7XX_CLK_CPU 10 > +#define NPCM7XX_CLK_SPI0 11 > +#define NPCM7XX_CLK_SPI3 12 > +#define NPCM7XX_CLK_SPIX 13 > +#define NPCM7XX_CLK_UART_CORE 14 > +#define NPCM7XX_CLK_TIMER 15 > +#define NPCM7XX_CLK_HOST_UART 16 > +#define NPCM7XX_CLK_MMC 17 > +#define NPCM7XX_CLK_SDHC 18 > +#define NPCM7XX_CLK_ADC 19 > +#define NPCM7XX_CLK_GFX_MEM 20 > +#define NPCM7XX_CLK_USB_BRIDGE 21 > +#define NPCM7XX_CLK_AXI 22 > +#define NPCM7XX_CLK_AHB 23 > +#define NPCM7XX_CLK_EMC 24 > +#define NPCM7XX_CLK_GMAC 25 > + > +#endif > -- > 2.14.1.581.gf28d330327-goog > Reviewed-by: Tomer Maimon <tmaimon77@gmail.com> Tested-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> Tested-by: Avi Fishman <avifishman70@gmail.com> ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 3/3] MAINTAINERS: Add entry for the Nuvoton NPCM architecture 2017-08-31 22:53 [PATCH v2 0/3] arm: npcm: add basic support for Nuvoton BMCs Brendan Higgins 2017-08-31 22:53 ` [PATCH v2 1/3] " Brendan Higgins 2017-08-31 22:53 ` [PATCH v2 2/3] arm: dts: add Nuvoton NPCM750 device tree Brendan Higgins @ 2017-08-31 22:54 ` Brendan Higgins 2017-09-04 14:25 ` Tomer Maimon 2 siblings, 1 reply; 9+ messages in thread From: Brendan Higgins @ 2017-08-31 22:54 UTC (permalink / raw) To: linux-arm-kernel Add maintainers and reviewers for the Nuvoton NPCM architecture. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> --- MAINTAINERS | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 44cb004c765d..67064bf11904 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1598,6 +1598,19 @@ F: drivers/pinctrl/nomadik/ F: drivers/i2c/busses/i2c-nomadik.c T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git +ARM/NUVOTON NPCM ARCHITECTURE +M: Avi Fishman <avifishman70@gmail.com> +M: Tomer Maimon <tmaimon77@gmail.com> +R: Brendan Higgins <brendanhiggins@google.com> +R: Rick Altherr <raltherr@google.com> +L: openbmc at lists.ozlabs.org (moderated for non-subscribers) +S: Maintained +F: arch/arm/mach-npcm/ +F: arch/arm/boot/dts/nuvoton-npcm* +F: include/dt-bindings/clock/nuvoton,npcm7xx-clks.h +F: drivers/*/*npcm* +F: Documentation/*/*npcm* + ARM/NUVOTON W90X900 ARM ARCHITECTURE M: Wan ZongShun <mcuos.com@gmail.com> L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers) -- 2.14.1.581.gf28d330327-goog ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 3/3] MAINTAINERS: Add entry for the Nuvoton NPCM architecture 2017-08-31 22:54 ` [PATCH v2 3/3] MAINTAINERS: Add entry for the Nuvoton NPCM architecture Brendan Higgins @ 2017-09-04 14:25 ` Tomer Maimon 0 siblings, 0 replies; 9+ messages in thread From: Tomer Maimon @ 2017-09-04 14:25 UTC (permalink / raw) To: linux-arm-kernel On 1 September 2017 at 01:54, Brendan Higgins <brendanhiggins@google.com> wrote: > Add maintainers and reviewers for the Nuvoton NPCM architecture. > > Signed-off-by: Brendan Higgins <brendanhiggins@google.com> > --- > MAINTAINERS | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 44cb004c765d..67064bf11904 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1598,6 +1598,19 @@ F: drivers/pinctrl/nomadik/ > F: drivers/i2c/busses/i2c-nomadik.c > T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git > > +ARM/NUVOTON NPCM ARCHITECTURE > +M: Avi Fishman <avifishman70@gmail.com> > +M: Tomer Maimon <tmaimon77@gmail.com> > +R: Brendan Higgins <brendanhiggins@google.com> > +R: Rick Altherr <raltherr@google.com> > +L: openbmc at lists.ozlabs.org (moderated for non-subscribers) > +S: Maintained > +F: arch/arm/mach-npcm/ > +F: arch/arm/boot/dts/nuvoton-npcm* > +F: include/dt-bindings/clock/nuvoton,npcm7xx-clks.h > +F: drivers/*/*npcm* > +F: Documentation/*/*npcm* > + > ARM/NUVOTON W90X900 ARM ARCHITECTURE > M: Wan ZongShun <mcuos.com@gmail.com> > L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers) > -- > 2.14.1.581.gf28d330327-goog > Reviewed-by: Tomer Maimon <tmaimon77@gmail.com> Tested-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> Tested-by: Avi Fishman <avifishman70@gmail.com> ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-09-06 0:42 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-08-31 22:53 [PATCH v2 0/3] arm: npcm: add basic support for Nuvoton BMCs Brendan Higgins 2017-08-31 22:53 ` [PATCH v2 1/3] " Brendan Higgins 2017-09-04 14:24 ` Tomer Maimon 2017-09-05 2:47 ` Florian Fainelli 2017-09-06 0:42 ` Brendan Higgins 2017-08-31 22:53 ` [PATCH v2 2/3] arm: dts: add Nuvoton NPCM750 device tree Brendan Higgins 2017-09-04 14:24 ` Tomer Maimon 2017-08-31 22:54 ` [PATCH v2 3/3] MAINTAINERS: Add entry for the Nuvoton NPCM architecture Brendan Higgins 2017-09-04 14:25 ` Tomer Maimon
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