[PATCH v2 5/5] clk/exynos5420: assign sclk_pixel id to pixel clock divider

[r.sh.open@gmail.com (Rahul Sharma)]

On 24 August 2013 01:32, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Hi Rahul,
>
> On Friday 23 of August 2013 12:27:58 Rahul Sharma wrote:
>> sclk_pixel is used to represent pixel clock divider on all exynos
>> SoCs not as a gate clock. It is queried in driver to pass as the
>> parent to hdmi clock while switching between parents. A new ID can
>> be asssigned Pixel gate clock which is currently not in use. Pixel
>> clock gate is default 'on'.
>
> This doesn't sound like a correct assumption, especially if you recall how
> common clock framework works - it disables any unclaimed clock
> automatically. Also we might want to support gating from power management
> reasons.
>
> IMHO you should simply export the dout_hdmi_pixel clock, keeping the
> original sclk_pixel exported as well.
>

Hi Tomasz,

Yea correct. I will export the divider clock and let hdmi driver use that
to pass as parent opf mout_pixel.

Regards,
Rahul Sharma.

> Best regards,
> Tomasz
>