From: "Nicholas Piggin" <npiggin@gmail.com>
To: "David Howells" <dhowells@redhat.com>,
"Linus Torvalds" <torvalds@linux-foundation.org>
Cc: "Mateusz Guzik" <mjguzik@gmail.com>,
"linux-arch" <linux-arch@vger.kernel.org>,
"Catalin Marinas" <catalin.marinas@arm.com>,
"Will Deacon" <will@kernel.org>,
"Michael Ellerman" <mpe@ellerman.id.au>, <tony.luck@intel.com>,
<viro@zeniv.linux.org.uk>, <linux-fsdevel@vger.kernel.org>,
"Jan Glauber" <jan.glauber@gmail.com>,
"linuxppc-dev" <linuxppc-dev@lists.ozlabs.org>,
"Linux ARM" <linux-arm-kernel@lists.infradead.org>
Subject: Re: Memory transaction instructions
Date: Thu, 19 Jan 2023 11:41:57 +1000 [thread overview]
Message-ID: <CPVS9PAXZRPK.3HFH2LTB662XP@bobo> (raw)
In-Reply-To: <2496131.1674032743@warthog.procyon.org.uk>
On Wed Jan 18, 2023 at 7:05 PM AEST, David Howells wrote:
> Linus Torvalds <torvalds@linux-foundation.org> wrote:
>
> > And for the kernel, where we don't have bad locking, and where we
> > actually use fine-grained locks that are _near_ the data that we are
> > locking (the lockref of the dcache is obviously one example of that,
> > but the skbuff queue you mention is almost certainly exactly the same
> > situation): the lock is right by the data that the lock protects, and
> > the "shared lock cacheline" model simply does not work. You'll bounce
> > the data, and most likely you'll also touch the same lock cacheline
> > too.
>
> Yeah. The reason I was actually wondering about them was if it would be
> possible to avoid the requirement to disable interrupts/softirqs to, say,
> modify the skbuff queue. On some arches actually disabling irqs is quite a
> heavy operation (I think this is/was true on ppc64, for example; it certainly
> was on frv) and it was necessary to "emulate" the disablement.
Not too bad on modern ppc64. Changing MSR in general has to flush the
pipe and even re-fetch, because it can alter memory translation among
other things, so it was heavy. Everything we support has a lightweight
MSR change that just modifies the interrupt enable bit and only needs
minor serialisation (although we still have that software-irq-disable
thing which avoids the heavy MSR problem on old CPUs).
Thanks,
Nick
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next prev parent reply other threads:[~2023-01-19 1:43 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CAGudoHHx0Nqg6DE70zAVA75eV-HXfWyhVMWZ-aSeOofkA_=WdA@mail.gmail.com>
2023-01-13 0:13 ` lockref scalability on x86-64 vs cpu_relax Linus Torvalds
2023-01-13 0:30 ` Luck, Tony
2023-01-13 0:45 ` Linus Torvalds
2023-01-13 7:55 ` ia64 removal (was: Re: lockref scalability on x86-64 vs cpu_relax) Ard Biesheuvel
2023-01-13 16:17 ` Luck, Tony
2023-01-13 20:49 ` Jessica Clarke
2023-01-13 21:03 ` Luck, Tony
2023-01-13 21:04 ` Jessica Clarke
2023-01-13 21:05 ` John Paul Adrian Glaubitz
2023-01-13 23:25 ` Ard Biesheuvel
2023-01-14 11:24 ` Sedat Dilek
2023-01-14 11:28 ` Sedat Dilek
2023-01-15 0:27 ` Matthew Wilcox
2023-01-15 12:04 ` Sedat Dilek
2023-01-16 9:42 ` John Paul Adrian Glaubitz
2023-01-16 9:41 ` John Paul Adrian Glaubitz
2023-01-16 13:28 ` Matthew Wilcox
2023-01-16 9:40 ` John Paul Adrian Glaubitz
2023-01-16 9:37 ` John Paul Adrian Glaubitz
2023-01-16 9:32 ` John Paul Adrian Glaubitz
2023-01-16 10:09 ` Ard Biesheuvel
2023-01-13 1:12 ` lockref scalability on x86-64 vs cpu_relax Mateusz Guzik
2023-01-13 4:08 ` Linus Torvalds
2023-01-13 9:46 ` Will Deacon
2023-01-13 3:20 ` Nicholas Piggin
2023-01-13 4:15 ` Linus Torvalds
2023-01-13 5:36 ` Nicholas Piggin
[not found] ` <1966767.1673878095@warthog.procyon.org.uk>
2023-01-16 15:09 ` Memory transaction instructions Matthew Wilcox
2023-01-16 16:59 ` Linus Torvalds
2023-01-18 9:05 ` David Howells
2023-01-19 1:41 ` Nicholas Piggin [this message]
2023-01-13 10:23 ` lockref scalability on x86-64 vs cpu_relax Peter Zijlstra
2023-01-13 18:44 ` [PATCH] lockref: stop doing cpu_relax in the cmpxchg loop Mateusz Guzik
2023-01-13 21:47 ` Luck, Tony
2023-01-13 23:31 ` Linus Torvalds
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