* [PATCH v7 1/5] dt-bindings: crypto: Add Tegra Security Engine
2024-04-03 10:00 [PATCH v7 0/5] Add Tegra Security Engine driver Akhil R
@ 2024-04-03 10:00 ` Akhil R
2024-04-03 10:00 ` [PATCH v7 2/5] gpu: host1x: Add Tegra SE to SID table Akhil R
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Akhil R @ 2024-04-03 10:00 UTC (permalink / raw)
To: herbert, davem, robh, krzysztof.kozlowski+dt, conor+dt,
thierry.reding, jonathanh, catalin.marinas, will, mperttunen,
airlied, daniel, linux-crypto, devicetree, linux-tegra,
linux-kernel, linux-arm-kernel, dri-devel
Cc: Akhil R, Krzysztof Kozlowski
Add DT binding document for Tegra Security Engine.
The AES and HASH algorithms are handled independently by separate
engines within the Security Engine. These engines are registered
as two separate crypto engine drivers.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../crypto/nvidia,tegra234-se-aes.yaml | 52 +++++++++++++++++++
.../crypto/nvidia,tegra234-se-hash.yaml | 52 +++++++++++++++++++
2 files changed, 104 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-aes.yaml
create mode 100644 Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-hash.yaml
diff --git a/Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-aes.yaml b/Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-aes.yaml
new file mode 100644
index 000000000000..cb47ae2889b6
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-aes.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/nvidia,tegra234-se-aes.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Security Engine for AES algorithms
+
+description:
+ The Tegra Security Engine accelerates the following AES encryption/decryption
+ algorithms - AES-ECB, AES-CBC, AES-OFB, AES-XTS, AES-CTR, AES-GCM, AES-CCM,
+ AES-CMAC
+
+maintainers:
+ - Akhil R <akhilrajeev@nvidia.com>
+
+properties:
+ compatible:
+ const: nvidia,tegra234-se-aes
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ dma-coherent: true
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/memory/tegra234-mc.h>
+ #include <dt-bindings/clock/tegra234-clock.h>
+
+ crypto@15820000 {
+ compatible = "nvidia,tegra234-se-aes";
+ reg = <0x15820000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_SE>;
+ iommus = <&smmu TEGRA234_SID_SES_SE1>;
+ dma-coherent;
+ };
+...
diff --git a/Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-hash.yaml b/Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-hash.yaml
new file mode 100644
index 000000000000..f57ef10645e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-hash.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/nvidia,tegra234-se-hash.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Security Engine for HASH algorithms
+
+description:
+ The Tegra Security HASH Engine accelerates the following HASH functions -
+ SHA1, SHA224, SHA256, SHA384, SHA512, SHA3-224, SHA3-256, SHA3-384, SHA3-512
+ HMAC(SHA224), HMAC(SHA256), HMAC(SHA384), HMAC(SHA512)
+
+maintainers:
+ - Akhil R <akhilrajeev@nvidia.com>
+
+properties:
+ compatible:
+ const: nvidia,tegra234-se-hash
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ dma-coherent: true
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/memory/tegra234-mc.h>
+ #include <dt-bindings/clock/tegra234-clock.h>
+
+ crypto@15840000 {
+ compatible = "nvidia,tegra234-se-hash";
+ reg = <0x15840000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_SE>;
+ iommus = <&smmu TEGRA234_SID_SES_SE2>;
+ dma-coherent;
+ };
+...
--
2.43.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v7 2/5] gpu: host1x: Add Tegra SE to SID table
2024-04-03 10:00 [PATCH v7 0/5] Add Tegra Security Engine driver Akhil R
2024-04-03 10:00 ` [PATCH v7 1/5] dt-bindings: crypto: Add Tegra Security Engine Akhil R
@ 2024-04-03 10:00 ` Akhil R
2024-04-03 10:00 ` [PATCH v7 4/5] arm64: defconfig: Enable Tegra Security Engine Akhil R
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Akhil R @ 2024-04-03 10:00 UTC (permalink / raw)
To: herbert, davem, robh, krzysztof.kozlowski+dt, conor+dt,
thierry.reding, jonathanh, catalin.marinas, will, mperttunen,
airlied, daniel, linux-crypto, devicetree, linux-tegra,
linux-kernel, linux-arm-kernel, dri-devel
Cc: Akhil R
Add Tegra Security Engine details to the SID table in host1x driver.
These entries are required to be in place to configure the stream ID
for SE. Register writes to stream ID registers fail otherwise.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Acked-by: Mikko Perttunen <mperttunen@nvidia.com>
---
drivers/gpu/host1x/dev.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 89983d7d73ca..3a0aaa68ac8d 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -215,6 +215,30 @@ static const struct host1x_info host1x07_info = {
* and firmware stream ID in the MMIO path table.
*/
static const struct host1x_sid_entry tegra234_sid_table[] = {
+ {
+ /* SE2 MMIO */
+ .base = 0x1658,
+ .offset = 0x90,
+ .limit = 0x90
+ },
+ {
+ /* SE4 MMIO */
+ .base = 0x1660,
+ .offset = 0x90,
+ .limit = 0x90
+ },
+ {
+ /* SE2 channel */
+ .base = 0x1738,
+ .offset = 0x90,
+ .limit = 0x90
+ },
+ {
+ /* SE4 channel */
+ .base = 0x1740,
+ .offset = 0x90,
+ .limit = 0x90
+ },
{
/* VIC channel */
.base = 0x17b8,
--
2.43.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v7 4/5] arm64: defconfig: Enable Tegra Security Engine
2024-04-03 10:00 [PATCH v7 0/5] Add Tegra Security Engine driver Akhil R
2024-04-03 10:00 ` [PATCH v7 1/5] dt-bindings: crypto: Add Tegra Security Engine Akhil R
2024-04-03 10:00 ` [PATCH v7 2/5] gpu: host1x: Add Tegra SE to SID table Akhil R
@ 2024-04-03 10:00 ` Akhil R
2024-04-03 10:00 ` [PATCH v7 5/5] arm64: tegra: Add Tegra Security Engine DT nodes Akhil R
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Akhil R @ 2024-04-03 10:00 UTC (permalink / raw)
To: herbert, davem, robh, krzysztof.kozlowski+dt, conor+dt,
thierry.reding, jonathanh, catalin.marinas, will, mperttunen,
airlied, daniel, linux-crypto, devicetree, linux-tegra,
linux-kernel, linux-arm-kernel, dri-devel
Cc: Akhil R
Enable Tegra Security Engine which can accelerate various
AES and HASH algorithms on supported hardware.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 2c30d617e180..af6f247c497c 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1647,6 +1647,7 @@ CONFIG_CRYPTO_DEV_FSL_CAAM=m
CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m
CONFIG_CRYPTO_DEV_QCE=m
CONFIG_CRYPTO_DEV_QCOM_RNG=m
+CONFIG_CRYPTO_DEV_TEGRA=m
CONFIG_CRYPTO_DEV_CCREE=m
CONFIG_CRYPTO_DEV_HISI_SEC2=m
CONFIG_CRYPTO_DEV_HISI_ZIP=m
--
2.43.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v7 5/5] arm64: tegra: Add Tegra Security Engine DT nodes
2024-04-03 10:00 [PATCH v7 0/5] Add Tegra Security Engine driver Akhil R
` (2 preceding siblings ...)
2024-04-03 10:00 ` [PATCH v7 4/5] arm64: defconfig: Enable Tegra Security Engine Akhil R
@ 2024-04-03 10:00 ` Akhil R
2024-04-12 7:31 ` [PATCH v7 0/5] Add Tegra Security Engine driver Herbert Xu
2024-04-26 15:32 ` (subset) " Thierry Reding
5 siblings, 0 replies; 8+ messages in thread
From: Akhil R @ 2024-04-03 10:00 UTC (permalink / raw)
To: herbert, davem, robh, krzysztof.kozlowski+dt, conor+dt,
thierry.reding, jonathanh, catalin.marinas, will, mperttunen,
airlied, daniel, linux-crypto, devicetree, linux-tegra,
linux-kernel, linux-arm-kernel, dri-devel
Cc: Akhil R
Add device tree nodes for Tegra AES and HASH engines.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 78cbfdd98dd1..f2e2d8d6845b 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -4406,6 +4406,22 @@ nvdec@15480000 {
*/
status = "disabled";
};
+
+ crypto@15820000 {
+ compatible = "nvidia,tegra234-se-aes";
+ reg = <0x00 0x15820000 0x00 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_SE>;
+ iommus = <&smmu_niso1 TEGRA234_SID_SES_SE1>;
+ dma-coherent;
+ };
+
+ crypto@15840000 {
+ compatible = "nvidia,tegra234-se-hash";
+ reg = <0x00 0x15840000 0x00 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_SE>;
+ iommus = <&smmu_niso1 TEGRA234_SID_SES_SE2>;
+ dma-coherent;
+ };
};
pcie@140a0000 {
--
2.43.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v7 0/5] Add Tegra Security Engine driver
2024-04-03 10:00 [PATCH v7 0/5] Add Tegra Security Engine driver Akhil R
` (3 preceding siblings ...)
2024-04-03 10:00 ` [PATCH v7 5/5] arm64: tegra: Add Tegra Security Engine DT nodes Akhil R
@ 2024-04-12 7:31 ` Herbert Xu
2024-04-26 15:32 ` (subset) " Thierry Reding
5 siblings, 0 replies; 8+ messages in thread
From: Herbert Xu @ 2024-04-12 7:31 UTC (permalink / raw)
To: Akhil R
Cc: davem, robh, krzysztof.kozlowski+dt, conor+dt, thierry.reding,
jonathanh, catalin.marinas, will, mperttunen, airlied, daniel,
linux-crypto, devicetree, linux-tegra, linux-kernel,
linux-arm-kernel, dri-devel
On Wed, Apr 03, 2024 at 03:30:34PM +0530, Akhil R wrote:
> Add support for Tegra Security Engine which can accelerates various
> crypto algorithms. The Engine has two separate instances within for
> AES and HASH algorithms respectively.
>
> The driver registers two crypto engines - one for AES and another for
> HASH algorithms and these operate independently and both uses the host1x
> bus. Additionally, it provides hardware-assisted key protection for up to
> 15 symmetric keys which it can use for the cipher operations.
>
> v6->v7:
> * Move fallback_tfm and fallback_req to end of struct
> * Set reqsize and statesize based on fallback_tfm
> * Remove ofb(aes)
> v5->v6:
> * Move copy/pase of intermediate results in export()/import() to
> 'update()' callback for CMAC as well.
> * Check for rctx size when using fallback alg.
> * Updated blocksizes to align with generic implementation
> * Combined GCM and CCM init into aead_cra_init
> * Updates to handle invalid cases better
> * Reduce log levels for invalid cases to dev_dbg
> v4->v5:
> * Move copy/paste of intermediate results in export()/import() to
> 'update()' callback
> v3->v4:
> * Remove unused header in bindings doc.
> * Update commit message in host1x change.
> * Fix test bot warning.
> v2->v3:
> * Update compatible in driver and device trees.
> * Remove extra new lines and symbols in binding doc.
> v1->v2:
> * Update probe errors with 'dev_err_probe'.
> * Clean up function prototypes and redundant prints.
> * Remove readl/writel wrappers.
> * Fix test bot warnings.
>
>
> Akhil R (5):
> dt-bindings: crypto: Add Tegra Security Engine
> gpu: host1x: Add Tegra SE to SID table
> crypto: tegra: Add Tegra Security Engine driver
> arm64: defconfig: Enable Tegra Security Engine
> arm64: tegra: Add Tegra Security Engine DT nodes
>
> .../crypto/nvidia,tegra234-se-aes.yaml | 52 +
> .../crypto/nvidia,tegra234-se-hash.yaml | 52 +
> MAINTAINERS | 5 +
> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 16 +
> arch/arm64/configs/defconfig | 1 +
> drivers/crypto/Kconfig | 8 +
> drivers/crypto/Makefile | 1 +
> drivers/crypto/tegra/Makefile | 9 +
> drivers/crypto/tegra/tegra-se-aes.c | 1933 +++++++++++++++++
> drivers/crypto/tegra/tegra-se-hash.c | 1060 +++++++++
> drivers/crypto/tegra/tegra-se-key.c | 156 ++
> drivers/crypto/tegra/tegra-se-main.c | 439 ++++
> drivers/crypto/tegra/tegra-se.h | 560 +++++
> drivers/gpu/host1x/dev.c | 24 +
> 14 files changed, 4316 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-aes.yaml
> create mode 100644 Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-hash.yaml
> create mode 100644 drivers/crypto/tegra/Makefile
> create mode 100644 drivers/crypto/tegra/tegra-se-aes.c
> create mode 100644 drivers/crypto/tegra/tegra-se-hash.c
> create mode 100644 drivers/crypto/tegra/tegra-se-key.c
> create mode 100644 drivers/crypto/tegra/tegra-se-main.c
> create mode 100644 drivers/crypto/tegra/tegra-se.h
>
> --
> 2.43.2
All applied. Thanks.
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: (subset) [PATCH v7 0/5] Add Tegra Security Engine driver
2024-04-03 10:00 [PATCH v7 0/5] Add Tegra Security Engine driver Akhil R
` (4 preceding siblings ...)
2024-04-12 7:31 ` [PATCH v7 0/5] Add Tegra Security Engine driver Herbert Xu
@ 2024-04-26 15:32 ` Thierry Reding
2024-04-26 15:35 ` Thierry Reding
5 siblings, 1 reply; 8+ messages in thread
From: Thierry Reding @ 2024-04-26 15:32 UTC (permalink / raw)
To: herbert, davem, robh, krzysztof.kozlowski+dt, conor+dt,
thierry.reding, jonathanh, catalin.marinas, will, mperttunen,
airlied, daniel, linux-crypto, devicetree, linux-tegra,
linux-kernel, linux-arm-kernel, dri-devel, Akhil R
From: Thierry Reding <treding@nvidia.com>
On Wed, 03 Apr 2024 15:30:34 +0530, Akhil R wrote:
> Add support for Tegra Security Engine which can accelerates various
> crypto algorithms. The Engine has two separate instances within for
> AES and HASH algorithms respectively.
>
> The driver registers two crypto engines - one for AES and another for
> HASH algorithms and these operate independently and both uses the host1x
> bus. Additionally, it provides hardware-assisted key protection for up to
> 15 symmetric keys which it can use for the cipher operations.
>
> [...]
Applied, thanks!
[4/5] arm64: defconfig: Enable Tegra Security Engine
commit: 4d4d3fe6b3cc2a0b2a334a08bb9c64ba1dcbbea4
Best regards,
--
Thierry Reding <treding@nvidia.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: (subset) [PATCH v7 0/5] Add Tegra Security Engine driver
2024-04-26 15:32 ` (subset) " Thierry Reding
@ 2024-04-26 15:35 ` Thierry Reding
0 siblings, 0 replies; 8+ messages in thread
From: Thierry Reding @ 2024-04-26 15:35 UTC (permalink / raw)
To: Thierry Reding, herbert, davem, robh, krzysztof.kozlowski+dt,
conor+dt, jonathanh, catalin.marinas, will, mperttunen, airlied,
daniel, linux-crypto, devicetree, linux-tegra, linux-kernel,
linux-arm-kernel, dri-devel, Akhil R
[-- Attachment #1.1: Type: text/plain, Size: 949 bytes --]
On Fri Apr 26, 2024 at 5:32 PM CEST, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
>
> On Wed, 03 Apr 2024 15:30:34 +0530, Akhil R wrote:
> > Add support for Tegra Security Engine which can accelerates various
> > crypto algorithms. The Engine has two separate instances within for
> > AES and HASH algorithms respectively.
> >
> > The driver registers two crypto engines - one for AES and another for
> > HASH algorithms and these operate independently and both uses the host1x
> > bus. Additionally, it provides hardware-assisted key protection for up to
> > 15 symmetric keys which it can use for the cipher operations.
> >
> > [...]
>
> Applied, thanks!
>
> [4/5] arm64: defconfig: Enable Tegra Security Engine
> commit: 4d4d3fe6b3cc2a0b2a334a08bb9c64ba1dcbbea4
For the record, I've also applied patch 5/5 but it didn't apply cleanly
and so b4 didn't track it properly.
Thanks,
Thierry
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread