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Tue, 03 Jun 2025 04:40:31 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200:37e0:4ec0:b6ec:ef2a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a4f0097210sm17962177f8f.73.2025.06.03.04.40.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jun 2025 04:40:30 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 03 Jun 2025 13:40:30 +0200 Message-Id: From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= Subject: Re: [PATCH v3 9/9] RISC-V: KVM: Upgrade the supported SBI version to 3.0 Cc: "Anup Patel" , "Will Deacon" , "Mark Rutland" , "Paul Walmsley" , "Palmer Dabbelt" , "Mayuresh Chitale" , , , , , , "linux-riscv" To: "Atish Patra" , "Andrew Jones" References: <20250522-pmu_event_info-v3-0-f7bba7fd9cfe@rivosinc.com> <20250522-pmu_event_info-v3-9-f7bba7fd9cfe@rivosinc.com> <61627296-6f94-45ea-9410-ed0ea2251870@linux.dev> <20250526-224478e15ee50987124a47ac@orel> <20250528-ff9f6120de39c3e4eefc5365@orel> <1169138f-8445-4522-94dd-ad008524c600@linux.dev> <2bac252c-883c-4f8a-9ae1-283660991520@linux.dev> <0dcd01cd-419f-4225-b22c-cbaf82718235@linux.dev> In-Reply-To: <0dcd01cd-419f-4225-b22c-cbaf82718235@linux.dev> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250603_044033_841980_CF4DEEC9 X-CRM114-Status: GOOD ( 18.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org 2025-05-30T12:29:30-07:00, Atish Patra : > On 5/30/25 4:09 AM, Radim Kr=C4=8Dm=C3=A1=C5=99 wrote: >> 2025-05-29T11:44:38-07:00, Atish Patra : >>> On 5/29/25 3:24 AM, Radim Kr=C4=8Dm=C3=A1=C5=99 wrote: >>>> I originally gave up on the idea, but I feel kinda bad for Drew now, s= o >>>> trying again: >>> I am sorry if some of my replies came across in the wrong way. That was >>> never >>> the intention. >> I didn't mean to accuse you, my apologies. I agree with Drew's >> positions, so to expand on a question that wasn't touched in his mail: >> >>>> Even if userspace wants SBI for the M-mode interface, security minded >>> This is probably a 3rd one ? Why we want M-mode interface in the user >>> space ? >> It is about turning KVM into an ISA accelerator. >> >> A guest thinks it is running in S/HS-mode. >> The ecall instruction traps to M-mode. RISC-V H extension doesn't >> accelerate M-mode, so we have to emulate the trap in software. > We don't need to accelerate M-mode. That's the beauty of the RISC-V H=20 > extension. (It is a gap to me. :]) > The ISA is designed in such a way that the SBI is the interface between= =20 > the supervisor environment (VS/HS) > and the supervisor execution environment (HS/M). The ISA says nothing about the implementation of said interface. Returning 42 in x21 as a response to an ecall with 0x10 in a7 and 0x3 in a6 is perfectly valid RISC-V implementation that KVM currently cannot virtualize. >> The ISA doesn't say that M-mode means SBI. We try really hard to have >> SBI on all RISC-V, but I think KVM is taking it a bit too far. >> >> We can discuss how best to describe SBI, so userspace can choose to >> accelerate the M-mode in KVM, but I think that the ability to emulate >> M-mode in userspace should be provided. > I am still trying to understand the advantages of emulating the M-mode=20 > in the user space. > Can you please elaborate ? This thread already has a lot of them, so to avoid repeating them, I have to go into quite niche use-cases: When developing M-mode software on RISC-V (when RISC-V has more useful implementations than QEMU), a developer might want to accelerate the S/U-modes in KVM. It is also simpler to implement an old SBI interface (especially with bugs/quirks) if virtualization just executes the old M-mode binary. Why must KVM prevent userspace from virtualizing RISC-V? > I am assuming you are not hinting Nested virtualization which can be=20 > achieved with existing > ISA provided mechanisms and accelerated by SBI NACL. Right, I am talking about virtualization of RISC-V, because I don't have a crystal ball to figure out what users will want.