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[95.94.245.170]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-452730d161csm21907155e9.37.2025.06.06.06.56.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jun 2025 06:56:11 -0700 (PDT) From: Rui Miguel Silva X-Google-Original-From: "Rui Miguel Silva" Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 06 Jun 2025 14:56:05 +0100 Message-Id: Cc: , , , , , , , , , , , , Subject: Re: [PATCH 1/2] media: platform: Refactor interrupt status registers To: "Isaac Scott" , References: <20250606121403.498153-1-isaac.scott@ideasonboard.com> <20250606121403.498153-2-isaac.scott@ideasonboard.com> In-Reply-To: <20250606121403.498153-2-isaac.scott@ideasonboard.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250606_065614_007678_33CDFEC5 X-CRM114-Status: GOOD ( 22.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hey Isaac, Thanks for the patch. On Fri Jun 6, 2025 at 1:14 PM WEST, Isaac Scott wrote: > The NXP i.MX 8 MP CSI-2 receiver features multiple interrupt and debug > status sources which span multiple registers. The driver currently > supports two interrupt source registers, and attributes the > mipi_csis_event event entries to those registers through a boolean debug > field that indicate if the event relates to the main interrupt status > (false) or debug interrupt status (true) register. To make it easier to > add new event fields, replace the debug bool with a 'status index' > integer than indicates the index of the corresponding status register. > > Signed-off-by: Isaac Scott > --- > drivers/media/platform/nxp/imx-mipi-csis.c | 64 +++++++++++----------- > 1 file changed, 31 insertions(+), 33 deletions(-) > > diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/p= latform/nxp/imx-mipi-csis.c > index d060eadebc7a..bbc549c22aff 100644 > --- a/drivers/media/platform/nxp/imx-mipi-csis.c > +++ b/drivers/media/platform/nxp/imx-mipi-csis.c > @@ -249,7 +249,7 @@ > #define MIPI_CSI2_DATA_TYPE_USER(x) (0x30 + (x)) > =20 > struct mipi_csis_event { > - bool debug; > + unsigned int status_index; > u32 mask; > const char * const name; > unsigned int counter; > @@ -257,30 +257,30 @@ struct mipi_csis_event { > =20 > static const struct mipi_csis_event mipi_csis_events[] =3D { > /* Errors */ > - { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS, "SOT Error" }, > - { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS, "Lost Frame Start Error" }, > - { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE, "Lost Frame End Error" }, > - { false, MIPI_CSIS_INT_SRC_ERR_OVER, "FIFO Overflow Error" }, > - { false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error" }= , > - { false, MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error" }, > - { false, MIPI_CSIS_INT_SRC_ERR_CRC, "CRC Error" }, > - { false, MIPI_CSIS_INT_SRC_ERR_UNKNOWN, "Unknown Error" }, > - { true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT, "Data Type Not Supported= " }, > - { true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE, "Data Type Ignored" }, > - { true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE, "Frame Size Error" }, > - { true, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME, "Truncated Frame" }, > - { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE, "Early Frame End" }, > - { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS, "Early Frame Start" }, > + { 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS, "SOT Error"}, Maybe instead of 0,1,2 (magic indexes)... we could give a meaningful index enums names, don't know, like: main, debug, user??? or something that you think is better. Cheers, Rui > + { 0, MIPI_CSIS_INT_SRC_ERR_LOST_FS, "Lost Frame Start Error"}, > + { 0, MIPI_CSIS_INT_SRC_ERR_LOST_FE, "Lost Frame End Error"}, > + { 0, MIPI_CSIS_INT_SRC_ERR_OVER, "FIFO Overflow Error"}, > + { 0, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error"}, > + { 0, MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error"}, > + { 0, MIPI_CSIS_INT_SRC_ERR_CRC, "CRC Error"}, > + { 0, MIPI_CSIS_INT_SRC_ERR_UNKNOWN, "Unknown Error"}, > + { 1, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT, "Data Type Not Supported"}, > + { 1, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE, "Data Type Ignored"}, > + { 1, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE, "Frame Size Error"}, > + { 1, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME, "Truncated Frame"}, > + { 1, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE, "Early Frame End"}, > + { 1, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS, "Early Frame Start"}, > /* Non-image data receive events */ > - { false, MIPI_CSIS_INT_SRC_EVEN_BEFORE, "Non-image data before even fr= ame" }, > - { false, MIPI_CSIS_INT_SRC_EVEN_AFTER, "Non-image data after even fram= e" }, > - { false, MIPI_CSIS_INT_SRC_ODD_BEFORE, "Non-image data before odd fram= e" }, > - { false, MIPI_CSIS_INT_SRC_ODD_AFTER, "Non-image data after odd frame"= }, > + { 0, MIPI_CSIS_INT_SRC_EVEN_BEFORE, "Non-image data before even frame"= }, > + { 0, MIPI_CSIS_INT_SRC_EVEN_AFTER, "Non-image data after even frame"}, > + { 0, MIPI_CSIS_INT_SRC_ODD_BEFORE, "Non-image data before odd frame"}, > + { 0, MIPI_CSIS_INT_SRC_ODD_AFTER, "Non-image data after odd frame"}, > /* Frame start/end */ > - { false, MIPI_CSIS_INT_SRC_FRAME_START, "Frame Start" }, > - { false, MIPI_CSIS_INT_SRC_FRAME_END, "Frame End" }, > - { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL, "VSYNC Falling Edge" }, > - { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE, "VSYNC Rising Edge" }, > + { 0, MIPI_CSIS_INT_SRC_FRAME_START, "Frame Start"}, > + { 0, MIPI_CSIS_INT_SRC_FRAME_END, "Frame End"}, > + { 1, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL, "VSYNC Falling Edge"}, > + { 1, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE, "VSYNC Rising Edge"}, > }; > =20 > #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events) > @@ -765,32 +765,30 @@ static irqreturn_t mipi_csis_irq_handler(int irq, v= oid *dev_id) > struct mipi_csis_device *csis =3D dev_id; > unsigned long flags; > unsigned int i; > - u32 status; > - u32 dbg_status; > + u32 status[2]; > =20 > - status =3D mipi_csis_read(csis, MIPI_CSIS_INT_SRC); > - dbg_status =3D mipi_csis_read(csis, MIPI_CSIS_DBG_INTR_SRC); > + status[0] =3D mipi_csis_read(csis, MIPI_CSIS_INT_SRC); > + status[1] =3D mipi_csis_read(csis, MIPI_CSIS_DBG_INTR_SRC); > =20 > spin_lock_irqsave(&csis->slock, flags); > =20 > /* Update the event/error counters */ > - if ((status & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) { > + if ((status[0] & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) { > for (i =3D 0; i < MIPI_CSIS_NUM_EVENTS; i++) { > struct mipi_csis_event *event =3D &csis->events[i]; > =20 > - if ((!event->debug && (status & event->mask)) || > - (event->debug && (dbg_status & event->mask))) > + if (status[event->status_index] & event->mask) > event->counter++; > } > } > =20 > - if (status & MIPI_CSIS_INT_SRC_FRAME_START) > + if (status[0] & MIPI_CSIS_INT_SRC_FRAME_START) > mipi_csis_queue_event_sof(csis); > =20 > spin_unlock_irqrestore(&csis->slock, flags); > =20 > - mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status); > - mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_SRC, dbg_status); > + mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status[0]); > + mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_SRC, status[1]); > =20 > return IRQ_HANDLED; > } > --=20 > 2.43.0