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From: =?utf-8?Q?Stefan_D=C3=B6singer?= In-Reply-To: <20260511-backstage-crewman-e44947ab6cfc@spud> Date: Tue, 12 May 2026 00:33:42 +0300 Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Message-Id: References: <20260511-zx29clk-v2-0-29f0edc300f5@gmail.com> <20260511-zx29clk-v2-1-29f0edc300f5@gmail.com> <20260511-backstage-crewman-e44947ab6cfc@spud> To: Conor Dooley X-Mailer: Apple Mail (2.3864.500.181) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260511_143402_306716_9E8D538F X-CRM114-Status: GOOD ( 19.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --Apple-Mail=_86F8E9FE-3936-42D2-92C0-780617216CA2 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=us-ascii Hi Conor, Thanks for your reply! > Am 11.05.2026 um 19:07 schrieb Conor Dooley : >=20 > How come the "matrixclk" has no constraints on clock properties? Because I am not sure what the correct/preferred way to express the = interface between top and matrix is - see the first question raised in = my cover letter. In short, matrix potentially consumes all clocks available on the top = controller. There is no obvious interface between them, like there is = between matrix and LSP. So I see two ways to handle this in the = bindings: 1) List the top clk inputs, top clk PLL outputs and PLL fractionals as = matrix input 2) Be quiet about it It'd be about 20 clocks or so that I know are consumed. The bigger issue = than the number of clocks is that my knowledge of the board is from = reverse engineering, not proper datasheets, so I might find out that a = clock is missing or wrong. > Although, these two devices seem too different to be in the same > dt-binding. Do they have anyhting in common other than the SoC they = are > part of? No, they don't have anything in common, other than that their concerns = are poorly separated in hardware. I take it from your question that the preferred way is to have separate = bindings for them in this case - I guess separate headers as well as = separate yaml files. Is this correct? The third clock controller - LSP - is nicely separated from the other = two. I would not be surprised to see this subsystem of the board show up = on a different ZTE board. If top and matrix should have different = bindings, LSP certainly should as well.= --Apple-Mail=_86F8E9FE-3936-42D2-92C0-780617216CA2 Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=signature.asc Content-Type: application/pgp-signature; name=signature.asc Content-Description: Message signed with OpenPGP -----BEGIN PGP SIGNATURE----- iQIzBAEBCAAdFiEEQxb0tqoFWyeVMl1sPRO8yFRPGiIFAmoCSzYACgkQPRO8yFRP GiJreA/+NGigL8m01fqUXyaZXJW5lLjWCmzMbFofI/RsTAhtteVvQK2IwcfN6iYG KtWe+zgDbdjjhwLYy1VJqgUMfyYHaWVicYSnxJ0q8JvTcJeDclHifEV0sQjqsmQO KWlolqcNVfSq9qLcYNyfygoKbBOSlIt//WqyiX591Rpkcar/mPVjrrSXqHciErrs hE5eTYr0RoyE4CDc2o20I5oqZwtntKa1xbOav4GSD1tUNLbsTm0xWLFLf2Bh3uX9 3qS/GJDgNCTeTnEK/Pks7JNPk25kIq2OeTktMR8cv5SSs8ZQLaKtvQCX97QnfL8H 03YRzF/jbBXsCYO+IXWMrn1R+J26HkUR61lWOkiWykoj4Zda7mX2zGaTsFR/tcPL u3rOSmbcqEaMMY2hD08I/vIrbXcPiZ26rxS0DgnwKwqN8kFem0ULhjw3L0UCURXO 3J9IHhKhkp++QmTZSclOOY8MWujAh3IRYoT8VwUtQkmmsEzDkTnmj+at0tf7CtOp fQmC3jkuGPrRj0fZJeFvPze3EGxHWWTBHkHaoAqtjGs6ONVNRx58MuasigPKmueb CN7jtmppAGpLlur53BXetZflBBdFfU+EpDmOszZJ989HOZtsg/zAu7ZuWfCYDMKH FD+WtwfgX6fIqRrLs0/FD7rV1kHx/GagGhOfBey/j+iPqvcTgoU= =XNGK -----END PGP SIGNATURE----- --Apple-Mail=_86F8E9FE-3936-42D2-92C0-780617216CA2--