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Thu, 04 Dec 2025 05:16:28 -0800 (PST) Received: from localhost ([1.232.169.190]) by smtp.gmail.com with UTF8SMTPSA id 98e67ed59e1d1-3494f38a27asm1890893a91.4.2025.12.04.05.16.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Dec 2025 05:16:27 -0800 (PST) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 04 Dec 2025 22:16:24 +0900 Message-Id: Subject: Re: [External] Re: [PATCH v3 5/8] riscv: smp: use NMI for CPU stop Cc: , , , , , , , , , , , , , , , , , , , , , , , , , "linux-riscv" To: "yunhui cui" From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20251127125305.89961-1-cuiyunhui@bytedance.com> <20251127125305.89961-6-cuiyunhui@bytedance.com> In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251204_051629_149851_1D852912 X-CRM114-Status: GOOD ( 15.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org 2025-12-04T13:28:45+08:00, yunhui cui : > Hi Radim, > > On Thu, Dec 4, 2025 at 12:07=E2=80=AFPM Radim Kr=C4=8Dm=C3=A1=C5=99 wrote: >> >> 2025-11-27T20:53:02+08:00, Yunhui Cui : >> > Use NMI instead of IPI for CPU stop if RISC-V SSE NMI is supported. >> > >> > Signed-off-by: Yunhui Cui >> > --- >> > diff --git a/drivers/firmware/riscv/riscv_sse_nmi.c b/drivers/firmware= /riscv/riscv_sse_nmi.c >> > @@ -58,6 +58,7 @@ static int local_nmi_handler(u32 evt, void *arg, str= uct pt_regs *regs) >> > type =3D atomic_read(this_cpu_ptr(&local_nmi)); >> > >> > NMI_HANDLE(LOCAL_NMI_CRASH, cpu_crash_stop, cpu, regs); >> > + NMI_HANDLE(LOCAL_NMI_STOP, cpu_stop); >> >> Please document the intended preemption design for all SSE events, >> because it will be a nightmare if we forget some assumptions in the >> coming years. (That includes the relative priorities of RAS/PMU/...) > > Actually, LOCAL_NMI_CRASH, LOCAL_NMI_STOP, LOCAL_NMI_BACKTRACE, > LOCAL_NMI_KGDB, ... are all implemented via the single SSE event > SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED. Per the SSE design, no > preemption will occur among CRASH, STOP, BACKTRACE, and KGDB events. That is how it is. I don't understand why it must be like that. For example: PMU_OVERFLOW has lower event_id than SOFTWARE_INJECTED, so it will currently interrupt NMI_CRASH as they both have priority 0, although NMI_CRASH probably shouldn't be masked by anything, and should preempt everything. NMI_BACKTRACE, on the other hand, probably shouldn't have that high priority as there seem more important events (e.g. RAS and NMI_CRASH). The issues can be avoided by event priorities, masking, or deemed as non-issue, but I think it would be beneficial to provide some reasoning behind the design, as the choices don't seem obvious to me. Thanks.