From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 68769CD8CB0 for ; Thu, 13 Nov 2025 17:47:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Date:Message-Id:Content-Type :Content-Transfer-Encoding:MIME-Version:Subject:Cc:To:From:References: In-Reply-To:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=0rNju7eQFm0esNy2lFB6OI4OIIy97M3G9CzH/q8kZmQ=; b=SFVoBHcLnOpKX1WWIQEuQfEIQX N3tQcgbS+XcJ107ZpsZsfwWUYApxIQUcYeUN8kNN84d/1WYO9qoQg83yJG/KmUYBpd7IOHvlkIUgH 9sCHcljt8OZAVTuY3xd2fedN0U2cey8Qbv/L8EhdPFXoDX2WahTX/xpoE6MBceQoymFbBRztE3/Nm SHznfwlkI3DoVAonFj/iDYCpGzMxKsQmV/AEq6CoVeqZsfzSLLrlTFJ5QKrFEMYJ6iYuST43dvM2+ Jm7Hmw/xeLCEHs56PLD597KBmaCfYmM5yvV7DV2lW4TYj6dq64tD40DgEmSPIDtLBHpal10I1EWkl 14Gu9CAg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vJbPM-0000000AswS-1EuJ; Thu, 13 Nov 2025 17:46:56 +0000 Received: from pandora.armlinux.org.uk ([2001:4d48:ad52:32c8:5054:ff:fe00:142]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vJbPJ-0000000Ast2-3tjg; Thu, 13 Nov 2025 17:46:55 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=armlinux.org.uk; s=pandora-2019; h=Date:Sender:Message-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:Subject:Cc:To:From:References: In-Reply-To:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=0rNju7eQFm0esNy2lFB6OI4OIIy97M3G9CzH/q8kZmQ=; b=wqI7nteEBuAimdgboDc56uOIV2 exg4mCxEDbMjx/YePg6KXWXk2eJDdzeYxxZoAGQs6yK9junMVvbDQCnvt+dsnEsiJ2dnq+HalOhLW r0JXIQ6jhWmNsusZLnU601UmMb9Q8pWEZTJ4LQ8p99gEX8VgokwmT+xQX1Bj94pIFTFPHss0ZEZVt nIWynopf8au6G471C4WH1NE/6adYpZ6rKMEs/JbuFdMS1ZMslkzhaYHhsUXL5xBW6VYn4/BOL3617 CyVeMeC1VhKUJoOHGSd9aP71X4qjXq5/bM6PJ4BEUTMeQvizo1mNaQwA4xKjAwZHEAEidvmho2BZA 7h/c4cVg==; Received: from e0022681537dd.dyn.armlinux.org.uk ([fd8f:7570:feb6:1:222:68ff:fe15:37dd]:57062 helo=rmk-PC.armlinux.org.uk) by pandora.armlinux.org.uk with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vJbPC-000000005o4-2480; Thu, 13 Nov 2025 17:46:46 +0000 Received: from rmk by rmk-PC.armlinux.org.uk with local (Exim 4.98.2) (envelope-from ) id 1vJbPB-0000000EBqV-27GS; Thu, 13 Nov 2025 17:46:45 +0000 In-Reply-To: References: From: "Russell King (Oracle)" To: Andrew Lunn , Heiner Kallweit Cc: Alexandre Torgue , Andrew Lunn , "David S. Miller" , Eric Dumazet , Heiko Stuebner , Jakub Kicinski , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, Maxime Coquelin , netdev@vger.kernel.org, Paolo Abeni Subject: [PATCH net-next 3/4] net: stmmac: rk: use PHY_INTF_SEL_x constants MIME-Version: 1.0 Content-Disposition: inline Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="utf-8" Message-Id: Date: Thu, 13 Nov 2025 17:46:45 +0000 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251113_094654_129862_FA8E6D0D X-CRM114-Status: UNSURE ( 9.20 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The values used in the xxx_GMAC_PHY_INTF_SEL_xxx() macros are the phy_intf_sel values used for the dwmac core. Use these to define these constants. No change to produced code on aarch64. Signed-off-by: Russell King (Oracle) --- .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 46 +++++++++---------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c index 4257cc1f66e9..49076ee00877 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c @@ -234,7 +234,7 @@ static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv, #define PX30_GRF_GMAC_CON1 0x0904 /* PX30_GRF_GMAC_CON1 */ -#define PX30_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4) +#define PX30_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII) #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2) #define PX30_GMAC_SPEED_100M GRF_BIT(2) @@ -290,8 +290,8 @@ static const struct rk_gmac_ops px30_ops = { #define RK3128_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) /* RK3128_GRF_MAC_CON1 */ -#define RK3128_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, 1) -#define RK3128_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(8, 6, 4) +#define RK3128_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, PHY_INTF_SEL_RGMII) +#define RK3128_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(8, 6, PHY_INTF_SEL_RMII) #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9) #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10) @@ -353,8 +353,8 @@ static const struct rk_gmac_ops rk3128_ops = { #define RK3228_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) /* RK3228_GRF_MAC_CON1 */ -#define RK3228_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1) -#define RK3228_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4) +#define RK3228_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII) +#define RK3228_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII) #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3) #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2) @@ -432,8 +432,8 @@ static const struct rk_gmac_ops rk3228_ops = { #define RK3288_GRF_SOC_CON3 0x0250 /*RK3288_GRF_SOC_CON1*/ -#define RK3288_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, 1) -#define RK3288_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(8, 6, 4) +#define RK3288_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, PHY_INTF_SEL_RGMII) +#define RK3288_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(8, 6, PHY_INTF_SEL_RMII) #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9) #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10) @@ -496,7 +496,7 @@ static const struct rk_gmac_ops rk3288_ops = { #define RK3308_GRF_MAC_CON0 0x04a0 /* RK3308_GRF_MAC_CON0 */ -#define RK3308_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(4, 2, 4) +#define RK3308_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(4, 2, PHY_INTF_SEL_RMII) #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3) #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) #define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0) @@ -535,8 +535,8 @@ static const struct rk_gmac_ops rk3308_ops = { #define RK3328_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) /* RK3328_GRF_MAC_CON1 */ -#define RK3328_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1) -#define RK3328_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4) +#define RK3328_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII) +#define RK3328_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII) #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3) #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2) @@ -622,8 +622,8 @@ static const struct rk_gmac_ops rk3328_ops = { #define RK3366_GRF_SOC_CON7 0x041c /* RK3366_GRF_SOC_CON6 */ -#define RK3366_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, 1) -#define RK3366_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, 4) +#define RK3366_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, PHY_INTF_SEL_RGMII) +#define RK3366_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, PHY_INTF_SEL_RMII) #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8) #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7) @@ -687,8 +687,8 @@ static const struct rk_gmac_ops rk3366_ops = { #define RK3368_GRF_SOC_CON16 0x0440 /* RK3368_GRF_SOC_CON15 */ -#define RK3368_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, 1) -#define RK3368_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, 4) +#define RK3368_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, PHY_INTF_SEL_RGMII) +#define RK3368_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, PHY_INTF_SEL_RMII) #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7) @@ -752,8 +752,8 @@ static const struct rk_gmac_ops rk3368_ops = { #define RK3399_GRF_SOC_CON6 0xc218 /* RK3399_GRF_SOC_CON5 */ -#define RK3399_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, 1) -#define RK3399_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, 4) +#define RK3399_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, PHY_INTF_SEL_RGMII) +#define RK3399_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, PHY_INTF_SEL_RMII) #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8) #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7) @@ -1015,8 +1015,8 @@ static const struct rk_gmac_ops rk3528_ops = { #define RK3568_GRF_GMAC1_CON1 0x038c /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ -#define RK3568_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1) -#define RK3568_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4) +#define RK3568_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII) +#define RK3568_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII) #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3) #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) @@ -1209,9 +1209,9 @@ static const struct rk_gmac_ops rk3576_ops = { #define RK3588_GRF_CLK_CON1 0X0070 #define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \ - (GRF_FIELD(5, 3, 1) << ((id) * 6)) + (GRF_FIELD(5, 3, PHY_INTF_SEL_RGMII) << ((id) * 6)) #define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \ - (GRF_FIELD(5, 3, 4) << ((id) * 6)) + (GRF_FIELD(5, 3, PHY_INTF_SEL_RMII) << ((id) * 6)) #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id)) #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id)) @@ -1328,7 +1328,7 @@ static const struct rk_gmac_ops rk3588_ops = { #define RV1108_GRF_GMAC_CON0 0X0900 /* RV1108_GRF_GMAC_CON0 */ -#define RV1108_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4) +#define RV1108_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII) #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3) #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2) @@ -1364,8 +1364,8 @@ static const struct rk_gmac_ops rv1108_ops = { #define RV1126_GRF_GMAC_CON2 0X0078 /* RV1126_GRF_GMAC_CON0 */ -#define RV1126_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1) -#define RV1126_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4) +#define RV1126_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII) +#define RV1126_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII) #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7) #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7) #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1) -- 2.47.3