From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
To: Andrew Lunn <andrew@lunn.ch>, Heiner Kallweit <hkallweit1@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Heiko Stuebner <heiko@sntech.de>,
Jakub Kicinski <kuba@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org,
linux-stm32@st-md-mailman.stormreply.com,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
netdev@vger.kernel.org, Paolo Abeni <pabeni@redhat.com>
Subject: [PATCH RFC net-next 08/15] net: stmmac: rk: use rk_encode_wm16() for RMII speed
Date: Mon, 01 Dec 2025 14:51:23 +0000 [thread overview]
Message-ID: <E1vQ5FL-0000000GNwB-2ckX@rmk-PC.armlinux.org.uk> (raw)
In-Reply-To: <aS2rFBlz1jdwXaS8@shell.armlinux.org.uk>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 71 +++++++++----------
1 file changed, 33 insertions(+), 38 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index d11a58d7f24b..5f586782d595 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -49,6 +49,7 @@ struct rk_gmac_ops {
u16 speed_grf_reg;
u16 gmii_clk_sel_mask;
+ u16 mac_speed_mask;
bool speed_reg_php_grf;
bool php_grf_required;
@@ -103,6 +104,7 @@ struct rk_priv_data {
u16 speed_grf_reg;
u16 gmii_clk_sel_mask;
+ u16 mac_speed_mask;
};
#define GMAC_CLK_DIV1_125M 0
@@ -156,10 +158,12 @@ static int rk_set_reg_speed(struct rk_priv_data *bsp_priv,
val = rk_encode_wm16(ret, bsp_priv->gmii_clk_sel_mask);
} else if (interface == PHY_INTERFACE_MODE_RMII) {
+ val = rk_encode_wm16(speed == SPEED_100,
+ bsp_priv->mac_speed_mask);
if (speed == SPEED_10) {
- val = rsd->rmii_10;
+ val |= rsd->rmii_10;
} else if (speed == SPEED_100) {
- val = rsd->rmii_100;
+ val |= rsd->rmii_100;
} else {
/* Phylink will not allow inappropriate speeds for
* interface modes, so this should never happen.
@@ -341,8 +345,6 @@ static const struct rk_gmac_ops px30_ops = {
/* RK3128_GRF_MAC_CON1 */
#define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
#define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
-#define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10)
-#define RK3128_GMAC_SPEED_100M GRF_BIT(10)
#define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11)
#define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
@@ -360,8 +362,8 @@ static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3128_reg_speed_data = {
- .rmii_10 = RK3128_GMAC_RMII_CLK_2_5M | RK3128_GMAC_SPEED_10M,
- .rmii_100 = RK3128_GMAC_RMII_CLK_25M | RK3128_GMAC_SPEED_100M,
+ .rmii_10 = RK3128_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3128_GMAC_RMII_CLK_25M,
};
static int rk3128_set_speed(struct rk_priv_data *bsp_priv,
@@ -382,6 +384,7 @@ static const struct rk_gmac_ops rk3128_ops = {
.speed_grf_reg = RK3128_GRF_MAC_CON1,
.gmii_clk_sel_mask = GENMASK_U16(13, 12),
+ .mac_speed_mask = BIT_U16(10),
};
#define RK3228_GRF_MAC_CON0 0x0900
@@ -396,8 +399,6 @@ static const struct rk_gmac_ops rk3128_ops = {
/* RK3228_GRF_MAC_CON1 */
#define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
-#define RK3228_GMAC_SPEED_100M GRF_BIT(2)
#define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
#define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
#define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
@@ -426,8 +427,8 @@ static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3228_reg_speed_data = {
- .rmii_10 = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_SPEED_10M,
- .rmii_100 = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_SPEED_100M,
+ .rmii_10 = RK3228_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3228_GMAC_RMII_CLK_25M,
};
static int rk3228_set_speed(struct rk_priv_data *bsp_priv,
@@ -458,6 +459,7 @@ static const struct rk_gmac_ops rk3228_ops = {
.speed_grf_reg = RK3228_GRF_MAC_CON1,
.gmii_clk_sel_mask = GENMASK_U16(9, 8),
+ .mac_speed_mask = BIT_U16(2),
};
#define RK3288_GRF_SOC_CON1 0x0248
@@ -466,8 +468,6 @@ static const struct rk_gmac_ops rk3228_ops = {
/*RK3288_GRF_SOC_CON1*/
#define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
#define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
-#define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
-#define RK3288_GMAC_SPEED_100M GRF_BIT(10)
#define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
#define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
@@ -493,8 +493,8 @@ static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3288_reg_speed_data = {
- .rmii_10 = RK3288_GMAC_RMII_CLK_2_5M | RK3288_GMAC_SPEED_10M,
- .rmii_100 = RK3288_GMAC_RMII_CLK_25M | RK3288_GMAC_SPEED_100M,
+ .rmii_10 = RK3288_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3288_GMAC_RMII_CLK_25M,
};
static int rk3288_set_speed(struct rk_priv_data *bsp_priv,
@@ -515,6 +515,7 @@ static const struct rk_gmac_ops rk3288_ops = {
.speed_grf_reg = RK3288_GRF_SOC_CON1,
.gmii_clk_sel_mask = GENMASK_U16(13, 12),
+ .mac_speed_mask = BIT_U16(10),
};
#define RK3308_GRF_MAC_CON0 0x04a0
@@ -522,16 +523,12 @@ static const struct rk_gmac_ops rk3288_ops = {
/* RK3308_GRF_MAC_CON0 */
#define RK3308_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0)
-#define RK3308_GMAC_SPEED_100M GRF_BIT(0)
static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
static const struct rk_reg_speed_data rk3308_reg_speed_data = {
- .rmii_10 = RK3308_GMAC_SPEED_10M,
- .rmii_100 = RK3308_GMAC_SPEED_100M,
};
static int rk3308_set_speed(struct rk_priv_data *bsp_priv,
@@ -549,6 +546,7 @@ static const struct rk_gmac_ops rk3308_ops = {
.phy_intf_sel_mask = GENMASK_U16(4, 2),
.speed_grf_reg = RK3308_GRF_MAC_CON0,
+ .mac_speed_mask = BIT_U16(0),
};
#define RK3328_GRF_MAC_CON0 0x0900
@@ -563,8 +561,6 @@ static const struct rk_gmac_ops rk3308_ops = {
/* RK3328_GRF_MAC_CON1 */
#define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2)
-#define RK3328_GMAC_SPEED_100M GRF_BIT(2)
#define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7)
#define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
#define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
@@ -609,8 +605,8 @@ static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3328_reg_speed_data = {
- .rmii_10 = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_SPEED_10M,
- .rmii_100 = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_SPEED_100M,
+ .rmii_10 = RK3328_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3328_GMAC_RMII_CLK_25M,
};
static int rk3328_set_speed(struct rk_priv_data *bsp_priv,
@@ -639,6 +635,8 @@ static const struct rk_gmac_ops rk3328_ops = {
.phy_intf_sel_mask = GENMASK_U16(6, 4),
.rmii_mode_mask = BIT_U16(9),
+ .mac_speed_mask = BIT_U16(2),
+
.regs_valid = true,
.regs = {
0xff540000, /* gmac2io */
@@ -653,8 +651,6 @@ static const struct rk_gmac_ops rk3328_ops = {
/* RK3366_GRF_SOC_CON6 */
#define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
-#define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
-#define RK3366_GMAC_SPEED_100M GRF_BIT(7)
#define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
@@ -680,8 +676,8 @@ static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3366_reg_speed_data = {
- .rmii_10 = RK3366_GMAC_RMII_CLK_2_5M | RK3366_GMAC_SPEED_10M,
- .rmii_100 = RK3366_GMAC_RMII_CLK_25M | RK3366_GMAC_SPEED_100M,
+ .rmii_10 = RK3366_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3366_GMAC_RMII_CLK_25M,
};
static int rk3366_set_speed(struct rk_priv_data *bsp_priv,
@@ -702,6 +698,7 @@ static const struct rk_gmac_ops rk3366_ops = {
.speed_grf_reg = RK3366_GRF_SOC_CON6,
.gmii_clk_sel_mask = GENMASK_U16(5, 4),
+ .mac_speed_mask = BIT_U16(7),
};
#define RK3368_GRF_SOC_CON15 0x043c
@@ -710,8 +707,6 @@ static const struct rk_gmac_ops rk3366_ops = {
/* RK3368_GRF_SOC_CON15 */
#define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
-#define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
-#define RK3368_GMAC_SPEED_100M GRF_BIT(7)
#define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
@@ -737,8 +732,8 @@ static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3368_reg_speed_data = {
- .rmii_10 = RK3368_GMAC_RMII_CLK_2_5M | RK3368_GMAC_SPEED_10M,
- .rmii_100 = RK3368_GMAC_RMII_CLK_25M | RK3368_GMAC_SPEED_100M,
+ .rmii_10 = RK3368_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3368_GMAC_RMII_CLK_25M,
};
static int rk3368_set_speed(struct rk_priv_data *bsp_priv,
@@ -759,6 +754,7 @@ static const struct rk_gmac_ops rk3368_ops = {
.speed_grf_reg = RK3368_GRF_SOC_CON15,
.gmii_clk_sel_mask = GENMASK_U16(5, 4),
+ .mac_speed_mask = BIT_U16(7),
};
#define RK3399_GRF_SOC_CON5 0xc214
@@ -767,8 +763,6 @@ static const struct rk_gmac_ops rk3368_ops = {
/* RK3399_GRF_SOC_CON5 */
#define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
-#define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
-#define RK3399_GMAC_SPEED_100M GRF_BIT(7)
#define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
@@ -794,8 +788,8 @@ static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3399_reg_speed_data = {
- .rmii_10 = RK3399_GMAC_RMII_CLK_2_5M | RK3399_GMAC_SPEED_10M,
- .rmii_100 = RK3399_GMAC_RMII_CLK_25M | RK3399_GMAC_SPEED_100M,
+ .rmii_10 = RK3399_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3399_GMAC_RMII_CLK_25M,
};
static int rk3399_set_speed(struct rk_priv_data *bsp_priv,
@@ -816,6 +810,7 @@ static const struct rk_gmac_ops rk3399_ops = {
.speed_grf_reg = RK3399_GRF_SOC_CON5,
.gmii_clk_sel_mask = GENMASK_U16(5, 4),
+ .mac_speed_mask = BIT_U16(7),
};
#define RK3506_GRF_SOC_CON8 0x0020
@@ -1361,8 +1356,6 @@ static const struct rk_gmac_ops rk3588_ops = {
/* RV1108_GRF_GMAC_CON0 */
#define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
#define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2)
-#define RV1108_GMAC_SPEED_100M GRF_BIT(2)
#define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7)
#define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
@@ -1371,8 +1364,8 @@ static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rv1108_reg_speed_data = {
- .rmii_10 = RV1108_GMAC_RMII_CLK_2_5M | RV1108_GMAC_SPEED_10M,
- .rmii_100 = RV1108_GMAC_RMII_CLK_25M | RV1108_GMAC_SPEED_100M,
+ .rmii_10 = RV1108_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RV1108_GMAC_RMII_CLK_25M,
};
static int rv1108_set_speed(struct rk_priv_data *bsp_priv,
@@ -1390,6 +1383,7 @@ static const struct rk_gmac_ops rv1108_ops = {
.phy_intf_sel_mask = GENMASK_U16(6, 4),
.speed_grf_reg = RV1108_GRF_GMAC_CON0,
+ .mac_speed_mask = BIT_U16(2),
};
#define RV1126_GRF_GMAC_CON0 0X0070
@@ -1672,6 +1666,7 @@ static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
/* Set the default speed related parameters */
bsp_priv->speed_grf_reg = ops->speed_grf_reg;
bsp_priv->gmii_clk_sel_mask = ops->gmii_clk_sel_mask;
+ bsp_priv->mac_speed_mask = ops->mac_speed_mask;
if (ops->init) {
ret = ops->init(bsp_priv);
--
2.47.3
next prev parent reply other threads:[~2025-12-01 14:51 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-01 14:49 [PATCH RFC net-next 00/15] net: stmmac: rk: cleanups galore Russell King (Oracle)
2025-12-01 14:50 ` [PATCH RFC net-next 01/15] net: stmmac: rk: add GMAC_CLK_xx constants, simplify RGMII definitions Russell King (Oracle)
2025-12-02 20:31 ` Andrew Lunn
2025-12-01 14:50 ` [PATCH RFC net-next 02/15] net: stmmac: rk: convert rk3328 to use bsp_priv->id Russell King (Oracle)
2025-12-01 14:50 ` [PATCH RFC net-next 03/15] net: stmmac: rk: add SoC specific ->init() method Russell King (Oracle)
2025-12-01 14:51 ` [PATCH RFC net-next 04/15] net: stmmac: rk: convert to mask-based interface mode configuration Russell King (Oracle)
2025-12-02 20:41 ` Russell King (Oracle)
2025-12-01 14:51 ` [PATCH RFC net-next 05/15] net: stmmac: rk: move speed GRF register offset to private data Russell King (Oracle)
2025-12-01 14:51 ` [PATCH RFC net-next 06/15] net: stmmac: rk: convert rk3588 to rk_set_reg_speed() Russell King (Oracle)
2025-12-01 14:51 ` [PATCH RFC net-next 07/15] net: stmmac: rk: use rk_encode_wm16() for RGMII clocks Russell King (Oracle)
2025-12-01 14:51 ` Russell King (Oracle) [this message]
2025-12-01 14:51 ` [PATCH RFC net-next 09/15] net: stmmac: rk: use rk_encode_wm16() for RMII clock Russell King (Oracle)
2025-12-01 14:51 ` [PATCH RFC net-next 10/15] net: stmmac: rk: move speed register into bsp_priv Russell King (Oracle)
2025-12-01 14:51 ` [PATCH RFC net-next 11/15] net: stmmac: rk: convert px30 Russell King (Oracle)
2025-12-01 14:51 ` [PATCH RFC net-next 12/15] net: stmmac: rk: introduce flags indicating support for RGMII/RMII Russell King (Oracle)
2025-12-01 14:51 ` [PATCH RFC net-next 13/15] net: stmmac: rk: replace empty set_to_rmii() with supports_rmii Russell King (Oracle)
2025-12-01 14:51 ` [PATCH RFC net-next 14/15] net: stmmac: rk: rk3328: gmac2phy only supports RMII Russell King (Oracle)
2025-12-01 14:51 ` [PATCH RFC net-next 15/15] net: stmmac: rk: rk3528: gmac0 " Russell King (Oracle)
2025-12-01 15:55 ` [PATCH RFC net-next 00/15] net: stmmac: rk: cleanups galore Andrew Lunn
2025-12-01 16:38 ` Russell King (Oracle)
2025-12-04 0:50 ` Jacob Keller
2025-12-01 16:44 ` Russell King (Oracle)
2025-12-04 0:51 ` Jacob Keller
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=E1vQ5FL-0000000GNwB-2ckX@rmk-PC.armlinux.org.uk \
--to=rmk+kernel@armlinux.org.uk \
--cc=alexandre.torgue@foss.st.com \
--cc=andrew+netdev@lunn.ch \
--cc=andrew@lunn.ch \
--cc=davem@davemloft.net \
--cc=edumazet@google.com \
--cc=heiko@sntech.de \
--cc=hkallweit1@gmail.com \
--cc=kuba@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-rockchip@lists.infradead.org \
--cc=linux-stm32@st-md-mailman.stormreply.com \
--cc=mcoquelin.stm32@gmail.com \
--cc=netdev@vger.kernel.org \
--cc=pabeni@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).