回覆: [PATCH 1/8] dt-bindings: i3c: Document the AST2700 I3C controller

[Billy Tsai <billy_tsai@aspeedtech.com>]

> > +  bias-pull-up:
> > +    $ref: /schemas/pinctrl/pincfg-node.yaml#/properties/bias-pull-up
> > +    enum: [177, 231, 261, 317, 400, 470, 550, 600, 750]
> > +    description:
> > +      Enable the PHY-internal pull-ups on SCL and SDA and select their
> > +      strength, in Ohms. High-voltage pins support 400, 470 or 600 Ohms,
> > +      and low-voltage pins support 177, 231, 261, 317, 400, 550 or 750
> > +      Ohms. When absent the internal pull-ups stay disabled and the bus
> > +      relies on external pull-ups.

> this one should go through pinctrl.

The only pinctrl capability of the device is to bias the pins via the PHY registers,
so describing the device as a pin controller feels excessive by comparison to allowing
a single property that already has an appropriate definition.

I'd prefer to keep this approach, but I'm open to reconsidering if there is a reason
this control needs to be exposed using the usual pinctrl bindings.

> > +  aspeed,pp-scl-high-ns:
> > +    description:
> > +      Push-pull SCL high period. Overrides the value derived from the
> > +      i3c-scl-hz bus rate.
[...]
> > +  aspeed,sr-p-scl-low-ns:
> > +    default: 40
> > +    description:
> > +      SCL low period used while preparing a repeated START or STOP
> > +      condition, kept separate from the push-pull SCL low period to
> > +      satisfy the MIPI I3C clock stalling requirements.

> these value is i3c stardard defined value, why need put into dt-binding.

The defaults are derived from i3c-scl-hz per the protocol formulas, but
board-level trace length, pull-up strength and capacitive loading can
require different high/low ratios, hold times and START/STOP setup
periods than what those formulas produce for a given board. These
properties only override the derived default when a specific board
needs it; anything left unset keeps the spec-derived value.

Billy