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[86.58.12.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4ba0234a5dcsm73237085e9.2.2026.11.10.07.55.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Nov 2026 07:55:43 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Stephen Boyd , Brian Masney , Jerome Brunet , Chen-Yu Tsai , Samuel Holland , Maxime Ripard , Andre Przywara , aiyengar1990@gmail.com Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH 2/2] clk: sunxi-ng: h616: Let the S/PDIF clock set the audio PLL rate Date: Tue, 10 Nov 2026 16:55:41 +0100 Message-ID: In-Reply-To: <20261110-h616-clk-emac-spdif-v1-2-e5e36e8963e4@gmail.com> References: <20261110-h616-clk-emac-spdif-v1-0-e5e36e8963e4@gmail.com> <20261110-h616-clk-emac-spdif-v1-2-e5e36e8963e4@gmail.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261110_075546_463316_76305D28 X-CRM114-Status: GOOD ( 20.59 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Dne torek, 10. november 2026 ob 07:03:01 Srednjeevropski standardni =C4=8Da= s je Arun Iyengar via B4 Relay napisal(a): > From: Arun Iyengar >=20 > sun4i-spdif asks for 22.5792 or 24.576 MHz on the S/PDIF (OWA) module > clock, depending on the sample rate family. The spdif clock has no > CLK_SET_RATE_PARENT, so it can only divide down the rate pll-audio > already runs at. Unless another audio device has already set the PLL for > the right family, the power-of-two divider rounds down and the request > succeeds at a wrong rate: about 12.3 MHz from the reset PLL value, so > 48 kHz content is sent at about 24 kHz. >=20 > Propagate rate changes to the parent, like the audio codec clocks > already do. This is the same change as the one just applied for the H6 > [1]. >=20 > Link: https://lore.kernel.org/all/20261104185027.883011-1-jernej.skrabec@= gmail.com/ [1] There is no need to link to H6 patch. It's clear that patch is needed. Acked-by: Jernej Skrabec Best regards, Jernej > Fixes: 88dde5e23da1 ("clk: sunxi-ng: Add support for the Allwinner H616 C= CU") > Cc: stable@vger.kernel.org > Signed-off-by: Arun Iyengar > --- > drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-n= g/ccu-sun50i-h616.c > index d2625fec651a..f703d690a563 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c > @@ -529,7 +529,7 @@ static struct ccu_div spdif_clk =3D { > .hw.init =3D CLK_HW_INIT_PARENTS("spdif", > audio_parents, > &ccu_div_ops, > - 0), > + CLK_SET_RATE_PARENT), > }, > }; > =20 >=20 >=20