From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C094C2D0E4 for ; Tue, 17 Nov 2020 16:49:22 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AAF87221FC for ; Tue, 17 Nov 2020 16:49:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="JuB2P4OE" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AAF87221FC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=CZ0xiqBfeDiVYWqAVNg8bFbOyx8cxALPC3pjXKWVn9k=; b=JuB2P4OEeOZHWOguYbo253pab LWaZ+hoOghdrHnevGaRNXVUCBGzhUwk2TtIHvvWnVhM5tHlXSVuEiNZAz+A7DqEQFPO3E8JdQ0mIl 4/CKm29CIjMjxxWgRXBLcUZgBkRfolzJBQtzXbEoBA7xOmcBdXkuReg/Ub0V8BdX2YqVPelCCnwKF 9sEFVnsbJUR8fprI1YfbS9uk2H1VUMew9dJl2yYdqZpE9TWGEJ4rDfwdnnI5B6DpR3qMmyJpowJgy T08Vd745mB+OTba0O+BjiRMpxDiHarWPGqvRr7qDu1dwnEvXahmAN5QdT5Sa9BAFaKRQ4pmtTr3cA sAJrlPuLg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kf490-0006ir-HO; Tue, 17 Nov 2020 16:47:50 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kf48x-0006iO-Vj for linux-arm-kernel@lists.infradead.org; Tue, 17 Nov 2020 16:47:49 +0000 Received: from trantor (unknown [2.26.170.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5391F221FC; Tue, 17 Nov 2020 16:47:46 +0000 (UTC) Date: Tue, 17 Nov 2020 16:47:43 +0000 From: Catalin Marinas To: Vladimir Murzin Subject: Re: [RFC PATCH 1/2] arm64: Support execute-only permissions with Enhanced PAN Message-ID: References: <20201113152023.102855-1-vladimir.murzin@arm.com> <20201113152023.102855-2-vladimir.murzin@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201113152023.102855-2-vladimir.murzin@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201117_114748_124012_B92B2102 X-CRM114-Status: GOOD ( 16.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: keescook@chromium.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Nov 13, 2020 at 03:20:22PM +0000, Vladimir Murzin wrote: > diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h > index 4ff12a7..d1f68d2 100644 > --- a/arch/arm64/include/asm/pgtable.h > +++ b/arch/arm64/include/asm/pgtable.h > @@ -113,8 +113,15 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; > #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) > > #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) > -#define pte_valid_not_user(pte) \ > - ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID) > +#define pte_valid_not_user(pte) \ > +({ \ > + int __val; \ > + if (cpus_have_const_cap(ARM64_HAS_EPAN)) \ > + __val = (pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN); \ > + else \ > + __val = (pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID; \ > + __val; \ Is it worth having the cap check here? I'd go with the PTE_VALID|PTE_UXN check only. > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index dcc165b..2033e0b 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -1602,6 +1602,13 @@ static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) > } > #endif /* CONFIG_ARM64_PAN */ > > +#ifdef CONFIG_ARM64_EPAN > +static void cpu_enable_epan(const struct arm64_cpu_capabilities *__unused) > +{ > + sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_EPAN); > +} > +#endif /* CONFIG_ARM64_EPAN */ I checked the spec (2020 arch updates) and the EPAN bit is permitted to be cached in the TLB. I think we get away with this because this function is called before cnp is enabled. Maybe we should make it explicit and move the CnP entry last with a comment. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel