From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2E43C05027 for ; Wed, 8 Feb 2023 19:37:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DaQ3tY1F37/zjRJeRpzNUkYnlaVtrFaPtYVSw5UqHp8=; b=retS8PZhYnmygY k43eJ9w8Fu98pjUuAp+UeWOQVJ1TIOxxxz/XUFbzVP9CmYK4p1FzW3Cd6fUFBbM07OIgQtxmQic5Q tm+r1nkiAKPPZYXA1ZM5RyMSV2VVIvMaOZ7SMLGCgXi6t3/iB4E6cv5oT4CgO+Ds0WQR1945x2bTr DtYfexxMTzc0ISmsuqQt59Y1e4myuFpNZG+0gm752HA2J4f/N4t+Jl+s2NpM8/vREBfx5DARjBzl+ TOzYWvg6T7RxiFqfiAlgDAGWIoKyvzQiUoQpEUNiDxY+xn3hgrTqNNW/Vt5S5ItvThrgUnPw8zak3 I5o3/s7U7QOadx6QzRtQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pPqEl-00Gkvb-Ab; Wed, 08 Feb 2023 19:36:11 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pPqEh-00GkuQ-Tq for linux-arm-kernel@lists.infradead.org; Wed, 08 Feb 2023 19:36:09 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 956A44B3; Wed, 8 Feb 2023 11:36:46 -0800 (PST) Received: from FVFF77S0Q05N.cambridge.arm.com (FVFF77S0Q05N.cambridge.arm.com [10.1.30.155]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 62E4E3F703; Wed, 8 Feb 2023 11:36:03 -0800 (PST) Date: Wed, 8 Feb 2023 19:36:00 +0000 From: Mark Rutland To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Catalin Marinas , Will Deacon Subject: Re: [PATCH V7 5/6] arm64/perf: Add branch stack support in ARMV8 PMU Message-ID: References: <20230105031039.207972-1-anshuman.khandual@arm.com> <20230105031039.207972-6-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230208_113608_082150_671DB21E X-CRM114-Status: GOOD ( 35.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jan 13, 2023 at 10:41:51AM +0530, Anshuman Khandual wrote: > > > On 1/12/23 19:59, Mark Rutland wrote: > > On Thu, Jan 05, 2023 at 08:40:38AM +0530, Anshuman Khandual wrote: > >> @@ -878,6 +890,13 @@ static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu) > >> if (!armpmu_event_set_period(event)) > >> continue; > >> > >> + if (has_branch_stack(event)) { > >> + WARN_ON(!cpuc->branches); > >> + armv8pmu_branch_read(cpuc, event); > >> + data.br_stack = &cpuc->branches->branch_stack; > >> + data.sample_flags |= PERF_SAMPLE_BRANCH_STACK; > >> + } > > > > How do we ensure the data we're getting isn't changed under our feet? Is BRBE > > disabled at this point? > > Right, BRBE is paused after a PMU IRQ. We also ensure the buffer is disabled for > all exception levels, i.e removing BRBCR_EL1_E0BRE/E1BRE from the configuration, > before initiating the actual read, which eventually populates the data.br_stack. Ok; just to confirm, what exactly is the condition that enforces that BRBE is disabled? Is that *while* there's an overflow asserted, or does something else get set at the instant the overflow occurs? What exactly is necessary for it to start again? > > Is this going to have branches after taking the exception, or does BRBE stop > > automatically at that point? If so we presumably need to take special care as > > to when we read this relative to enabling/disabling and/or manipulating the > > overflow bits. > > The default BRBE configuration includes setting BRBCR_EL1.FZP, enabling BRBE to > be paused automatically, right after a PMU IRQ. Regardless, before reading the > buffer, BRBE is paused (BRBFCR_EL1.PAUSED) and disabled for all privilege levels > ~(BRBCR_EL1.E0BRE/E1BRE) which ensures that no new branch record is getting into > the buffer, while it is being read for perf right buffer. Ok; I think we could do with some comments as to this. > > > > >> + > >> /* > >> * Perf event overflow will queue the processing of the event as > >> * an irq_work which will be taken care of in the handling of > >> @@ -976,6 +995,14 @@ static int armv8pmu_user_event_idx(struct perf_event *event) > >> return event->hw.idx; > >> } > >> > >> +static void armv8pmu_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in) > >> +{ > >> + struct arm_pmu *armpmu = to_arm_pmu(pmu_ctx->pmu); > >> + > >> + if (sched_in && arm_pmu_branch_stack_supported(armpmu)) > >> + armv8pmu_branch_reset(); > >> +} > > > > When scheduling out, shouldn't we save what we have so far? > > > > It seems odd that we just throw that away rather than placing it into a FIFO. > > IIRC we had discussed this earlier, save and restore mechanism will be added > later, not during this enablement patch series. Sorry, but why? I don't understand why it's acceptable to non-deterministically throw away data for now. At the least that's going to confuse users, especially as the observable behaviour may change if and when that's added later. I assume that there's some reason that it's painful to do that? Could you please elaborate on that? > For now resetting the buffer ensures that branch records from one session > does not get into another. I agree that it's necessary to do that, but as above I don't believe it's sufficient. > Note that these branches cannot be pushed into perf ring buffer either, as > there was no corresponding PMU interrupt to be associated with. I'm not suggesting we put it in the perf ring buffer; I'm suggesting that we snapshot it into *some* kernel-internal storage, then later reconcile that. Maybe that's far more painful than I expect? Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel