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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Krzysztof Kozlowski , Jan Petrous , netdev@vger.kernel.org, s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Matthias Brugger , Chester Lin Subject: Re: [PATCH 2/5] dt-bindings: net: add schema for NXP S32CC dwmac glue driver Message-ID: References: <20221031101052.14956-1-clin@suse.com> <20221031101052.14956-3-clin@suse.com> <20221102155515.GA3959603-robh@kernel.org> <2a7ebef4-77cc-1c26-ec6d-86db5ee5a94b@suse.de> <20221102214456.GB459441-robh@kernel.org> Content-Disposition: inline In-Reply-To: <20221102214456.GB459441-robh@kernel.org> X-ClientProxiedBy: FR3P281CA0044.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:4a::7) To VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR0402MB3439:EE_|AS8PR04MB7814:EE_ X-MS-Office365-Filtering-Correlation-Id: 5f6de8fa-588b-4ac2-df16-08dabe4cf820 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Rob and Andreas, On Wed, Nov 02, 2022 at 04:44:56PM -0500, Rob Herring wrote: > On Wed, Nov 02, 2022 at 06:13:35PM +0100, Andreas F=E4rber wrote: > > Hi Rob, > > = > > On 02.11.22 16:55, Rob Herring wrote: > > > On Mon, Oct 31, 2022 at 06:10:49PM +0800, Chester Lin wrote: > > > > Add the DT schema for the DWMAC Ethernet controller on NXP S32 Comm= on > > > > Chassis. > > > > = > > > > Signed-off-by: Jan Petrous > > > > Signed-off-by: Chester Lin > > > > --- > > > > .../bindings/net/nxp,s32cc-dwmac.yaml | 145 +++++++++++++= +++++ > > > > 1 file changed, 145 insertions(+) > > > > create mode 100644 Documentation/devicetree/bindings/net/nxp,s32c= c-dwmac.yaml > > > > = > > > > diff --git a/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.= yaml b/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml > > > > new file mode 100644 > > > > index 000000000000..f6b8486f9d42 > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml > > > > @@ -0,0 +1,145 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > +# Copyright 2021-2022 NXP > > > > +%YAML 1.2 > > > > +--- > > > > +$id: "http://devicetree.org/schemas/net/nxp,s32cc-dwmac.yaml#" > > > > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > > > > + > > > > +title: NXP S32CC DWMAC Ethernet controller > > > > + > > > > +maintainers: > > > > + - Jan Petrous > > > > + - Chester Lin > > [...] > > > > +properties: > > > > + compatible: > > > > + contains: > > > = > > > Drop 'contains'. > > > = > > > > + enum: > > > > + - nxp,s32cc-dwmac > > = > > In the past you were adamant that we use concrete SoC-specific strings.= Here > > that would mean s32g2 or s32g274 instead of s32cc (which aims to share = with > > S32G3 IIUC). > = > Yes they should be SoC specific. Really, 1 per maskset or die is fine if = > that level of detail is known. No need for different compatibles for = > different part numbers created by fused off features or package pinout = > differences. > = If I understand correctly from NXP, the GMAC0 belongs to a common hardware sub-architecture called "S32 Common Chassis", which is a common IP set appl= ied in many S32 SoC series, such as S32G2/G3 and S32R45. Therefore this binding= is not specifically for S32G2 but it supports all S32 SoC series who adopt S32= CC sub-arch if they could all be upstreamed in the future. Logically S32G2 and S32R45 have the same subset *S32CC* but it doesn't mean= that S32G2 and S32R45 are derived from each other. Regards, Chester > > [...] > > > > + clocks: > > > > + items: > > > > + - description: Main GMAC clock > > > > + - description: Peripheral registers clock > > > > + - description: Transmit SGMII clock > > > > + - description: Transmit RGMII clock > > > > + - description: Transmit RMII clock > > > > + - description: Transmit MII clock > > > > + - description: Receive SGMII clock > > > > + - description: Receive RGMII clock > > > > + - description: Receive RMII clock > > > > + - description: Receive MII clock > > > > + - description: > > > > + PTP reference clock. This clock is used for programming = the > > > > + Timestamp Addend Register. If not passed then the system > > > > + clock will be used. > > > = > > > If optional, then you need 'minItems'. > > [snip] > > = > > Do we have any precedence of bindings with *MII clocks like these? > = > Don't know... > = > > AFAIU the reason there are so many here is that there are in fact physi= cally > > just five, but different parent clock configurations that SCMI does not > > currently expose to Linux. Thus I was raising that we may want to exten= d the > > SCMI protocol with some SET_PARENT operation that could allow us to use= less > > input clocks here, but obviously such a standardization process will ta= ke > > time... > > = > > What are your thoughts on how to best handle this here? > = > Perhaps use assigned-clocks if it is static for a board. > = > > Not clear to me has been whether the PHY mode can be switched at runtime > > (like DPAA2 on Layerscape allows for SFPs) or whether this is fixed by = board > > design. If the latter, the two out of six SCMI IDs could get selected in > > TF-A, to have only physical clocks here in the binding. > > = > > Regards, > > Andreas _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel